499 lines
26 KiB
C
499 lines
26 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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*/
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#ifndef __LINUX_REGULATOR_MT6377_H
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#define __LINUX_REGULATOR_MT6377_H
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enum {
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MT6377_ID_VBUCK1,
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MT6377_ID_VBUCK2,
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MT6377_ID_VBUCK3,
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MT6377_ID_VBUCK4,
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MT6377_ID_VBUCK5,
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MT6377_ID_VBUCK6,
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MT6377_ID_VS1,
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MT6377_ID_VS2,
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MT6377_ID_VPA,
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MT6377_ID_VBUCK3_SSHUB,
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MT6377_ID_VBUCK4_SSHUB,
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MT6377_ID_VSRAM_OTHERS_SSHUB,
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MT6377_ID_VSRAM_MD,
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MT6377_ID_VSRAM_PROC1,
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MT6377_ID_VSRAM_PROC2,
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MT6377_ID_VSRAM_OTHERS,
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MT6377_ID_VA12,
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MT6377_ID_VAUD18,
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MT6377_ID_VAUD28,
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MT6377_ID_VAUX18,
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MT6377_ID_VBIF28,
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MT6377_ID_VCN33_1,
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MT6377_ID_VCN33_2,
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MT6377_ID_VCN18,
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MT6377_ID_VRFCK,
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MT6377_ID_VBBCK,
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MT6377_ID_VXO22,
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MT6377_ID_VM18,
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MT6377_ID_VEFUSE,
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MT6377_ID_VEMC,
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MT6377_ID_VUFS,
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MT6377_ID_VIO18,
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MT6377_ID_VRF18,
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MT6377_ID_VRF12,
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MT6377_ID_VRF09,
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MT6377_ID_VRFVA12,
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MT6377_ID_VRFIO18,
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MT6377_ID_VMCH,
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MT6377_ID_VMC,
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MT6377_ID_VUSB,
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MT6377_ID_VIBR,
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MT6377_ID_VIO28,
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MT6377_ID_VFP,
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MT6377_ID_VTP,
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MT6377_ID_VMCH_EINT_HIGH,
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MT6377_ID_VMCH_EINT_LOW,
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MT6377_ID_ISINK_LOAD,
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MT6377_MAX_REGULATOR,
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};
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#define MTK_REGULATOR_MAX_NR MT6377_MAX_REGULATOR
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/* Register */
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#define MT6377_VM_MODE_ADDR (0x3c)
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#define MT6377_RG_BUCK_VBUCK1_VOSEL_ADDR (0x24d)
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#define MT6377_RG_BUCK_VBUCK1_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VBUCK2_VOSEL_ADDR (0x24e)
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#define MT6377_RG_BUCK_VBUCK2_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VBUCK3_VOSEL_ADDR (0x24f)
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#define MT6377_RG_BUCK_VBUCK3_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VBUCK4_VOSEL_ADDR (0x250)
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#define MT6377_RG_BUCK_VBUCK4_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VBUCK5_VOSEL_ADDR (0x251)
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#define MT6377_RG_BUCK_VBUCK5_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VBUCK6_VOSEL_ADDR (0x252)
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#define MT6377_RG_BUCK_VBUCK6_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VS1_VOSEL_ADDR (0x253)
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#define MT6377_RG_BUCK_VS1_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VS2_VOSEL_ADDR (0x254)
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#define MT6377_RG_BUCK_VS2_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VPA_VOSEL_ADDR (0x257)
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#define MT6377_RG_BUCK_VPA_VOSEL_MASK (0x7f)
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#define MT6377_RG_LDO_VSRAM_MD_VOSEL_ADDR (0x258)
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#define MT6377_RG_LDO_VSRAM_MD_VOSEL_MASK (0x7f)
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#define MT6377_RG_LDO_VSRAM_PROC1_VOSEL_ADDR (0x259)
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#define MT6377_RG_LDO_VSRAM_PROC1_VOSEL_MASK (0x7f)
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#define MT6377_RG_LDO_VSRAM_PROC2_VOSEL_ADDR (0x25a)
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#define MT6377_RG_LDO_VSRAM_PROC2_VOSEL_MASK (0x7f)
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#define MT6377_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR (0x25b)
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#define MT6377_RG_LDO_VSRAM_OTHERS_VOSEL_MASK (0x7f)
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#define MT6377_BUCK_VBUCK1_OP_EN_0 (0x148d)
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#define MT6377_BUCK_VBUCK2_OP_EN_0 (0x150d)
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#define MT6377_BUCK_VBUCK3_OP_EN_0 (0x158d)
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#define MT6377_BUCK_VBUCK4_OP_EN_0 (0x160d)
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#define MT6377_BUCK_VBUCK5_OP_EN_0 (0x168d)
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#define MT6377_BUCK_VBUCK6_OP_EN_0 (0x170d)
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#define MT6377_BUCK_VS1_OP_EN_0 (0x178d)
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#define MT6377_BUCK_VS2_OP_EN_0 (0x180d)
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#define MT6377_RG_BUCK_VBUCK1_EN_ADDR (0x1496)
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#define MT6377_RG_BUCK_VBUCK1_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VBUCK1_LP_ADDR (0x1496)
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#define MT6377_RG_BUCK_VBUCK1_LP_SHIFT (1)
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#define MT6377_DA_VBUCK1_EN_ADDR (0x1499)
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#define MT6377_RG_BUCK_VBUCK2_EN_ADDR (0x1516)
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#define MT6377_RG_BUCK_VBUCK2_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VBUCK2_LP_ADDR (0x1516)
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#define MT6377_RG_BUCK_VBUCK2_LP_SHIFT (1)
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#define MT6377_DA_VBUCK2_EN_ADDR (0x1519)
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#define MT6377_RG_BUCK_VBUCK3_EN_ADDR (0x1596)
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#define MT6377_RG_BUCK_VBUCK3_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VBUCK3_LP_ADDR (0x1596)
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#define MT6377_RG_BUCK_VBUCK3_LP_SHIFT (1)
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#define MT6377_DA_VBUCK3_EN_ADDR (0x1599)
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#define MT6377_RG_BUCK_VBUCK4_EN_ADDR (0x1616)
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#define MT6377_RG_BUCK_VBUCK4_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VBUCK4_LP_ADDR (0x1616)
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#define MT6377_RG_BUCK_VBUCK4_LP_SHIFT (1)
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#define MT6377_DA_VBUCK4_EN_ADDR (0x1619)
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#define MT6377_RG_BUCK_VBUCK5_EN_ADDR (0x1696)
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#define MT6377_RG_BUCK_VBUCK5_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VBUCK5_LP_ADDR (0x1696)
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#define MT6377_RG_BUCK_VBUCK5_LP_SHIFT (1)
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#define MT6377_DA_VBUCK5_EN_ADDR (0x1699)
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#define MT6377_RG_BUCK_VBUCK6_EN_ADDR (0x1716)
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#define MT6377_RG_BUCK_VBUCK6_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VBUCK6_LP_ADDR (0x1716)
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#define MT6377_RG_BUCK_VBUCK6_LP_SHIFT (1)
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#define MT6377_DA_VBUCK6_EN_ADDR (0x1719)
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#define MT6377_RG_BUCK_VS1_EN_ADDR (0x1796)
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#define MT6377_RG_BUCK_VS1_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VS1_LP_ADDR (0x1796)
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#define MT6377_RG_BUCK_VS1_LP_SHIFT (1)
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#define MT6377_DA_VS1_EN_ADDR (0x1799)
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#define MT6377_RG_BUCK_VS2_EN_ADDR (0x1816)
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#define MT6377_RG_BUCK_VS2_EN_SHIFT (0)
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#define MT6377_RG_BUCK_VS2_LP_ADDR (0x1816)
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#define MT6377_RG_BUCK_VS2_LP_SHIFT (1)
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#define MT6377_DA_VS2_EN_ADDR (0x1819)
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#define MT6377_RG_BUCK_VPA_EN_ADDR (0x243)
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#define MT6377_RG_BUCK_VPA_EN_SHIFT (3)
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#define MT6377_RG_BUCK_VPA_LP_ADDR (0x249)
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#define MT6377_RG_BUCK_VPA_LP_SHIFT (3)
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#define MT6377_RG_VBUCK5_FCCM_ADDR (0x1918)
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#define MT6377_RG_VBUCK5_FCCM_SHIFT (0)
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#define MT6377_RG_VBUCK6_FCCM_ADDR (0x1928)
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#define MT6377_RG_VBUCK6_FCCM_SHIFT (0)
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#define MT6377_RG_VS1_FCCM_ADDR (0x1938)
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#define MT6377_RG_VS1_FCCM_SHIFT (0)
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#define MT6377_RG_VS2_FCCM_ADDR (0x1948)
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#define MT6377_RG_VS2_FCCM_SHIFT (0)
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#define MT6377_RG_VPA_MODESET_ADDR (0x19c1)
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#define MT6377_RG_VPA_MODESET_SHIFT (0)
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#define MT6377_RG_VBUCK1_FCCM_ADDR (0x19b2)
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#define MT6377_RG_VBUCK1_FCCM_SHIFT (0)
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#define MT6377_RG_VBUCK2_FCCM_ADDR (0x19b2)
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#define MT6377_RG_VBUCK2_FCCM_SHIFT (1)
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#define MT6377_RG_VBUCK3_FCCM_ADDR (0x19b2)
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#define MT6377_RG_VBUCK3_FCCM_SHIFT (2)
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#define MT6377_RG_VBUCK4_FCCM_ADDR (0x19b2)
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#define MT6377_RG_VBUCK4_FCCM_SHIFT (3)
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#define MT6377_RG_VEMC_VOSEL_0_ADDR (0x1b51)
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#define MT6377_RG_VEMC_VOSEL_0_MASK (0xf)
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#define MT6377_RG_VEMC_VOCAL_0_ADDR (0x1b51)
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#define MT6377_RG_VEMC_VOCAL_0_MASK (0xf0)
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#define MT6377_RG_LDO_VA12_EN_ADDR (0x1b87)
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#define MT6377_RG_LDO_VA12_EN_SHIFT (0)
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#define MT6377_RG_LDO_VA12_LP_ADDR (0x1b87)
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#define MT6377_RG_LDO_VA12_LP_SHIFT (1)
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#define MT6377_DA_VA12_B_LP_ADDR (0x1b8b)
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#define MT6377_RG_LDO_VAUD18_EN_ADDR (0x1b95)
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#define MT6377_RG_LDO_VAUD18_EN_SHIFT (0)
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#define MT6377_RG_LDO_VAUD18_LP_ADDR (0x1b95)
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#define MT6377_RG_LDO_VAUD18_LP_SHIFT (1)
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#define MT6377_DA_VAUD18_B_LP_ADDR (0x1b99)
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#define MT6377_RG_LDO_VAUD28_EN_ADDR (0x1ba3)
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#define MT6377_RG_LDO_VAUD28_EN_SHIFT (0)
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#define MT6377_RG_LDO_VAUD28_LP_ADDR (0x1ba3)
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#define MT6377_RG_LDO_VAUD28_LP_SHIFT (1)
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#define MT6377_DA_VAUD28_B_LP_ADDR (0x1ba7)
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#define MT6377_RG_LDO_VAUX18_EN_ADDR (0x1bb1)
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#define MT6377_RG_LDO_VAUX18_EN_SHIFT (0)
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#define MT6377_RG_LDO_VAUX18_LP_ADDR (0x1bb1)
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#define MT6377_RG_LDO_VAUX18_LP_SHIFT (1)
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#define MT6377_DA_VAUX18_B_LP_ADDR (0x1bb5)
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#define MT6377_RG_LDO_VBIF28_EN_ADDR (0x1bbf)
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#define MT6377_RG_LDO_VBIF28_EN_SHIFT (0)
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#define MT6377_RG_LDO_VBIF28_LP_ADDR (0x1bbf)
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#define MT6377_RG_LDO_VBIF28_LP_SHIFT (1)
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#define MT6377_DA_VBIF28_B_LP_ADDR (0x1bc3)
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#define MT6377_RG_LDO_VCN33_1_EN_ADDR (0x1bcd)
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#define MT6377_RG_LDO_VCN33_1_EN_SHIFT (0)
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#define MT6377_RG_LDO_VCN33_1_LP_ADDR (0x1bcd)
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#define MT6377_RG_LDO_VCN33_1_LP_SHIFT (1)
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#define MT6377_DA_VCN33_1_B_LP_ADDR (0x1bd1)
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#define MT6377_RG_LDO_VCN33_2_EN_ADDR (0x1c07)
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#define MT6377_RG_LDO_VCN33_2_EN_SHIFT (0)
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#define MT6377_RG_LDO_VCN33_2_LP_ADDR (0x1c07)
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#define MT6377_RG_LDO_VCN33_2_LP_SHIFT (1)
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#define MT6377_DA_VCN33_2_B_LP_ADDR (0x1c0b)
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#define MT6377_RG_LDO_VCN18_EN_ADDR (0x1c15)
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#define MT6377_RG_LDO_VCN18_EN_SHIFT (0)
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#define MT6377_RG_LDO_VCN18_LP_ADDR (0x1c15)
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#define MT6377_RG_LDO_VCN18_LP_SHIFT (1)
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#define MT6377_DA_VCN18_B_LP_ADDR (0x1c19)
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#define MT6377_RG_LDO_VRFCK_EN_ADDR (0x1c23)
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#define MT6377_RG_LDO_VRFCK_EN_SHIFT (0)
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#define MT6377_RG_LDO_VRFCK_LP_ADDR (0x1c23)
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#define MT6377_RG_LDO_VRFCK_LP_SHIFT (1)
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#define MT6377_DA_VRFCK_B_LP_ADDR (0x1c27)
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#define MT6377_RG_LDO_VBBCK_EN_ADDR (0x1c31)
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#define MT6377_RG_LDO_VBBCK_EN_SHIFT (0)
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#define MT6377_RG_LDO_VBBCK_LP_ADDR (0x1c31)
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#define MT6377_RG_LDO_VBBCK_LP_SHIFT (1)
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#define MT6377_DA_VBBCK_B_LP_ADDR (0x1c35)
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#define MT6377_RG_LDO_VXO22_EN_ADDR (0x1c3f)
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#define MT6377_RG_LDO_VXO22_EN_SHIFT (0)
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#define MT6377_RG_LDO_VXO22_LP_ADDR (0x1c3f)
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#define MT6377_RG_LDO_VXO22_LP_SHIFT (1)
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#define MT6377_DA_VXO22_B_LP_ADDR (0x1c43)
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#define MT6377_RG_LDO_VM18_EN_ADDR (0x1c4d)
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#define MT6377_RG_LDO_VM18_EN_SHIFT (0)
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#define MT6377_RG_LDO_VM18_LP_ADDR (0x1c4d)
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#define MT6377_RG_LDO_VM18_LP_SHIFT (1)
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#define MT6377_DA_VM18_B_LP_ADDR (0x1c51)
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#define MT6377_RG_LDO_VEFUSE_EN_ADDR (0x1ca3)
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#define MT6377_RG_LDO_VEFUSE_EN_SHIFT (0)
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#define MT6377_RG_LDO_VEFUSE_LP_ADDR (0x1ca3)
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#define MT6377_RG_LDO_VEFUSE_LP_SHIFT (1)
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#define MT6377_DA_VEFUSE_B_LP_ADDR (0x1ca7)
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#define MT6377_RG_LDO_VEMC_EN_ADDR (0x1cb1)
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#define MT6377_RG_LDO_VEMC_EN_SHIFT (0)
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#define MT6377_RG_LDO_VEMC_LP_ADDR (0x1cb1)
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#define MT6377_RG_LDO_VEMC_LP_SHIFT (1)
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#define MT6377_DA_VEMC_B_LP_ADDR (0x1cb5)
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#define MT6377_RG_LDO_VUFS_EN_ADDR (0x1cbf)
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#define MT6377_RG_LDO_VUFS_EN_SHIFT (0)
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#define MT6377_RG_LDO_VUFS_LP_ADDR (0x1cbf)
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#define MT6377_RG_LDO_VUFS_LP_SHIFT (1)
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#define MT6377_DA_VUFS_B_LP_ADDR (0x1cc3)
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#define MT6377_RG_LDO_VIO18_EN_ADDR (0x1ccd)
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#define MT6377_RG_LDO_VIO18_EN_SHIFT (0)
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#define MT6377_RG_LDO_VIO18_LP_ADDR (0x1ccd)
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#define MT6377_RG_LDO_VIO18_LP_SHIFT (1)
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#define MT6377_DA_VIO18_B_LP_ADDR (0x1cd1)
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#define MT6377_RG_LDO_VRF18_EN_ADDR (0x1d07)
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#define MT6377_RG_LDO_VRF18_EN_SHIFT (0)
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#define MT6377_RG_LDO_VRF18_LP_ADDR (0x1d07)
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#define MT6377_RG_LDO_VRF18_LP_SHIFT (1)
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#define MT6377_DA_VRF18_B_LP_ADDR (0x1d0b)
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#define MT6377_RG_LDO_VRF12_EN_ADDR (0x1d15)
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#define MT6377_RG_LDO_VRF12_EN_SHIFT (0)
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#define MT6377_RG_LDO_VRF12_LP_ADDR (0x1d15)
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#define MT6377_RG_LDO_VRF12_LP_SHIFT (1)
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#define MT6377_DA_VRF12_B_LP_ADDR (0x1d19)
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#define MT6377_RG_LDO_VRF09_EN_ADDR (0x1d23)
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#define MT6377_RG_LDO_VRF09_EN_SHIFT (0)
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#define MT6377_RG_LDO_VRF09_LP_ADDR (0x1d23)
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#define MT6377_RG_LDO_VRF09_LP_SHIFT (1)
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#define MT6377_DA_VRF09_B_LP_ADDR (0x1d27)
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#define MT6377_RG_LDO_VRFVA12_EN_ADDR (0x1d31)
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#define MT6377_RG_LDO_VRFVA12_EN_SHIFT (0)
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#define MT6377_RG_LDO_VRFVA12_LP_ADDR (0x1d31)
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#define MT6377_RG_LDO_VRFVA12_LP_SHIFT (1)
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#define MT6377_DA_VRFVA12_B_LP_ADDR (0x1d35)
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#define MT6377_RG_LDO_VRFIO18_EN_ADDR (0x1d3f)
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#define MT6377_RG_LDO_VRFIO18_EN_SHIFT (0)
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#define MT6377_RG_LDO_VRFIO18_LP_ADDR (0x1d3f)
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#define MT6377_RG_LDO_VRFIO18_LP_SHIFT (1)
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#define MT6377_DA_VRFIO18_B_LP_ADDR (0x1d43)
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#define MT6377_RG_LDO_VMCH_EN_ADDR (0x1d4d)
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#define MT6377_RG_LDO_VMCH_EN_SHIFT (0)
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#define MT6377_RG_LDO_VMCH_LP_ADDR (0x1d4d)
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#define MT6377_RG_LDO_VMCH_LP_SHIFT (1)
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#define MT6377_DA_VMCH_B_LP_ADDR (0x1d51)
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#define MT6377_RG_LDO_VMC_EN_ADDR (0x1d87)
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#define MT6377_RG_LDO_VMC_EN_SHIFT (0)
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#define MT6377_RG_LDO_VMC_LP_ADDR (0x1d87)
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#define MT6377_RG_LDO_VMC_LP_SHIFT (1)
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#define MT6377_DA_VMC_B_LP_ADDR (0x1d8b)
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#define MT6377_RG_LDO_VSIM1_EN_ADDR (0x1d95)
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#define MT6377_RG_LDO_VSIM1_EN_SHIFT (0)
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#define MT6377_RG_LDO_VSIM1_LP_ADDR (0x1d95)
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#define MT6377_RG_LDO_VSIM1_LP_SHIFT (1)
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#define MT6377_DA_VSIM1_B_LP_ADDR (0x1d99)
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#define MT6377_RG_LDO_VSIM2_EN_ADDR (0x1da4)
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#define MT6377_RG_LDO_VSIM2_EN_SHIFT (0)
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#define MT6377_RG_LDO_VSIM2_LP_ADDR (0x1da4)
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#define MT6377_RG_LDO_VSIM2_LP_SHIFT (1)
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#define MT6377_DA_VSIM2_B_LP_ADDR (0x1da8)
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#define MT6377_RG_LDO_VUSB_EN_ADDR (0x1db3)
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#define MT6377_RG_LDO_VUSB_EN_SHIFT (0)
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#define MT6377_RG_LDO_VUSB_LP_ADDR (0x1db3)
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#define MT6377_RG_LDO_VUSB_LP_SHIFT (1)
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#define MT6377_DA_VUSB_B_LP_ADDR (0x1db7)
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#define MT6377_RG_LDO_VIBR_EN_ADDR (0x1dc1)
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#define MT6377_RG_LDO_VIBR_EN_SHIFT (0)
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#define MT6377_RG_LDO_VIBR_LP_ADDR (0x1dc1)
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#define MT6377_RG_LDO_VIBR_LP_SHIFT (1)
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#define MT6377_DA_VIBR_B_LP_ADDR (0x1dc5)
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#define MT6377_RG_LDO_VIO28_EN_ADDR (0x1dcf)
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#define MT6377_RG_LDO_VIO28_EN_SHIFT (0)
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#define MT6377_RG_LDO_VIO28_LP_ADDR (0x1dcf)
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#define MT6377_RG_LDO_VIO28_LP_SHIFT (1)
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#define MT6377_DA_VIO28_B_LP_ADDR (0x1dd3)
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#define MT6377_RG_LDO_VFP_EN_ADDR (0x1e07)
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#define MT6377_RG_LDO_VFP_EN_SHIFT (0)
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#define MT6377_RG_LDO_VFP_LP_ADDR (0x1e07)
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#define MT6377_RG_LDO_VFP_LP_SHIFT (1)
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#define MT6377_DA_VFP_B_LP_ADDR (0x1e0b)
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#define MT6377_RG_LDO_VTP_EN_ADDR (0x1e15)
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#define MT6377_RG_LDO_VTP_EN_SHIFT (0)
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#define MT6377_RG_LDO_VTP_LP_ADDR (0x1e15)
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#define MT6377_RG_LDO_VTP_LP_SHIFT (1)
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#define MT6377_DA_VTP_B_LP_ADDR (0x1e19)
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#define MT6377_RG_LDO_VSRAM_MD_EN_ADDR (0x1e87)
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#define MT6377_RG_LDO_VSRAM_MD_EN_SHIFT (0)
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#define MT6377_RG_LDO_VSRAM_MD_LP_ADDR (0x1e87)
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#define MT6377_RG_LDO_VSRAM_MD_LP_SHIFT (1)
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#define MT6377_DA_VSRAM_MD_B_LP_ADDR (0x1e8b)
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#define MT6377_LDO_VSRAM_MD_WDTDBG_VOSEL_ADDR (0x1e8e)
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#define MT6377_RG_LDO_VSRAM_PROC1_EN_ADDR (0x1e9d)
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#define MT6377_RG_LDO_VSRAM_PROC1_EN_SHIFT (0)
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#define MT6377_RG_LDO_VSRAM_PROC1_LP_ADDR (0x1e9d)
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#define MT6377_RG_LDO_VSRAM_PROC1_LP_SHIFT (1)
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#define MT6377_DA_VSRAM_PROC1_B_LP_ADDR (0x1ea1)
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#define MT6377_LDO_VSRAM_PROC1_WDTDBG_VOSEL_ADDR (0x1ea4)
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#define MT6377_RG_LDO_VSRAM_PROC2_EN_ADDR (0x1f07)
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#define MT6377_RG_LDO_VSRAM_PROC2_EN_SHIFT (0)
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#define MT6377_RG_LDO_VSRAM_PROC2_LP_ADDR (0x1f07)
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#define MT6377_RG_LDO_VSRAM_PROC2_LP_SHIFT (1)
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#define MT6377_DA_VSRAM_PROC2_B_LP_ADDR (0x1f0b)
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#define MT6377_LDO_VSRAM_PROC2_WDTDBG_VOSEL_ADDR (0x1f0e)
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#define MT6377_RG_LDO_VSRAM_OTHERS_EN_ADDR (0x1f1d)
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#define MT6377_RG_LDO_VSRAM_OTHERS_EN_SHIFT (0)
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#define MT6377_RG_LDO_VSRAM_OTHERS_LP_ADDR (0x1f1d)
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#define MT6377_RG_LDO_VSRAM_OTHERS_LP_SHIFT (1)
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#define MT6377_DA_VSRAM_OTHERS_B_LP_ADDR (0x1f21)
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#define MT6377_LDO_VSRAM_OTHERS_WDTDBG_VOSEL_ADDR (0x1f24)
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#define MT6377_LDO_VA12_OP_EN0 (0x1b8c)
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#define MT6377_LDO_VAUD18_OP_EN0 (0x1b9a)
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#define MT6377_LDO_VAUD28_OP_EN0 (0x1ba8)
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#define MT6377_LDO_VAUX18_OP_EN0 (0x1bb6)
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#define MT6377_LDO_VBIF28_OP_EN0 (0x1bc4)
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#define MT6377_LDO_VCN33_1_OP_EN0 (0x1bd2)
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#define MT6377_LDO_VCN33_2_OP_EN0 (0x1c0c)
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#define MT6377_LDO_VCN18_OP_EN0 (0x1c1a)
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#define MT6377_LDO_VRFCK_OP_EN0 (0x1c28)
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#define MT6377_LDO_VBBCK_OP_EN0 (0x1c36)
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#define MT6377_LDO_VXO22_OP_EN0 (0x1c44)
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#define MT6377_LDO_VM18_OP_EN0 (0x1c52)
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#define MT6377_LDO_VEFUSE_OP_EN0 (0x1ca8)
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#define MT6377_LDO_VEMC_OP_EN0 (0x1cb6)
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#define MT6377_LDO_VUFS_OP_EN0 (0x1cc4)
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#define MT6377_LDO_VIO18_OP_EN0 (0x1cd2)
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#define MT6377_LDO_VRF18_OP_EN0 (0x1d0c)
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#define MT6377_LDO_VRF12_OP_EN0 (0x1d1a)
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#define MT6377_LDO_VRF09_OP_EN0 (0x1d28)
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#define MT6377_LDO_VRFVA12_OP_EN0 (0x1d36)
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#define MT6377_LDO_VRFIO18_OP_EN0 (0x1d44)
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#define MT6377_LDO_VMCH_OP_EN0 (0x1d52)
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#define MT6377_LDO_VMC_OP_EN0 (0x1d8c)
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#define MT6377_LDO_VSIM1_OP_EN0 (0x1d9a)
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#define MT6377_LDO_VSIM2_OP_EN0 (0x1da9)
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#define MT6377_LDO_VUSB_OP_EN0 (0x1db8)
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#define MT6377_LDO_VIBR_OP_EN0 (0x1dc6)
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#define MT6377_LDO_VIO28_OP_EN0 (0x1dd4)
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#define MT6377_LDO_VFP_OP_EN0 (0x1e0c)
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#define MT6377_LDO_VTP_OP_EN0 (0x1e1a)
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#define MT6377_RG_VAUD28_VOCAL_ADDR (0x1f88)
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#define MT6377_RG_VAUD28_VOCAL_MASK (0xf)
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#define MT6377_RG_VAUD28_VOSEL_ADDR (0x1f89)
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#define MT6377_RG_VAUD28_VOSEL_MASK (0xf)
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#define MT6377_RG_VAUX18_VOCAL_ADDR (0x1f8b)
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#define MT6377_RG_VAUX18_VOCAL_MASK (0xf)
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#define MT6377_RG_VAUX18_VOSEL_ADDR (0x1f8c)
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#define MT6377_RG_VAUX18_VOSEL_MASK (0xf)
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#define MT6377_RG_VBIF28_VOCAL_ADDR (0x1f91)
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#define MT6377_RG_VBIF28_VOCAL_MASK (0xf)
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#define MT6377_RG_VBIF28_VOSEL_ADDR (0x1f92)
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#define MT6377_RG_VBIF28_VOSEL_MASK (0xf)
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#define MT6377_RG_VCN33_1_VOCAL_ADDR (0x1f94)
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#define MT6377_RG_VCN33_1_VOCAL_MASK (0xf)
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#define MT6377_RG_VCN33_1_VOSEL_ADDR (0x1f95)
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#define MT6377_RG_VCN33_1_VOSEL_MASK (0xf)
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#define MT6377_RG_VCN33_2_VOCAL_ADDR (0x1f98)
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#define MT6377_RG_VCN33_2_VOCAL_MASK (0xf)
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#define MT6377_RG_VCN33_2_VOSEL_ADDR (0x1f99)
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#define MT6377_RG_VCN33_2_VOSEL_MASK (0xf)
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#define MT6377_RG_VSIM1_VOCAL_ADDR (0x1f9e)
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#define MT6377_RG_VSIM1_VOCAL_MASK (0xf)
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#define MT6377_RG_VSIM1_VOSEL_ADDR (0x1f9f)
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#define MT6377_RG_VSIM1_VOSEL_MASK (0xf)
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#define MT6377_RG_VSIM2_VOCAL_ADDR (0x1fa1)
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#define MT6377_RG_VSIM2_VOCAL_MASK (0xf)
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#define MT6377_RG_VSIM2_VOSEL_ADDR (0x1fa2)
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#define MT6377_RG_VSIM2_VOSEL_MASK (0xf)
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#define MT6377_RG_VIO28_VOCAL_ADDR (0x1fa4)
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#define MT6377_RG_VIO28_VOCAL_MASK (0xf)
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#define MT6377_RG_VIO28_VOSEL_ADDR (0x1fa5)
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#define MT6377_RG_VIO28_VOSEL_MASK (0xf)
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#define MT6377_RG_VIBR_VOCAL_ADDR (0x1fa8)
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#define MT6377_RG_VIBR_VOCAL_MASK (0xf)
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#define MT6377_RG_VIBR_VOSEL_ADDR (0x1fa9)
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#define MT6377_RG_VIBR_VOSEL_MASK (0xf)
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#define MT6377_RG_VMCH_VOCAL_ADDR (0x1fad)
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#define MT6377_RG_VMCH_VOCAL_MASK (0xf)
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#define MT6377_RG_VMCH_VOSEL_ADDR (0x1fae)
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#define MT6377_RG_VMCH_VOSEL_MASK (0xf)
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#define MT6377_RG_VMC_VOCAL_ADDR (0x1fb1)
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#define MT6377_RG_VMC_VOCAL_MASK (0xf)
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#define MT6377_RG_VMC_VOSEL_ADDR (0x1fb2)
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#define MT6377_RG_VMC_VOSEL_MASK (0xf)
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#define MT6377_RG_VFP_VOCAL_ADDR (0x1fb4)
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#define MT6377_RG_VFP_VOCAL_MASK (0xf)
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#define MT6377_RG_VFP_VOSEL_ADDR (0x1fb5)
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#define MT6377_RG_VFP_VOSEL_MASK (0xf)
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#define MT6377_RG_VTP_VOCAL_ADDR (0x1fb8)
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#define MT6377_RG_VTP_VOCAL_MASK (0xf)
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#define MT6377_RG_VTP_VOSEL_ADDR (0x1fb9)
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#define MT6377_RG_VTP_VOSEL_MASK (0xf)
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#define MT6377_RG_VRF18_VOCAL_ADDR (0x2008)
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#define MT6377_RG_VRF18_VOCAL_MASK (0xf)
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#define MT6377_RG_VRF18_VOSEL_ADDR (0x2009)
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#define MT6377_RG_VRF18_VOSEL_MASK (0xf)
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#define MT6377_RG_VEFUSE_VOCAL_ADDR (0x200b)
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#define MT6377_RG_VEFUSE_VOCAL_MASK (0xf)
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#define MT6377_RG_VEFUSE_VOSEL_ADDR (0x200c)
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#define MT6377_RG_VEFUSE_VOSEL_MASK (0xf)
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#define MT6377_RG_VCN18_VOCAL_ADDR (0x200e)
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#define MT6377_RG_VCN18_VOCAL_MASK (0xf)
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#define MT6377_RG_VCN18_VOSEL_ADDR (0x200f)
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#define MT6377_RG_VCN18_VOSEL_MASK (0xf)
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#define MT6377_RG_VRFIO18_VOCAL_ADDR (0x2011)
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#define MT6377_RG_VRFIO18_VOCAL_MASK (0xf)
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#define MT6377_RG_VRFIO18_VOSEL_ADDR (0x2012)
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#define MT6377_RG_VRFIO18_VOSEL_MASK (0xf)
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#define MT6377_RG_VAUD18_VOCAL_ADDR (0x2014)
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#define MT6377_RG_VAUD18_VOCAL_MASK (0xf)
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#define MT6377_RG_VAUD18_VOSEL_ADDR (0x2015)
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#define MT6377_RG_VAUD18_VOSEL_MASK (0xf)
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#define MT6377_RG_VIO18_VOCAL_ADDR (0x2017)
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#define MT6377_RG_VIO18_VOCAL_MASK (0xf)
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#define MT6377_RG_VIO18_VOSEL_ADDR (0x2018)
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#define MT6377_RG_VIO18_VOSEL_MASK (0xf)
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#define MT6377_RG_VM18_VOCAL_ADDR (0x201a)
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#define MT6377_RG_VM18_VOCAL_MASK (0xf)
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#define MT6377_RG_VM18_VOSEL_ADDR (0x201b)
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#define MT6377_RG_VM18_VOSEL_MASK (0xf)
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#define MT6377_RG_VUFS_VOCAL_ADDR (0x201d)
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#define MT6377_RG_VUFS_VOCAL_MASK (0xf)
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#define MT6377_RG_VUFS_VOSEL_ADDR (0x201e)
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#define MT6377_RG_VUFS_VOSEL_MASK (0xf)
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#define MT6377_RG_VRF12_VOCAL_ADDR (0x202a)
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#define MT6377_RG_VRF12_VOCAL_MASK (0xf)
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#define MT6377_RG_VRF12_VOSEL_ADDR (0x202b)
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#define MT6377_RG_VRF12_VOSEL_MASK (0xf)
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#define MT6377_RG_VRF09_VOCAL_ADDR (0x202e)
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#define MT6377_RG_VRF09_VOCAL_MASK (0xf)
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#define MT6377_RG_VRF09_VOSEL_ADDR (0x202f)
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#define MT6377_RG_VRF09_VOSEL_MASK (0xf)
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#define MT6377_RG_VRFVA12_VOCAL_ADDR (0x2033)
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#define MT6377_RG_VRFVA12_VOCAL_MASK (0xf)
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#define MT6377_RG_VRFVA12_VOSEL_ADDR (0x2034)
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#define MT6377_RG_VRFVA12_VOSEL_MASK (0xf)
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#define MT6377_RG_VA12_VOCAL_ADDR (0x2051)
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#define MT6377_RG_VA12_VOCAL_MASK (0xf0)
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#define MT6377_RG_VA12_VOSEL_ADDR (0x2052)
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#define MT6377_RG_VA12_VOSEL_MASK (0xf)
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#define MT6377_RG_VXO22_VOCAL_ADDR (0x2088)
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#define MT6377_RG_VXO22_VOCAL_MASK (0xf)
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#define MT6377_RG_VXO22_VOSEL_ADDR (0x2088)
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#define MT6377_RG_VXO22_VOSEL_MASK (0xf0)
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#define MT6377_RG_VRFCK_VOCAL_ADDR (0x208a)
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#define MT6377_RG_VRFCK_VOCAL_MASK (0xf)
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#define MT6377_RG_VBBCK_VOCAL_ADDR (0)
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#define MT6377_RG_VBBCK_VOCAL_MASK (0)
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#define MT6377_RG_VRFCK_VOSEL_ADDR (0x208b)
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#define MT6377_RG_VRFCK_VOSEL_MASK (0xf)
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#define MT6377_RG_VBBCK_VOSEL_ADDR (0x2092)
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#define MT6377_RG_VBBCK_VOSEL_MASK (0xf)
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#define MT6377_RG_BUCK_VBUCK3_SSHUB_EN_ADDR (0x159b)
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#define MT6377_RG_BUCK_VBUCK4_SSHUB_EN_ADDR (0x161b)
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#define MT6377_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR (0x1f33)
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#define MT6377_RG_BUCK_VBUCK3_SSHUB_VOSEL_ADDR (0x159c)
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#define MT6377_RG_BUCK_VBUCK3_SSHUB_VOSEL_MASK (0xff)
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#define MT6377_RG_BUCK_VBUCK4_SSHUB_VOSEL_ADDR (0x161c)
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#define MT6377_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK (0xff)
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#define MT6377_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR (0x1f33)
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#define MT6377_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK (0xfe)
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#define MT6377_LDO_VMCH_EINT (0x1d5b)
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#define MT6377_PMIC_RG_LDO_VMCH_EINT_EN_MASK (0x1)
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#define MT6377_PMIC_RG_LDO_VMCH_EINT_POL_MASK (0x4)
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#define MT6377_PMIC_RG_LDO_VMCH_EINT_DB_MASK (0x10)
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#define MT6377_ISINK_EN_CTRL0 (0x220b)
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#define MT6377_ISINK_EN_CTRL1 (0x220c)
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#endif /* __LINUX_REGULATOR_MT6377_H */
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