253 lines
12 KiB
C
253 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __LINUX_REGULATOR_MT6368_H
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#define __LINUX_REGULATOR_MT6368_H
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enum {
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MT6368_ID_VBUCK1,
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MT6368_ID_VBUCK2,
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MT6368_ID_VBUCK3,
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MT6368_ID_VBUCK4,
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MT6368_ID_VBUCK5,
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MT6368_ID_VBUCK6,
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MT6368_ID_VPA,
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MT6368_ID_VUSB,
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MT6368_ID_VAUX18,
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MT6368_ID_VRF13_AIF,
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MT6368_ID_VRF18_AIF,
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MT6368_ID_VANT18,
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MT6368_ID_VIBR,
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MT6368_ID_VIO28,
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MT6368_ID_VFP,
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MT6368_ID_VTP,
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MT6368_ID_VMCH,
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MT6368_ID_VMC,
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MT6368_ID_VAUD18,
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MT6368_ID_VCN33_1,
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MT6368_ID_VCN33_2,
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MT6368_ID_VEFUSE,
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MT6368_ID_VMCH_EINT_HIGH,
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MT6368_ID_VMCH_EINT_LOW,
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MT6368_MAX_REGULATOR,
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};
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/* Register */
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#define MT6368_TOP_CFG_ELR5 0x14b
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#define MT6368_PMIC_RG_BUCK_VBUCK1_EN_ADDR 0x240
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#define MT6368_PMIC_RG_BUCK_VBUCK1_EN_SHIFT 1
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#define MT6368_PMIC_RG_BUCK_VBUCK2_EN_ADDR 0x240
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#define MT6368_PMIC_RG_BUCK_VBUCK2_EN_SHIFT 2
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#define MT6368_PMIC_RG_BUCK_VBUCK3_EN_ADDR 0x240
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#define MT6368_PMIC_RG_BUCK_VBUCK3_EN_SHIFT 3
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#define MT6368_PMIC_RG_BUCK_VBUCK4_EN_ADDR 0x240
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#define MT6368_PMIC_RG_BUCK_VBUCK4_EN_SHIFT 4
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#define MT6368_PMIC_RG_BUCK_VBUCK5_EN_ADDR 0x240
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#define MT6368_PMIC_RG_BUCK_VBUCK5_EN_SHIFT 5
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#define MT6368_PMIC_RG_BUCK_VBUCK6_EN_ADDR 0x240
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#define MT6368_PMIC_RG_BUCK_VBUCK6_EN_SHIFT 6
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#define MT6368_PMIC_RG_BUCK_VPA_EN_ADDR 0x243
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#define MT6368_PMIC_RG_BUCK_VPA_EN_SHIFT 3
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#define MT6368_PMIC_RG_BUCK_VBUCK1_LP_ADDR 0x246
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#define MT6368_PMIC_RG_BUCK_VBUCK1_LP_SHIFT 1
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#define MT6368_PMIC_RG_BUCK_VBUCK2_LP_ADDR 0x246
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#define MT6368_PMIC_RG_BUCK_VBUCK2_LP_SHIFT 2
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#define MT6368_PMIC_RG_BUCK_VBUCK3_LP_ADDR 0x246
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#define MT6368_PMIC_RG_BUCK_VBUCK3_LP_SHIFT 3
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#define MT6368_PMIC_RG_BUCK_VBUCK4_LP_ADDR 0x246
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#define MT6368_PMIC_RG_BUCK_VBUCK4_LP_SHIFT 4
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#define MT6368_PMIC_RG_BUCK_VBUCK5_LP_ADDR 0x246
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#define MT6368_PMIC_RG_BUCK_VBUCK5_LP_SHIFT 5
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#define MT6368_PMIC_RG_BUCK_VBUCK6_LP_ADDR 0x246
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#define MT6368_PMIC_RG_BUCK_VBUCK6_LP_SHIFT 6
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#define MT6368_PMIC_RG_BUCK_VPA_LP_ADDR 0x249
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#define MT6368_PMIC_RG_BUCK_VPA_LP_SHIFT 3
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#define MT6368_PMIC_RG_BUCK_VBUCK1_VOSEL_ADDR 0x24d
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#define MT6368_PMIC_RG_BUCK_VBUCK1_VOSEL_MASK 0xFF
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#define MT6368_PMIC_RG_BUCK_VBUCK2_VOSEL_ADDR 0x24e
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#define MT6368_PMIC_RG_BUCK_VBUCK2_VOSEL_MASK 0xFF
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#define MT6368_PMIC_RG_BUCK_VBUCK3_VOSEL_ADDR 0x24f
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#define MT6368_PMIC_RG_BUCK_VBUCK3_VOSEL_MASK 0xFF
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#define MT6368_PMIC_RG_BUCK_VBUCK4_VOSEL_ADDR 0x250
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#define MT6368_PMIC_RG_BUCK_VBUCK4_VOSEL_MASK 0xFF
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#define MT6368_PMIC_RG_BUCK_VBUCK5_VOSEL_ADDR 0x251
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#define MT6368_PMIC_RG_BUCK_VBUCK5_VOSEL_MASK 0xFF
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#define MT6368_PMIC_RG_BUCK_VBUCK6_VOSEL_ADDR 0x252
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#define MT6368_PMIC_RG_BUCK_VBUCK6_VOSEL_MASK 0xFF
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#define MT6368_PMIC_RG_BUCK_VPA_VOSEL_ADDR 0x257
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#define MT6368_PMIC_RG_BUCK_VPA_VOSEL_MASK 0x7F
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#define MT6368_BUCK_TOP_KEY_PROT_LO 0x1421
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#define MT6368_PMIC_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR 0x1423
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#define MT6368_PMIC_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR 0x1424
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#define MT6368_PMIC_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR 0x1425
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#define MT6368_PMIC_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR 0x1426
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#define MT6368_PMIC_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR 0x1427
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#define MT6368_PMIC_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR 0x1428
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#define MT6368_PMIC_BUCK_VPA_WDTDBG_VOSEL_ADDR 0x1429
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#define MT6368_PMIC_RG_VBUCK1_FCCM_ADDR 0x1833
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#define MT6368_PMIC_RG_VBUCK1_FCCM_SHIFT 0
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#define MT6368_PMIC_RG_VBUCK2_FCCM_ADDR 0x1833
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#define MT6368_PMIC_RG_VBUCK2_FCCM_SHIFT 1
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#define MT6368_PMIC_RG_VBUCK3_FCCM_ADDR 0x1833
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#define MT6368_PMIC_RG_VBUCK3_FCCM_SHIFT 2
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#define MT6368_PMIC_RG_VBUCK4_FCCM_ADDR 0x1833
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#define MT6368_PMIC_RG_VBUCK4_FCCM_SHIFT 3
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#define MT6368_PMIC_RG_VBUCK5_FCCM_ADDR 0x1893
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#define MT6368_PMIC_RG_VBUCK5_FCCM_SHIFT 0
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#define MT6368_PMIC_RG_VBUCK6_FCCM_ADDR 0x18a2
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#define MT6368_PMIC_RG_VBUCK6_FCCM_SHIFT 0
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#define MT6368_PMIC_RG_VPA_MODESET_ADDR 0x18a6
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#define MT6368_PMIC_RG_VPA_MODESET_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VSIM1_EN_ADDR 0x1b87
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#define MT6368_PMIC_RG_LDO_VSIM1_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VSIM1_LP_ADDR 0x1b87
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#define MT6368_PMIC_RG_LDO_VSIM1_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VSIM2_EN_ADDR 0x1b96
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#define MT6368_PMIC_RG_LDO_VSIM2_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VSIM2_LP_ADDR 0x1b96
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#define MT6368_PMIC_RG_LDO_VSIM2_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VMDDR_EN_ADDR 0x1ba5
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#define MT6368_PMIC_RG_LDO_VMDDR_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VMDDR_LP_ADDR 0x1ba5
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#define MT6368_PMIC_RG_LDO_VMDDR_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VMDDQ_EN_ADDR 0x1bb3
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#define MT6368_PMIC_RG_LDO_VMDDQ_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VMDDQ_LP_ADDR 0x1bb3
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#define MT6368_PMIC_RG_LDO_VMDDQ_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VUSB_EN_ADDR 0x1bc1
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#define MT6368_PMIC_RG_LDO_VUSB_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VUSB_LP_ADDR 0x1bc1
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#define MT6368_PMIC_RG_LDO_VUSB_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VAUX18_EN_ADDR 0x1bcf
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#define MT6368_PMIC_RG_LDO_VAUX18_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VAUX18_LP_ADDR 0x1bcf
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#define MT6368_PMIC_RG_LDO_VAUX18_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VRF13_AIF_EN_ADDR 0x1c07
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#define MT6368_PMIC_RG_LDO_VRF13_AIF_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VRF13_AIF_LP_ADDR 0x1c07
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#define MT6368_PMIC_RG_LDO_VRF13_AIF_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VRF18_AIF_EN_ADDR 0x1c15
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#define MT6368_PMIC_RG_LDO_VRF18_AIF_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VRF18_AIF_LP_ADDR 0x1c15
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#define MT6368_PMIC_RG_LDO_VRF18_AIF_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VANT18_EN_ADDR 0x1c23
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#define MT6368_PMIC_RG_LDO_VANT18_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VANT18_LP_ADDR 0x1c23
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#define MT6368_PMIC_RG_LDO_VANT18_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VIBR_EN_ADDR 0x1c31
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#define MT6368_PMIC_RG_LDO_VIBR_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VIBR_LP_ADDR 0x1c31
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#define MT6368_PMIC_RG_LDO_VIBR_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VIO28_EN_ADDR 0x1c3f
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#define MT6368_PMIC_RG_LDO_VIO28_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VIO28_LP_ADDR 0x1c3f
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#define MT6368_PMIC_RG_LDO_VIO28_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VFP_EN_ADDR 0x1c4d
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#define MT6368_PMIC_RG_LDO_VFP_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VFP_LP_ADDR 0x1c4d
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#define MT6368_PMIC_RG_LDO_VFP_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VTP_EN_ADDR 0x1c87
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#define MT6368_PMIC_RG_LDO_VTP_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VTP_LP_ADDR 0x1c87
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#define MT6368_PMIC_RG_LDO_VTP_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VMCH_EN_ADDR 0x1c95
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#define MT6368_PMIC_RG_LDO_VMCH_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VMCH_LP_ADDR 0x1c95
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#define MT6368_PMIC_RG_LDO_VMCH_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VMC_EN_ADDR 0x1ca4
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#define MT6368_PMIC_RG_LDO_VMC_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VMC_LP_ADDR 0x1ca4
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#define MT6368_PMIC_RG_LDO_VMC_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VAUD18_EN_ADDR 0x1cb2
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#define MT6368_PMIC_RG_LDO_VAUD18_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VAUD18_LP_ADDR 0x1cb2
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#define MT6368_PMIC_RG_LDO_VAUD18_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VCN33_1_EN_ADDR 0x1cc0
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#define MT6368_PMIC_RG_LDO_VCN33_1_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VCN33_1_LP_ADDR 0x1cc0
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#define MT6368_PMIC_RG_LDO_VCN33_1_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VCN33_2_EN_ADDR 0x1cce
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#define MT6368_PMIC_RG_LDO_VCN33_2_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VCN33_2_LP_ADDR 0x1cce
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#define MT6368_PMIC_RG_LDO_VCN33_2_LP_SHIFT 1
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#define MT6368_PMIC_RG_LDO_VEFUSE_EN_ADDR 0x1d07
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#define MT6368_PMIC_RG_LDO_VEFUSE_EN_SHIFT 0
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#define MT6368_PMIC_RG_LDO_VEFUSE_LP_ADDR 0x1d07
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#define MT6368_PMIC_RG_LDO_VEFUSE_LP_SHIFT 1
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#define MT6368_PMIC_RG_VAUX18_VOCAL_ADDR 0x1d88
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#define MT6368_PMIC_RG_VAUX18_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VAUX18_VOSEL_ADDR 0x1d89
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#define MT6368_PMIC_RG_VAUX18_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VSIM1_VOCAL_ADDR 0x1d8c
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#define MT6368_PMIC_RG_VSIM1_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VSIM1_VOSEL_ADDR 0x1d8d
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#define MT6368_PMIC_RG_VSIM1_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VSIM2_VOCAL_ADDR 0x1d90
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#define MT6368_PMIC_RG_VSIM2_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VSIM2_VOSEL_ADDR 0x1d91
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#define MT6368_PMIC_RG_VSIM2_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VUSB_VOCAL_ADDR 0x1d94
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#define MT6368_PMIC_RG_VUSB_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VUSB_VOSEL_ADDR 0x1d95
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#define MT6368_PMIC_RG_VUSB_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VIBR_VOCAL_ADDR 0x1d98
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#define MT6368_PMIC_RG_VIBR_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VIBR_VOSEL_ADDR 0x1d99
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#define MT6368_PMIC_RG_VIBR_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VIO28_VOCAL_ADDR 0x1d9c
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#define MT6368_PMIC_RG_VIO28_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VIO28_VOSEL_ADDR 0x1d9d
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#define MT6368_PMIC_RG_VIO28_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VFP_VOCAL_ADDR 0x1da0
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#define MT6368_PMIC_RG_VFP_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VFP_VOSEL_ADDR 0x1da1
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#define MT6368_PMIC_RG_VFP_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VTP_VOCAL_ADDR 0x1da4
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#define MT6368_PMIC_RG_VTP_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VTP_VOSEL_ADDR 0x1da5
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#define MT6368_PMIC_RG_VTP_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VMCH_VOCAL_ADDR 0x1da8
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#define MT6368_PMIC_RG_VMCH_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VMCH_VOSEL_ADDR 0x1da9
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#define MT6368_PMIC_RG_VMCH_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VMC_VOCAL_ADDR 0x1dac
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#define MT6368_PMIC_RG_VMC_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VMC_VOSEL_ADDR 0x1dad
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#define MT6368_PMIC_RG_VMC_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VCN33_1_VOCAL_ADDR 0x1db0
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#define MT6368_PMIC_RG_VCN33_1_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VCN33_1_VOSEL_ADDR 0x1db1
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#define MT6368_PMIC_RG_VCN33_1_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VCN33_2_VOCAL_ADDR 0x1db4
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#define MT6368_PMIC_RG_VCN33_2_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VCN33_2_VOSEL_ADDR 0x1db5
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#define MT6368_PMIC_RG_VCN33_2_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VAUD18_VOCAL_ADDR 0x1db8
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#define MT6368_PMIC_RG_VAUD18_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VAUD18_VOSEL_ADDR 0x1db9
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#define MT6368_PMIC_RG_VAUD18_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VANT18_VOCAL_ADDR 0x1e08
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#define MT6368_PMIC_RG_VANT18_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VANT18_VOSEL_ADDR 0x1e09
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#define MT6368_PMIC_RG_VANT18_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VEFUSE_VOCAL_ADDR 0x1e0c
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#define MT6368_PMIC_RG_VEFUSE_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VEFUSE_VOSEL_ADDR 0x1e0d
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#define MT6368_PMIC_RG_VEFUSE_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VRF18_AIF_VOCAL_ADDR 0x1e10
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#define MT6368_PMIC_RG_VRF18_AIF_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VRF18_AIF_VOSEL_ADDR 0x1e11
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#define MT6368_PMIC_RG_VRF18_AIF_VOSEL_MASK 0xF
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#define MT6368_PMIC_RG_VRF13_AIF_VOCAL_ADDR 0x1e19
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#define MT6368_PMIC_RG_VRF13_AIF_VOCAL_MASK 0xF
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#define MT6368_PMIC_RG_VRF13_AIF_VOSEL_ADDR 0x1e1a
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#define MT6368_PMIC_RG_VRF13_AIF_VOSEL_MASK 0xF
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#define MT6368_LDO_VMCH_EINT 0x1ca3
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#define MT6368_PMIC_RG_LDO_VMCH_EINT_EN_MASK 0x1
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#define MT6368_PMIC_RG_LDO_VMCH_EINT_POL_MASK 0x4
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#define MT6368_PMIC_RG_LDO_VMCH_EINT_DB_MASK 0x10
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#endif /* __LINUX_REGULATOR_MT6368_H */
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