424 lines
22 KiB
C
424 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __LINUX_REGULATOR_MT6363_H
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#define __LINUX_REGULATOR_MT6363_H
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enum {
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MT6363_ID_VS2,
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MT6363_ID_VBUCK1,
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MT6363_ID_VBUCK2,
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MT6363_ID_VBUCK3,
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MT6363_ID_VBUCK4,
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MT6363_ID_VBUCK5,
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MT6363_ID_VBUCK6,
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MT6363_ID_VBUCK7,
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MT6363_ID_VS1,
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MT6363_ID_VS3,
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MT6363_ID_VBUCK1_SSHUB,
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MT6363_ID_VBUCK2_SSHUB,
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MT6363_ID_VBUCK4_SSHUB,
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MT6363_ID_VSRAM_DIGRF,
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MT6363_ID_VSRAM_MDFE,
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MT6363_ID_VSRAM_MODEM,
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MT6363_ID_VSRAM_CPUB,
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MT6363_ID_VSRAM_CPUM,
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MT6363_ID_VSRAM_CPUL,
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MT6363_ID_VSRAM_APU,
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MT6363_ID_VEMC,
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MT6363_ID_VCN13,
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MT6363_ID_VTREF18,
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MT6363_ID_VAUX18,
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MT6363_ID_VCN15,
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MT6363_ID_VUFS18,
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MT6363_ID_VIO18,
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MT6363_ID_VM18,
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MT6363_ID_VA15,
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MT6363_ID_VRF18,
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MT6363_ID_VRFIO18,
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MT6363_ID_VIO075,
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MT6363_ID_VUFS12,
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MT6363_ID_VA12_1,
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MT6363_ID_VA12_2,
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MT6363_ID_VRF12,
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MT6363_ID_VRF13,
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MT6363_ID_VRF09,
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MT6363_ID_ISINK_LOAD,
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MT6363_MAX_REGULATOR,
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};
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#define MTK_REGULATOR_MAX_NR MT6363_MAX_REGULATOR
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/* Register */
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#define MT6363_TOP_TRAP (0x36)
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#define MT6363_TOP_TMA_KEY_L (0x39e)
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#define MT6363_BUCK_TOP_KEY_PROT_LO (0x142a)
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#define MT6363_BUCK_VS2_OP_EN_0 (0x148d)
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#define MT6363_BUCK_VS2_HW_LP_MODE (0x1498)
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#define MT6363_BUCK_VBUCK1_OP_EN_0 (0x150d)
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#define MT6363_BUCK_VBUCK1_HW_LP_MODE (0x1518)
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#define MT6363_BUCK_VBUCK2_OP_EN_0 (0x158d)
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#define MT6363_BUCK_VBUCK2_HW_LP_MODE (0x1598)
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#define MT6363_BUCK_VBUCK3_OP_EN_0 (0x160d)
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#define MT6363_BUCK_VBUCK3_HW_LP_MODE (0x1618)
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#define MT6363_BUCK_VBUCK4_OP_EN_0 (0x168d)
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#define MT6363_BUCK_VBUCK4_HW_LP_MODE (0x1698)
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#define MT6363_BUCK_VBUCK5_OP_EN_0 (0x170d)
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#define MT6363_BUCK_VBUCK5_HW_LP_MODE (0x1718)
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#define MT6363_BUCK_VBUCK6_OP_EN_0 (0x178d)
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#define MT6363_BUCK_VBUCK6_HW_LP_MODE (0x1798)
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#define MT6363_BUCK_VBUCK7_OP_EN_0 (0x180d)
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#define MT6363_BUCK_VBUCK7_HW_LP_MODE (0x1818)
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#define MT6363_BUCK_VS1_OP_EN_0 (0x188d)
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#define MT6363_BUCK_VS1_HW_LP_MODE (0x1898)
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#define MT6363_BUCK_VS3_OP_EN_0 (0x190d)
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#define MT6363_BUCK_VS3_HW_LP_MODE (0x1918)
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#define MT6363_LDO_VCN15_HW_LP_MODE (0x1b8b)
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#define MT6363_LDO_VCN15_OP_EN0 (0x1b8c)
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#define MT6363_LDO_VRF09_HW_LP_MODE (0x1b99)
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#define MT6363_LDO_VRF09_OP_EN0 (0x1b9a)
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#define MT6363_LDO_VRF12_HW_LP_MODE (0x1ba7)
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#define MT6363_LDO_VRF12_OP_EN0 (0x1ba8)
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#define MT6363_LDO_VRF13_HW_LP_MODE (0x1bb5)
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#define MT6363_LDO_VRF13_OP_EN0 (0x1bb6)
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#define MT6363_LDO_VRF18_HW_LP_MODE (0x1bc3)
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#define MT6363_LDO_VRF18_OP_EN0 (0x1bc4)
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#define MT6363_LDO_VRFIO18_HW_LP_MODE (0x1bd1)
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#define MT6363_LDO_VRFIO18_OP_EN0 (0x1bd2)
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#define MT6363_LDO_VTREF18_HW_LP_MODE (0x1c0b)
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#define MT6363_LDO_VTREF18_OP_EN0 (0x1c0c)
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#define MT6363_LDO_VAUX18_HW_LP_MODE (0x1c19)
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#define MT6363_LDO_VAUX18_OP_EN0 (0x1c1a)
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#define MT6363_LDO_VEMC_HW_LP_MODE (0x1c27)
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#define MT6363_LDO_VEMC_OP_EN0 (0x1c28)
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#define MT6363_LDO_VUFS12_HW_LP_MODE (0x1c35)
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#define MT6363_LDO_VUFS12_OP_EN0 (0x1c36)
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#define MT6363_LDO_VUFS18_HW_LP_MODE (0x1c43)
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#define MT6363_LDO_VUFS18_OP_EN0 (0x1c44)
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#define MT6363_LDO_VIO18_HW_LP_MODE (0x1c51)
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#define MT6363_LDO_VIO18_OP_EN0 (0x1c52)
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#define MT6363_LDO_VIO075_HW_LP_MODE (0x1c8b)
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#define MT6363_LDO_VIO075_OP_EN0 (0x1c8c)
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#define MT6363_LDO_VA12_1_HW_LP_MODE (0x1c99)
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#define MT6363_LDO_VA12_1_OP_EN0 (0x1c9a)
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#define MT6363_LDO_VA12_2_HW_LP_MODE (0x1ca7)
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#define MT6363_LDO_VA12_2_OP_EN0 (0x1ca8)
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#define MT6363_LDO_VA15_HW_LP_MODE (0x1cb5)
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#define MT6363_LDO_VA15_OP_EN0 (0x1cb6)
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#define MT6363_LDO_VM18_HW_LP_MODE (0x1cc3)
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#define MT6363_LDO_VM18_OP_EN0 (0x1cc4)
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#define MT6363_LDO_VCN13_HW_LP_MODE (0x1d0b)
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#define MT6363_LDO_VCN13_OP_EN0 (0x1d14)
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#define MT6363_LDO_VSRAM_DIGRF_HW_LP_MODE (0x1d21)
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#define MT6363_LDO_VSRAM_DIGRF_OP_EN0 (0x1d2a)
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#define MT6363_LDO_VSRAM_MDFE_HW_LP_MODE (0x1d8b)
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#define MT6363_LDO_VSRAM_MDFE_OP_EN0 (0x1d94)
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#define MT6363_LDO_VSRAM_MODEM_HW_LP_MODE (0x1da6)
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#define MT6363_LDO_VSRAM_MODEM_OP_EN0 (0x1daf)
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#define MT6363_LDO_VSRAM_CPUB_HW_LP_MODE (0x1e0b)
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#define MT6363_LDO_VSRAM_CPUB_OP_EN0 (0x1e14)
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#define MT6363_LDO_VSRAM_CPUM_HW_LP_MODE (0x1e21)
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#define MT6363_LDO_VSRAM_CPUM_OP_EN0 (0x1e2a)
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#define MT6363_LDO_VSRAM_CPUL_HW_LP_MODE (0x1e8b)
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#define MT6363_LDO_VSRAM_CPUL_OP_EN0 (0x1e94)
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#define MT6363_LDO_VSRAM_APU_HW_LP_MODE (0x1ea1)
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#define MT6363_LDO_VSRAM_APU_OP_EN0 (0x1eaa)
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#define MT6363_RG_BUCK_VS2_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VS2_EN_SHIFT (0)
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#define MT6363_RG_BUCK_VBUCK1_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VBUCK1_EN_SHIFT (1)
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#define MT6363_RG_BUCK_VBUCK2_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VBUCK2_EN_SHIFT (2)
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#define MT6363_RG_BUCK_VBUCK3_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VBUCK3_EN_SHIFT (3)
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#define MT6363_RG_BUCK_VBUCK4_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VBUCK4_EN_SHIFT (4)
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#define MT6363_RG_BUCK_VBUCK5_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VBUCK5_EN_SHIFT (5)
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#define MT6363_RG_BUCK_VBUCK6_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VBUCK6_EN_SHIFT (6)
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#define MT6363_RG_BUCK_VBUCK7_EN_ADDR (0x240)
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#define MT6363_RG_BUCK_VBUCK7_EN_SHIFT (7)
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#define MT6363_RG_BUCK_VS1_EN_ADDR (0x243)
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#define MT6363_RG_BUCK_VS1_EN_SHIFT (0)
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#define MT6363_RG_BUCK_VS3_EN_ADDR (0x243)
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#define MT6363_RG_BUCK_VS3_EN_SHIFT (1)
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#define MT6363_RG_LDO_VSRAM_DIGRF_EN_ADDR (0x243)
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#define MT6363_RG_LDO_VSRAM_DIGRF_EN_SHIFT (4)
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#define MT6363_RG_LDO_VSRAM_MDFE_EN_ADDR (0x243)
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#define MT6363_RG_LDO_VSRAM_MDFE_EN_SHIFT (5)
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#define MT6363_RG_LDO_VSRAM_MODEM_EN_ADDR (0x243)
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#define MT6363_RG_LDO_VSRAM_MODEM_EN_SHIFT (6)
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#define MT6363_RG_BUCK_VS2_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VS2_LP_SHIFT (0)
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#define MT6363_RG_BUCK_VBUCK1_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VBUCK1_LP_SHIFT (1)
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#define MT6363_RG_BUCK_VBUCK2_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VBUCK2_LP_SHIFT (2)
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#define MT6363_RG_BUCK_VBUCK3_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VBUCK3_LP_SHIFT (3)
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#define MT6363_RG_BUCK_VBUCK4_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VBUCK4_LP_SHIFT (4)
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#define MT6363_RG_BUCK_VBUCK5_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VBUCK5_LP_SHIFT (5)
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#define MT6363_RG_BUCK_VBUCK6_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VBUCK6_LP_SHIFT (6)
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#define MT6363_RG_BUCK_VBUCK7_LP_ADDR (0x246)
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#define MT6363_RG_BUCK_VBUCK7_LP_SHIFT (7)
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#define MT6363_RG_BUCK_VS1_LP_ADDR (0x249)
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#define MT6363_RG_BUCK_VS1_LP_SHIFT (0)
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#define MT6363_RG_BUCK_VS3_LP_ADDR (0x249)
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#define MT6363_RG_BUCK_VS3_LP_SHIFT (1)
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#define MT6363_RG_LDO_VSRAM_DIGRF_LP_ADDR (0x249)
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#define MT6363_RG_LDO_VSRAM_DIGRF_LP_SHIFT (4)
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#define MT6363_RG_LDO_VSRAM_MDFE_LP_ADDR (0x249)
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#define MT6363_RG_LDO_VSRAM_MDFE_LP_SHIFT (5)
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#define MT6363_RG_LDO_VSRAM_MODEM_LP_ADDR (0x249)
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#define MT6363_RG_LDO_VSRAM_MODEM_LP_SHIFT (6)
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#define MT6363_RG_BUCK_VS2_VOSEL_ADDR (0x24c)
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#define MT6363_RG_BUCK_VS2_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK1_VOSEL_ADDR (0x24d)
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#define MT6363_RG_BUCK_VBUCK1_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK2_VOSEL_ADDR (0x24e)
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#define MT6363_RG_BUCK_VBUCK2_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK3_VOSEL_ADDR (0x24f)
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#define MT6363_RG_BUCK_VBUCK3_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK4_VOSEL_ADDR (0x250)
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#define MT6363_RG_BUCK_VBUCK4_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK5_VOSEL_ADDR (0x251)
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#define MT6363_RG_BUCK_VBUCK5_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK6_VOSEL_ADDR (0x252)
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#define MT6363_RG_BUCK_VBUCK6_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK7_VOSEL_ADDR (0x253)
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#define MT6363_RG_BUCK_VBUCK7_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VS1_VOSEL_ADDR (0x254)
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#define MT6363_RG_BUCK_VS1_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VS3_VOSEL_ADDR (0x255)
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#define MT6363_RG_BUCK_VS3_VOSEL_MASK (0xff)
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#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_ADDR (0x258)
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#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_MASK (0x7f)
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#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_ADDR (0x259)
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#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_MASK (0x7f)
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#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_ADDR (0x25a)
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#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_MASK (0x7f)
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#define MT6363_BUCK_VS2_WDTDBG_VOSEL_ADDR (0x142c)
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#define MT6363_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR (0x142d)
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#define MT6363_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR (0x142e)
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#define MT6363_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR (0x142f)
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#define MT6363_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR (0x1430)
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#define MT6363_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR (0x1431)
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#define MT6363_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR (0x1432)
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#define MT6363_BUCK_VBUCK7_WDTDBG_VOSEL_ADDR (0x1433)
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#define MT6363_BUCK_VS1_WDTDBG_VOSEL_ADDR (0x1434)
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#define MT6363_BUCK_VS3_WDTDBG_VOSEL_ADDR (0x1435)
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#define MT6363_RG_BUCK_VBUCK1_SSHUB_EN_ADDR (0x151a)
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#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_ADDR (0x151b)
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#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK2_SSHUB_EN_ADDR (0x159a)
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#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_ADDR (0x159b)
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#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_MASK (0xff)
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#define MT6363_RG_BUCK_VBUCK4_SSHUB_EN_ADDR (0x169a)
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#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_ADDR (0x169b)
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#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK (0xff)
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#define MT6363_RG_VS1_FCCM_ADDR (0x1994)
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#define MT6363_RG_VS1_FCCM_SHIFT (0)
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#define MT6363_RG_VS3_FCCM_ADDR (0x19a3)
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#define MT6363_RG_VS3_FCCM_SHIFT (0)
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#define MT6363_RG_VBUCK1_FCCM_ADDR (0x1a32)
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#define MT6363_RG_VBUCK1_FCCM_SHIFT (0)
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#define MT6363_RG_VBUCK2_FCCM_ADDR (0x1a32)
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#define MT6363_RG_VBUCK2_FCCM_SHIFT (1)
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#define MT6363_RG_VBUCK3_FCCM_ADDR (0x1a32)
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#define MT6363_RG_VBUCK3_FCCM_SHIFT (2)
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#define MT6363_RG_VS2_FCCM_ADDR (0x1a32)
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#define MT6363_RG_VS2_FCCM_SHIFT (3)
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#define MT6363_RG_VBUCK4_FCCM_ADDR (0x1ab2)
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#define MT6363_RG_VBUCK4_FCCM_SHIFT (0)
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#define MT6363_RG_VBUCK5_FCCM_ADDR (0x1ab2)
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#define MT6363_RG_VBUCK5_FCCM_SHIFT (1)
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#define MT6363_RG_VBUCK6_FCCM_ADDR (0x1ab2)
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#define MT6363_RG_VBUCK6_FCCM_SHIFT (2)
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#define MT6363_RG_VBUCK7_FCCM_ADDR (0x1ab2)
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#define MT6363_RG_VBUCK7_FCCM_SHIFT (3)
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#define MT6363_RG_VCN13_VOSEL_ADDR (0x1b3f)
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#define MT6363_RG_VCN13_VOSEL_MASK (0xf)
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#define MT6363_RG_VEMC_VOSEL_0_ADDR (0x1b40)
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#define MT6363_RG_VEMC_VOSEL_0_MASK (0xf)
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#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_ADDR (0x1b44)
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#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_MASK (0x7f)
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#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_ADDR (0x1b45)
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#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_MASK (0x7f)
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#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_ADDR (0x1b46)
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#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_MASK (0x7f)
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#define MT6363_RG_LDO_VSRAM_APU_VOSEL_ADDR (0x1b47)
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#define MT6363_RG_LDO_VSRAM_APU_VOSEL_MASK (0x7f)
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#define MT6363_RG_VEMC_VOCAL_0_ADDR (0x1b4b)
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#define MT6363_RG_VEMC_VOCAL_0_MASK (0xf)
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#define MT6363_RG_LDO_VCN15_EN_ADDR (0x1b87)
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#define MT6363_RG_LDO_VCN15_EN_SHIFT (0)
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#define MT6363_RG_LDO_VCN15_LP_ADDR (0x1b87)
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#define MT6363_RG_LDO_VCN15_LP_SHIFT (1)
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#define MT6363_RG_LDO_VRF09_EN_ADDR (0x1b95)
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#define MT6363_RG_LDO_VRF09_EN_SHIFT (0)
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#define MT6363_RG_LDO_VRF09_LP_ADDR (0x1b95)
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#define MT6363_RG_LDO_VRF09_LP_SHIFT (1)
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#define MT6363_RG_LDO_VRF12_EN_ADDR (0x1ba3)
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#define MT6363_RG_LDO_VRF12_EN_SHIFT (0)
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#define MT6363_RG_LDO_VRF12_LP_ADDR (0x1ba3)
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#define MT6363_RG_LDO_VRF12_LP_SHIFT (1)
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#define MT6363_RG_LDO_VRF13_EN_ADDR (0x1bb1)
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#define MT6363_RG_LDO_VRF13_EN_SHIFT (0)
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#define MT6363_RG_LDO_VRF13_LP_ADDR (0x1bb1)
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#define MT6363_RG_LDO_VRF13_LP_SHIFT (1)
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#define MT6363_RG_LDO_VRF18_EN_ADDR (0x1bbf)
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#define MT6363_RG_LDO_VRF18_EN_SHIFT (0)
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#define MT6363_RG_LDO_VRF18_LP_ADDR (0x1bbf)
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#define MT6363_RG_LDO_VRF18_LP_SHIFT (1)
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#define MT6363_RG_LDO_VRFIO18_EN_ADDR (0x1bcd)
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#define MT6363_RG_LDO_VRFIO18_EN_SHIFT (0)
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#define MT6363_RG_LDO_VRFIO18_LP_ADDR (0x1bcd)
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#define MT6363_RG_LDO_VRFIO18_LP_SHIFT (1)
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#define MT6363_RG_LDO_VTREF18_EN_ADDR (0x1c07)
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#define MT6363_RG_LDO_VTREF18_EN_SHIFT (0)
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#define MT6363_RG_LDO_VTREF18_LP_ADDR (0x1c07)
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#define MT6363_RG_LDO_VTREF18_LP_SHIFT (1)
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#define MT6363_RG_LDO_VAUX18_EN_ADDR (0x1c15)
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#define MT6363_RG_LDO_VAUX18_EN_SHIFT (0)
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#define MT6363_RG_LDO_VAUX18_LP_ADDR (0x1c15)
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#define MT6363_RG_LDO_VAUX18_LP_SHIFT (1)
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#define MT6363_RG_LDO_VEMC_EN_ADDR (0x1c23)
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#define MT6363_RG_LDO_VEMC_EN_SHIFT (0)
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#define MT6363_RG_LDO_VEMC_LP_ADDR (0x1c23)
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#define MT6363_RG_LDO_VEMC_LP_SHIFT (1)
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#define MT6363_RG_LDO_VUFS12_EN_ADDR (0x1c31)
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#define MT6363_RG_LDO_VUFS12_EN_SHIFT (0)
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#define MT6363_RG_LDO_VUFS12_LP_ADDR (0x1c31)
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#define MT6363_RG_LDO_VUFS12_LP_SHIFT (1)
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#define MT6363_RG_LDO_VUFS18_EN_ADDR (0x1c3f)
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#define MT6363_RG_LDO_VUFS18_EN_SHIFT (0)
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#define MT6363_RG_LDO_VUFS18_LP_ADDR (0x1c3f)
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#define MT6363_RG_LDO_VUFS18_LP_SHIFT (1)
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#define MT6363_RG_LDO_VIO18_EN_ADDR (0x1c4d)
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#define MT6363_RG_LDO_VIO18_EN_SHIFT (0)
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#define MT6363_RG_LDO_VIO18_LP_ADDR (0x1c4d)
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#define MT6363_RG_LDO_VIO18_LP_SHIFT (1)
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#define MT6363_RG_LDO_VIO075_EN_ADDR (0x1c87)
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#define MT6363_RG_LDO_VIO075_EN_SHIFT (0)
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#define MT6363_RG_LDO_VIO075_LP_ADDR (0x1c87)
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#define MT6363_RG_LDO_VIO075_LP_SHIFT (1)
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#define MT6363_RG_LDO_VA12_1_EN_ADDR (0x1c95)
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#define MT6363_RG_LDO_VA12_1_EN_SHIFT (0)
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#define MT6363_RG_LDO_VA12_1_LP_ADDR (0x1c95)
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#define MT6363_RG_LDO_VA12_1_LP_SHIFT (1)
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#define MT6363_RG_LDO_VA12_2_EN_ADDR (0x1ca3)
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#define MT6363_RG_LDO_VA12_2_EN_SHIFT (0)
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#define MT6363_RG_LDO_VA12_2_LP_ADDR (0x1ca3)
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#define MT6363_RG_LDO_VA12_2_LP_SHIFT (1)
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#define MT6363_RG_LDO_VA15_EN_ADDR (0x1cb1)
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#define MT6363_RG_LDO_VA15_EN_SHIFT (0)
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#define MT6363_RG_LDO_VA15_LP_ADDR (0x1cb1)
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#define MT6363_RG_LDO_VA15_LP_SHIFT (1)
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#define MT6363_RG_LDO_VM18_EN_ADDR (0x1cbf)
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#define MT6363_RG_LDO_VM18_EN_SHIFT (0)
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#define MT6363_RG_LDO_VM18_LP_ADDR (0x1cbf)
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#define MT6363_RG_LDO_VM18_LP_SHIFT (1)
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#define MT6363_RG_LDO_VCN13_EN_ADDR (0x1d07)
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#define MT6363_RG_LDO_VCN13_EN_SHIFT (0)
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#define MT6363_RG_LDO_VCN13_LP_ADDR (0x1d07)
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#define MT6363_RG_LDO_VCN13_LP_SHIFT (1)
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#define MT6363_LDO_VSRAM_DIGRF_WDTDBG_VOSEL_ADDR (0x1d24)
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#define MT6363_LDO_VSRAM_MDFE_WDTDBG_VOSEL_ADDR (0x1d8e)
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#define MT6363_LDO_VSRAM_MODEM_WDTDBG_VOSEL_ADDR (0x1da9)
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#define MT6363_RG_LDO_VSRAM_CPUB_EN_ADDR (0x1e07)
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#define MT6363_RG_LDO_VSRAM_CPUB_EN_SHIFT (0)
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#define MT6363_RG_LDO_VSRAM_CPUB_LP_ADDR (0x1e07)
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#define MT6363_RG_LDO_VSRAM_CPUB_LP_SHIFT (1)
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#define MT6363_LDO_VSRAM_CPUB_WDTDBG_VOSEL_ADDR (0x1e0e)
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#define MT6363_RG_LDO_VSRAM_CPUM_EN_ADDR (0x1e1d)
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#define MT6363_RG_LDO_VSRAM_CPUM_EN_SHIFT (0)
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#define MT6363_RG_LDO_VSRAM_CPUM_LP_ADDR (0x1e1d)
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#define MT6363_RG_LDO_VSRAM_CPUM_LP_SHIFT (1)
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#define MT6363_LDO_VSRAM_CPUM_WDTDBG_VOSEL_ADDR (0x1e24)
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#define MT6363_RG_LDO_VSRAM_CPUL_EN_ADDR (0x1e87)
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#define MT6363_RG_LDO_VSRAM_CPUL_EN_SHIFT (0)
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#define MT6363_RG_LDO_VSRAM_CPUL_LP_ADDR (0x1e87)
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#define MT6363_RG_LDO_VSRAM_CPUL_LP_SHIFT (1)
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#define MT6363_LDO_VSRAM_CPUL_WDTDBG_VOSEL_ADDR (0x1e8e)
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#define MT6363_RG_LDO_VSRAM_APU_EN_ADDR (0x1e9d)
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#define MT6363_RG_LDO_VSRAM_APU_EN_SHIFT (0)
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#define MT6363_RG_LDO_VSRAM_APU_LP_ADDR (0x1e9d)
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#define MT6363_RG_LDO_VSRAM_APU_LP_SHIFT (1)
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#define MT6363_LDO_VSRAM_APU_WDTDBG_VOSEL_ADDR (0x1ea4)
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#define MT6363_RG_VTREF18_VOCAL_ADDR (0x1f08)
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#define MT6363_RG_VTREF18_VOCAL_MASK (0xf)
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#define MT6363_RG_VTREF18_VOSEL_ADDR (0x1f09)
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#define MT6363_RG_VTREF18_VOSEL_MASK (0xf)
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#define MT6363_RG_VAUX18_VOCAL_ADDR (0x1f0c)
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#define MT6363_RG_VAUX18_VOCAL_MASK (0xf)
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#define MT6363_RG_VAUX18_VOSEL_ADDR (0x1f0d)
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#define MT6363_RG_VAUX18_VOSEL_MASK (0xf)
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#define MT6363_RG_VCN15_VOCAL_ADDR (0x1f13)
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#define MT6363_RG_VCN15_VOCAL_MASK (0xf)
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#define MT6363_RG_VCN15_VOSEL_ADDR (0x1f14)
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#define MT6363_RG_VCN15_VOSEL_MASK (0xf)
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#define MT6363_RG_VUFS18_VOCAL_ADDR (0x1f17)
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#define MT6363_RG_VUFS18_VOCAL_MASK (0xf)
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#define MT6363_RG_VUFS18_VOSEL_ADDR (0x1f18)
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#define MT6363_RG_VUFS18_VOSEL_MASK (0xf)
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#define MT6363_RG_VIO18_VOCAL_ADDR (0x1f1b)
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#define MT6363_RG_VIO18_VOCAL_MASK (0xf)
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#define MT6363_RG_VIO18_VOSEL_ADDR (0x1f1c)
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#define MT6363_RG_VIO18_VOSEL_MASK (0xf)
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#define MT6363_RG_VM18_VOCAL_ADDR (0x1f1f)
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#define MT6363_RG_VM18_VOCAL_MASK (0xf)
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#define MT6363_RG_VM18_VOSEL_ADDR (0x1f20)
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#define MT6363_RG_VM18_VOSEL_MASK (0xf)
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#define MT6363_RG_VA15_VOCAL_ADDR (0x1f23)
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#define MT6363_RG_VA15_VOCAL_MASK (0xf)
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#define MT6363_RG_VA15_VOSEL_ADDR (0x1f24)
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#define MT6363_RG_VA15_VOSEL_MASK (0xf)
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#define MT6363_RG_VRF18_VOCAL_ADDR (0x1f27)
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#define MT6363_RG_VRF18_VOCAL_MASK (0xf)
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#define MT6363_RG_VRF18_VOSEL_ADDR (0x1f28)
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#define MT6363_RG_VRF18_VOSEL_MASK (0xf)
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#define MT6363_RG_VRFIO18_VOCAL_ADDR (0x1f2b)
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#define MT6363_RG_VRFIO18_VOCAL_MASK (0xf)
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#define MT6363_RG_VRFIO18_VOSEL_ADDR (0x1f2c)
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#define MT6363_RG_VRFIO18_VOSEL_MASK (0xf)
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#define MT6363_RG_VIO075_VOCAL_ADDR (0x1f31)
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#define MT6363_RG_VIO075_VOCAL_MASK (0xf)
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#define MT6363_RG_VIO075_VOSEL_ADDR (0x1f31)
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#define MT6363_RG_VIO075_VOSEL_MASK (0x70)
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#define MT6363_RG_VCN13_VOCAL_ADDR (0x1f88)
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#define MT6363_RG_VCN13_VOCAL_MASK (0xf)
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#define MT6363_RG_VUFS12_VOCAL_ADDR (0x1f91)
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#define MT6363_RG_VUFS12_VOCAL_MASK (0xf)
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#define MT6363_RG_VUFS12_VOSEL_ADDR (0x1f92)
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#define MT6363_RG_VUFS12_VOSEL_MASK (0xf)
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#define MT6363_RG_VA12_1_VOCAL_ADDR (0x1f95)
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#define MT6363_RG_VA12_1_VOCAL_MASK (0xf)
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#define MT6363_RG_VA12_1_VOSEL_ADDR (0x1f96)
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#define MT6363_RG_VA12_1_VOSEL_MASK (0xf)
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#define MT6363_RG_VA12_2_VOCAL_ADDR (0x1f99)
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#define MT6363_RG_VA12_2_VOCAL_MASK (0xf)
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#define MT6363_RG_VA12_2_VOSEL_ADDR (0x1f9a)
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#define MT6363_RG_VA12_2_VOSEL_MASK (0xf)
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#define MT6363_RG_VRF12_VOCAL_ADDR (0x1f9d)
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#define MT6363_RG_VRF12_VOCAL_MASK (0xf)
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#define MT6363_RG_VRF12_VOSEL_ADDR (0x1f9e)
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#define MT6363_RG_VRF12_VOSEL_MASK (0xf)
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#define MT6363_RG_VRF13_VOCAL_ADDR (0x1fa1)
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#define MT6363_RG_VRF13_VOCAL_MASK (0xf)
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#define MT6363_RG_VRF13_VOSEL_ADDR (0x1fa2)
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#define MT6363_RG_VRF13_VOSEL_MASK (0xf)
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#define MT6363_RG_VRF09_VOCAL_ADDR (0x1fa8)
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#define MT6363_RG_VRF09_VOCAL_MASK (0xf)
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#define MT6363_RG_VRF09_VOSEL_ADDR (0x1fa9)
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#define MT6363_RG_VRF09_VOSEL_MASK (0xf)
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#define MT6363_ISINK_EN_CTRL0 (0x220b)
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#define MT6363_ISINK_EN_CTRL1 (0x220c)
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#endif /* __LINUX_REGULATOR_MT6363_H */
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