94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#ifndef __MFD_MT6368_CORE_H__
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#define __MFD_MT6368_CORE_H__
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#define MT6368_REG_WIDTH 8
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enum mt6368_irq_top_status_shift {
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MT6368_BUCK_TOP = 0,
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MT6368_LDO_TOP,
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MT6368_PSC_TOP,
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MT6368_MISC_TOP,
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MT6368_HK_TOP,
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MT6368_SCK_TOP,
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MT6368_BM_TOP,
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MT6368_AUD_TOP,
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};
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enum mt6368_irq_numbers {
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MT6368_IRQ_VBUCK1_OC,
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MT6368_IRQ_VBUCK2_OC,
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MT6368_IRQ_VBUCK3_OC,
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MT6368_IRQ_VBUCK4_OC,
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MT6368_IRQ_VBUCK5_OC,
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MT6368_IRQ_VBUCK6_OC,
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MT6368_IRQ_VPA_OC,
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MT6368_IRQ_VSIM1_OC = 8,
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MT6368_IRQ_VSIM2_OC,
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MT6368_IRQ_VMDDR_OC,
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MT6368_IRQ_VMDDQ_OC,
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MT6368_IRQ_VUSB_OC,
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MT6368_IRQ_VAUX18_OC,
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MT6368_IRQ_VRF13_AIF_OC,
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MT6368_IRQ_VRF18_AIF_OC,
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MT6368_IRQ_VANT18_OC,
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MT6368_IRQ_VIBR_OC,
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MT6368_IRQ_VIO28_OC,
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MT6368_IRQ_VFP_OC,
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MT6368_IRQ_VTP_OC,
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MT6368_IRQ_VMCH_OC,
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MT6368_IRQ_VMC_OC,
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MT6368_IRQ_VAUD18_OC,
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MT6368_IRQ_VCN33_1_OC,
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MT6368_IRQ_VCN33_2_OC,
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MT6368_IRQ_VEFUSE_OC,
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MT6368_IRQ_RCS0 = 48,
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MT6368_IRQ_SPMI_CMD_ALERT,
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MT6368_IRQ_SPMI_P_CMD_ALERT,
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MT6368_IRQ_BM_PROTREG = 54,
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MT6368_IRQ_VRC_PROTREG,
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MT6368_IRQ_BUCK_PROTREG,
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MT6368_IRQ_LDO_PROTREG,
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MT6368_IRQ_PSC_PROTREG,
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MT6368_IRQ_PLT_PROTREG,
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MT6368_IRQ_HK_PROTREG,
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MT6368_IRQ_SCK_PROTREG,
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MT6368_IRQ_XPP_PROTREG,
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MT6368_IRQ_TOP_PROTREG,
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MT6368_IRQ_AUDIO = 96,
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MT6368_IRQ_ACCDET,
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MT6368_IRQ_ACCDET_EINT0,
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MT6368_IRQ_ACCDET_EINT1,
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MT6368_IRQ_NR = 100,
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};
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#define MT6368_IRQ_BUCK_BASE MT6368_IRQ_VBUCK1_OC
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#define MT6368_IRQ_LDO_BASE MT6368_IRQ_VSIM1_OC
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#define MT6368_IRQ_MISC_BASE MT6368_IRQ_RCS0
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#define MT6368_IRQ_AUD_BASE MT6368_IRQ_AUDIO
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#define MT6368_IRQ_BUCK_BITS \
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(MT6368_IRQ_VPA_OC - MT6368_IRQ_BUCK_BASE + 1)
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#define MT6368_IRQ_LDO_BITS \
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(MT6368_IRQ_VEFUSE_OC - MT6368_IRQ_LDO_BASE + 1)
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#define MT6368_IRQ_MISC_BITS \
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(MT6368_IRQ_TOP_PROTREG - MT6368_IRQ_MISC_BASE + 1)
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#define MT6368_IRQ_AUD_BITS \
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(MT6368_IRQ_ACCDET_EINT1 - MT6368_IRQ_AUD_BASE + 1)
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#define MT6368_TOP_GEN(sp) \
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{ \
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.hwirq_base = MT6368_IRQ_##sp##_BASE, \
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.num_int_regs = ((MT6368_IRQ_##sp##_BITS - 1) / MT6368_REG_WIDTH) + 1, \
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.en_reg = MT6368_##sp##_TOP_INT_CON0, \
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.en_reg_shift = 0x3, \
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.sta_reg = MT6368_##sp##_TOP_INT_STATUS0, \
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.sta_reg_shift = 0x1, \
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.top_offset = MT6368_##sp##_TOP, \
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}
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#endif /* __MFD_MT6368_CORE_H__ */
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