51 lines
1.8 KiB
C
51 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Weiyi Lu <weiyi.lu@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
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#define _DT_BINDINGS_POWER_MT8195_POWER_H
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#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0
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#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1
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#define MT8195_POWER_DOMAIN_PCIE_PHY 2
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#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3
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#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4
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#define MT8195_POWER_DOMAIN_ETHER 5
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#define MT8195_POWER_DOMAIN_ADSP 6
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#define MT8195_POWER_DOMAIN_AUDIO 7
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#define MT8195_POWER_DOMAIN_AUDIO_ASRC 8
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#define MT8195_POWER_DOMAIN_NNA 9
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#define MT8195_POWER_DOMAIN_NNA0 10
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#define MT8195_POWER_DOMAIN_NNA1 11
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#define MT8195_POWER_DOMAIN_MFG0 12
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#define MT8195_POWER_DOMAIN_MFG1 13
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#define MT8195_POWER_DOMAIN_MFG2 14
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#define MT8195_POWER_DOMAIN_MFG3 15
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#define MT8195_POWER_DOMAIN_MFG4 16
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#define MT8195_POWER_DOMAIN_MFG5 17
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#define MT8195_POWER_DOMAIN_MFG6 18
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#define MT8195_POWER_DOMAIN_VPPSYS0 19
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#define MT8195_POWER_DOMAIN_VDOSYS0 20
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#define MT8195_POWER_DOMAIN_VPPSYS1 21
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#define MT8195_POWER_DOMAIN_VDOSYS1 22
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#define MT8195_POWER_DOMAIN_DP_TX 23
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#define MT8195_POWER_DOMAIN_EPD_TX 24
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#define MT8195_POWER_DOMAIN_HDMI_TX 25
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#define MT8195_POWER_DOMAIN_HDMI_RX 26
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#define MT8195_POWER_DOMAIN_WPESYS 27
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#define MT8195_POWER_DOMAIN_VDEC0 28
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#define MT8195_POWER_DOMAIN_VDEC1 29
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#define MT8195_POWER_DOMAIN_VDEC2 30
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#define MT8195_POWER_DOMAIN_VENC 31
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#define MT8195_POWER_DOMAIN_VENC_CORE1 32
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#define MT8195_POWER_DOMAIN_IMG 33
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#define MT8195_POWER_DOMAIN_DIP 34
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#define MT8195_POWER_DOMAIN_IPE 35
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#define MT8195_POWER_DOMAIN_CAM 36
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#define MT8195_POWER_DOMAIN_CAM_RAWA 37
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#define MT8195_POWER_DOMAIN_CAM_RAWB 38
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#define MT8195_POWER_DOMAIN_CAM_MRAW 39
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#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */
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