73 lines
2.6 KiB
C
73 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_POWER_MT6985_POWER_H
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#define _DT_BINDINGS_POWER_MT6985_POWER_H
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/* GPU_EB_RPC */
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#define MT6985_POWER_DOMAIN_MFG1 0
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#define MT6985_POWER_DOMAIN_MFG2 1
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#define MT6985_POWER_DOMAIN_MFG3 2
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#define MT6985_POWER_DOMAIN_MFG4 3
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#define MT6985_POWER_DOMAIN_MFG5 4
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#define MT6985_POWER_DOMAIN_MFG6 5
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#define MT6985_POWER_DOMAIN_MFG7 6
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#define MT6985_POWER_DOMAIN_MFG8 7
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#define MT6985_POWER_DOMAIN_MFG9 8
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#define MT6985_POWER_DOMAIN_MFG10 9
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#define MT6985_POWER_DOMAIN_MFG11 10
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#define MT6985_POWER_DOMAIN_MFG12 11
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#define MT6985_POWER_DOMAIN_MFG13 12
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#define MT6985_POWER_DOMAIN_MFG14 13
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#define MT6985_POWER_DOMAIN_MFG15 14
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#define MT6985_POWER_DOMAIN_MFG16 15
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#define MT6985_POWER_DOMAIN_MFG17 16
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#define MT6985_POWER_DOMAIN_MFG18 17
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#define MT6985_POWER_DOMAIN_MFG19 18
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#define MT6985_GPU_EB_RPC_POWER_DOMAIN_NR 19
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/* SPM */
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#define MT6985_POWER_DOMAIN_MD 0
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#define MT6985_POWER_DOMAIN_CONN 1
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#define MT6985_POWER_DOMAIN_UFS0_SHUTDOWN 2
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#define MT6985_POWER_DOMAIN_UFS0_PHY_SHUTDOWN 3
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#define MT6985_POWER_DOMAIN_PEXTP_MAC0_SHUTDOWN 4
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#define MT6985_POWER_DOMAIN_PEXTP_MAC1_SHUTDOWN 5
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#define MT6985_POWER_DOMAIN_PEXTP_PHY0 6
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#define MT6985_POWER_DOMAIN_PEXTP_PHY1 7
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#define MT6985_POWER_DOMAIN_AUDIO 8
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#define MT6985_POWER_DOMAIN_ADSP_TOP_DORMANT 9
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#define MT6985_POWER_DOMAIN_MM_INFRA 10
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#define MT6985_POWER_DOMAIN_MM_PROC_DORMANT 11
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#define MT6985_POWER_DOMAIN_ISP_VCORE 12
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#define MT6985_POWER_DOMAIN_ISP_MAIN 13
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#define MT6985_POWER_DOMAIN_ISP_DIP1 14
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#define MT6985_POWER_DOMAIN_VDE_VCORE0 15
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#define MT6985_POWER_DOMAIN_VDE0 16
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#define MT6985_POWER_DOMAIN_VDE_VCORE1 17
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#define MT6985_POWER_DOMAIN_VDE1 18
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#define MT6985_POWER_DOMAIN_VEN0 19
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#define MT6985_POWER_DOMAIN_VEN1 20
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#define MT6985_POWER_DOMAIN_VEN2 21
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#define MT6985_POWER_DOMAIN_CAM_VCORE 22
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#define MT6985_POWER_DOMAIN_CAM_MAIN 23
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#define MT6985_POWER_DOMAIN_CAM_MRAW 24
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#define MT6985_POWER_DOMAIN_CAM_SUBA 25
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#define MT6985_POWER_DOMAIN_CAM_SUBB 26
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#define MT6985_POWER_DOMAIN_CAM_SUBC 27
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#define MT6985_POWER_DOMAIN_MDP0_SHUTDOWN 28
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#define MT6985_POWER_DOMAIN_MDP1_SHUTDOWN 29
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#define MT6985_POWER_DOMAIN_DIS0_SHUTDOWN 30
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#define MT6985_POWER_DOMAIN_DIS1_SHUTDOWN 31
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#define MT6985_POWER_DOMAIN_OVLSYS_SHUTDOWN 32
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#define MT6985_POWER_DOMAIN_OVLSYS1_SHUTDOWN 33
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#define MT6985_POWER_DOMAIN_DP_TX 34
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#define MT6985_POWER_DOMAIN_CSI_RX 35
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#define MT6985_POWER_DOMAIN_APU 36
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#define MT6985_SPM_POWER_DOMAIN_NR 37
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#endif /* _DT_BINDINGS_POWER_MT6985_POWER_H */
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