122 lines
3 KiB
C
122 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Eason Yen <eason.yen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MML_MT6886_H
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#define _DT_BINDINGS_MML_MT6886_H
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/* MML engines in mt6886 */
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/* The id 0 leaves empty, do not use. */
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#define MML_MMLSYS 1
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#define MML_MUTEX 2
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#define MML_RDMA0 3
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#define MML_DLI0 4
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#define MML_DLI0_SEL 5
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#define MML_HDR0 6
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#define MML_AAL0 7
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#define MML_RSZ0 8
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#define MML_TDSHP0 9
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#define MML_COLOR0 10
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#define MML_DLO0_SOUT 11
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#define MML_WROT0 12
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#define MML_DLO0 13
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#define MML_ENGINE_TOTAL 14
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/* MML component types. See mtk-mml-sys.c */
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#define MML_CT_SYS 1
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#define MML_CT_PATH 2
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#define MML_CT_DL_IN 3
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#define MML_CT_DL_OUT 4
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/* MML SYS registers */
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#define CG_CON0 0x100
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#define CG_SET0 0x104
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#define CG_CLR0 0x108
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#define CG_CON1 0x110
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#define CG_SET1 0x114
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#define CG_CLR1 0x118
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#define CG_CON2 0x120
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#define CG_SET2 0x124
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#define CG_CLR2 0x128
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#define CG_CON3 0x130
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#define CG_SET3 0x134
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#define CG_CLR3 0x138
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#define CG_CON4 0x140
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#define CG_SET4 0x144
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#define CG_CLR4 0x148
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#define SW0_RST_B 0x700
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#define SW1_RST_B 0x704
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#define SW2_RST_B 0x708
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#define SW3_RST_B 0x70c
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#define SW4_RST_B 0x710
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#define EVENT_GCEM_EN 0x7f4
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#define EVENT_GCED_EN 0x7f8
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#define IN_LINE_READY_SEL 0x7fc
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#define SMI_LARB_GREQ 0x8dc
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#define BYPASS_MUX_SHADOW 0xf00
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#define MOUT_RST 0xf04
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/* MML DL IN/OUT registers in mt6886 */
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#define DL_IN_RELAY0_SIZE 0x220
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#define DL_IN_RELAY1_SIZE 0x224
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#define DL_OUT_RELAY0_SIZE 0x228
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#define DL_OUT_RELAY1_SIZE 0x22c
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#define DLO_ASYNC0_STATUS0 0x230
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#define DLO_ASYNC0_STATUS1 0x234
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#define DLO_ASYNC1_STATUS0 0x238
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#define DLO_ASYNC1_STATUS1 0x23c
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#define DLI_ASYNC0_STATUS0 0x240
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#define DLI_ASYNC0_STATUS1 0x244
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#define DLI_ASYNC1_STATUS0 0x248
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#define DLI_ASYNC1_STATUS1 0x24c
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/* MML MUX registers in mt6886 */
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#define DLI0_SEL_IN 0xf14
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#define DLI1_SEL_IN 0xf18
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#define RDMA0_MOUT_EN 0xf20
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#define RDMA1_MOUT_EN 0xf24
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#define PQ0_SEL_IN 0xf30
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#define PQ1_SEL_IN 0xf34
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#define WROT0_SEL_IN 0xf70
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#define WROT1_SEL_IN 0xf74
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#define PQ0_SOUT_SEL 0xf80
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#define PQ1_SOUT_SEL 0xf84
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#define DLO0_SOUT_SEL 0xf88
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#define DLO1_SOUT_SEL 0xf8c
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#define BYP0_MOUT_EN 0xf90
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#define BYP1_MOUT_EN 0xf94
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#define BYP0_SEL_IN 0xf98
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#define BYP1_SEL_IN 0xf9c
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#define RSZ2_SEL_IN 0xfa0
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#define RSZ3_SEL_IN 0xfa4
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/* MML AID for secure */
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#define RDMA0_AIDSEL 0xfa8
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#define RDMA1_AIDSEL 0xfac
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#define WROT0_AIDSEL 0xfb0
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#define WROT1_AIDSEL 0xfb4
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#define WROT2_AIDSEL 0xfb8
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#define WROT3_AIDSEL 0xfbc
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#define FAKE0_AIDSEL 0xfc0
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#define FG0_AIDSEL 0xfc4
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#define FG1_AIDSEL 0xfc8
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#define AID_SEL_MODE 0xfcc
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#define MOUT_MASK0 0xfd0
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#define MOUT_MASK1 0xfd4
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#define MOUT_MASK2 0xfd8
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#define DL_VALID0 0xfe0
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#define DL_VALID1 0xfe4
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#define DL_VALID2 0xfe8
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#define DL_READY0 0xff0
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#define DL_READY1 0xff4
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#define DL_READY2 0xff8
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/* MML SYS mux types. See mtk-mml-sys.c */
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#define MML_MUX_MOUT 1
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#define MML_MUX_SOUT 2
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#define MML_MUX_SLIN 3
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#endif /* _DT_BINDINGS_MML_MT6886_H */
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