402 lines
24 KiB
C
402 lines
24 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Mingyuan Ma <mingyuan.ma@mediatek.com>
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*/
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#ifndef _DTS_IOMMU_PORT_MT6886_H_
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#define _DTS_IOMMU_PORT_MT6886_H_
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#include <dt-bindings/memory/mtk-memory-port.h>
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/* table id must be the same as mtk_iommu.h */
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#define MM_TAB (0)
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#define APU_TAB (1)
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/* iova region definition */
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#define NORMAL_DOM (0)
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#define GCE_DOM (1)
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#define LK_RESV_DOM (2)
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#define CCU0_DOM (3)
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#define CCU1_DOM (4)
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#define VDO_DOM (5)
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#define VDEC_DOM (6)
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#define APU_DATA_DOM (0)
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#define APU_SEC_DOM (1)
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#define APU_CODE_DOM (2)
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/* larb0 */
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#define M4U_PORT_L0_DISP_POSTMASK MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 0)
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#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 1)
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#define M4U_PORT_L0_DISP_OVL0_2L_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 2)
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#define M4U_PORT_L0_DISP_OVL1_2L_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 3)
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#define M4U_PORT_L0_DISP_OVL0_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 4)
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#define M4U_PORT_L0_DISP_OVL0_2L_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 5)
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#define M4U_PORT_L0_DISP_OVL1_2L_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 6)
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#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 7)
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#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 8)
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#define M4U_PORT_L0_DISP_UFBC_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 9)
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#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 10)
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/* larb1 */
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#define M4U_PORT_L1_DISP_OVL0_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 0)
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#define M4U_PORT_L1_DISP_OVL0_2L_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 1)
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#define M4U_PORT_L1_DISP_OVL1_2L_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 2)
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#define M4U_PORT_L1_DISP_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 3)
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#define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 4)
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#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 5)
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/* larb2 */
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#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 0)
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#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 1)
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#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 2)
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#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 3)
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#define M4U_PORT_L2_DISP_FAKE0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 4)
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/* larb3--dummy */
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/* larb4 */
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#define M4U_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 0)
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#define M4U_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 1)
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#define M4U_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 2)
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#define M4U_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 3)
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#define M4U_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 4)
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#define M4U_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 5)
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#define M4U_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 6)
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#define M4U_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 7)
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#define M4U_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 8)
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#define M4U_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 9)
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#define M4U_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 10)
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#define M4U_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 11)
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#define M4U_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 12)
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#define M4U_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 13)
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/* larb5--dummy */
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/* larb6--dummy */
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/* larb7 */
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#define M4U_PORT_L7_VENC_RCPU MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 0)
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#define M4U_PORT_L7_VENC_REC MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 1)
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#define M4U_PORT_L7_VENC_BSDNA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 2)
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#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 3)
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#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 4)
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#define M4U_PORT_L7_VENC_NBM_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 5)
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#define M4U_PORT_L7_VENC_NBM_RDMA_LITE MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 6)
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#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 7)
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#define M4U_PORT_L7_JPGENC_C_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 8)
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#define M4U_PORT_L7_JPGENC_Q_TABLE MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 9)
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#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 10)
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#define M4U_PORT_L7_VENC_FCS_NBM_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 11)
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#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 12)
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#define M4U_PORT_L7_VENC_NBM_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 13)
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#define M4U_PORT_L7_VENC_NBM_WDMA_LITE MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 14)
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#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 15)
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#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 16)
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#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 17)
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#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 18)
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#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 19)
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#define M4U_PORT_L7_VENC_FCS_NBM_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 20)
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/* larb8--dummy */
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/* larb9 */
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#define M4U_PORT_L9_IMGI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 0)
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#define M4U_PORT_L9_IMGI_T1_N_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 1)
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#define M4U_PORT_L9_IMGCI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 2)
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#define M4U_PORT_L9_IMGCI_T1_N_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 3)
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#define M4U_PORT_L9_SMTI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 4)
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#define M4U_PORT_L9_SMTI_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 5)
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#define M4U_PORT_L9_YUVO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 6)
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#define M4U_PORT_L9_YUVBO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 7)
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#define M4U_PORT_L9_YUVCO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 8)
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#define M4U_PORT_L9_YUVO_T2_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 9)
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#define M4U_PORT_L9_YUVO_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 10)
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#define M4U_PORT_L9_IMGI_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 11)
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#define M4U_PORT_L9_IMGI_T1_N_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 12)
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#define M4U_PORT_L9_IMGCI_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 13)
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#define M4U_PORT_L9_IMGCI_T1_N_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 14)
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#define M4U_PORT_L9_SMTI_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 15)
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#define M4U_PORT_L9_YUVO_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 16)
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#define M4U_PORT_L9_YUVO_T1_N_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 17)
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#define M4U_PORT_L9_YUVCO_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 18)
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#define M4U_PORT_L9_YUVO_T2_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 19)
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#define M4U_PORT_L9_YUVO_T4_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 20)
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#define M4U_PORT_L9_TNCSTO_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 21)
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#define M4U_PORT_L9_SMTO_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 25)
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/* larb10 */
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#define M4U_PORT_L10_IMG_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 0)
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#define M4U_PORT_L10_IMGCI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 1)
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#define M4U_PORT_L10_IMGCI_D1_N MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 2)
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#define M4U_PORT_L10_DMGI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 3)
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#define M4U_PORT_L10_RECI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 4)
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#define M4U_PORT_L10_TNRAIMI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 5)
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#define M4U_PORT_L10_RECI_D3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 6)
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#define M4U_PORT_L10_RECBI_D2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 7)
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#define M4U_PORT_L10_TNRWI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 8)
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#define M4U_PORT_L10_TNRCI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 9)
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#define M4U_PORT_L10_SMTI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 10)
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#define M4U_PORT_L10_SMTCI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 11)
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#define M4U_PORT_L10_IMG4O_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 12)
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#define M4U_PORT_L10_IMG4CO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 13)
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#define M4U_PORT_L10_TNRMO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 14)
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#define M4U_PORT_L10_SMTO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 15)
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#define M4U_PORT_L10_SMTCO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 16)
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#define M4U_PORT_L10_TNRSI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 17)
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#define M4U_PORT_L10_TNRSO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 18)
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/* larb11 */
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#define M4U_PORT_L11_WPE_RDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 0)
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#define M4U_PORT_L11_WPE_RDMA_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 1)
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#define M4U_PORT_L11_WPE_RDMA_4P_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 2)
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#define M4U_PORT_L11_WPE_RDMA_4P_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 3)
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#define M4U_PORT_L11_PIMGI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 4)
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#define M4U_PORT_L11_PIMGBI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 5)
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#define M4U_PORT_L11_WPE_WDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 6)
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#define M4U_PORT_L11_WPE_WDMA_4P_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 7)
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#define M4U_PORT_L11_WROT_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 8)
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#define M4U_PORT_L11_TESCO_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 9)
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/* larb12 */
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#define M4U_PORT_L12_FDVT_RDA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 0)
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#define M4U_PORT_L12_FDVT_WRA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 1)
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#define M4U_PORT_L12_ME_RDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 2)
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#define M4U_PORT_L12_ME_WDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 3)
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#define M4U_PORT_L12_MEMMG_RDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 4)
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#define M4U_PORT_L12_MEMMG_WDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 5)
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#define M4U_PORT_L12_ME_2ND_RDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 6)
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#define M4U_PORT_L12_ME_2ND_WDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 7)
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#define M4U_PORT_L12_MEMMG_2ND_RDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 8)
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#define M4U_PORT_L12_MEMMG_2ND_WDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 9)
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/* larb13 */
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#define M4U_PORT_L13_CAMSV_CQI_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 0)
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#define M4U_PORT_L13_CAMSV_E1_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 1)
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#define M4U_PORT_L13_FAKE_ENG MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 2)
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#define M4U_PORT_L13_CAMSV_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 3)
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#define M4U_PORT_L13_CAMSV_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 4)
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/* larb14 */
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#define M4U_PORT_L14_CAMSV_CQI_E0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 0)
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#define M4U_PORT_L14_CAMSV_E0_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 1)
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#define M4U_PORT_L14_CAMSV_R_0_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 2)
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#define M4U_PORT_L14_CAMSV_R_1_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 3)
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/* larb15 */
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#define M4U_PORT_L15_VIPI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 0)
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#define M4U_PORT_L15_VIPI_D1_N MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 1)
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#define M4U_PORT_L15_TNCSTI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 2)
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#define M4U_PORT_L15_TNCSI_D4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 3)
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#define M4U_PORT_L15_EECSI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 4)
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#define M4U_PORT_L15_SNRCSI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 5)
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#define M4U_PORT_L15_CSMCSI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 6)
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#define M4U_PORT_L15_SMITI_D4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 7)
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#define M4U_PORT_L15_SMTI_D6 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 8)
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#define M4U_PORT_L15_IMG3O_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 9)
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#define M4U_PORT_L15_IMG3CO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 10)
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#define M4U_PORT_L15_IMG2O_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 11)
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#define M4U_PORT_L15_TNCO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 12)
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#define M4U_PORT_L15_TNCSO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 13)
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#define M4U_PORT_L15_TNCSTO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 14)
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#define M4U_PORT_L15_SMTO_D4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 15)
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#define M4U_PORT_L15_SMTO_D6 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 16)
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/* larb16 */
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#define M4U_PORT_L16_CQI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 0)
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#define M4U_PORT_L16_RAWI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 1)
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#define M4U_PORT_L16_RAWI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 2)
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#define M4U_PORT_L16_RAWI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 3)
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#define M4U_PORT_L16_IMGO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 4)
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#define M4U_PORT_L16_BPCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 5)
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#define M4U_PORT_L16_LSCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 6)
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#define M4U_PORT_L16_UFEO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 7)
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#define M4U_PORT_L16_LTMSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 8)
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#define M4U_PORT_L16_DRZB2NO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 9)
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#define M4U_PORT_L16_AAO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 10)
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#define M4U_PORT_L16_AFO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 11)
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#define M4U_PORT_L16_RGBWI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 12)
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#define M4U_PORT_L16_RAW_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 13)
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#define M4U_PORT_L16_RAW_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 14)
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#define M4U_PORT_L16_RAW_R_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 15)
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/* larb17 */
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#define M4U_PORT_L17_YUVO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 0)
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#define M4U_PORT_L17_YUVO_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 1)
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#define M4U_PORT_L17_YUVO_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 2)
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#define M4U_PORT_L17_YUVO_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 3)
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#define M4U_PORT_L17_YUV_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 4)
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#define M4U_PORT_L17_TCYSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 5)
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#define M4U_PORT_L17_DRZHNO_R9 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 6)
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#define M4U_PORT_L17_YUV_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 7)
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/* larb18--dummy */
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/* larb19 */
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#define M4U_PORT_L19_CCUI MTK_M4U_PORT_ID(MM_TAB, CCU0_DOM, 19, 0)
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#define M4U_PORT_L19_CCUO MTK_M4U_PORT_ID(MM_TAB, CCU0_DOM, 19, 1)
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#define M4U_PORT_L19_CCUI2 MTK_M4U_PORT_ID(MM_TAB, CCU1_DOM, 19, 2)
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#define M4U_PORT_L19_CCUO2 MTK_M4U_PORT_ID(MM_TAB, CCU1_DOM, 19, 3)
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#define M4U_PORT_L19_DVS_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 4)
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#define M4U_PORT_L19_DVS_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 5)
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#define M4U_PORT_L19_DVP_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 6)
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#define M4U_PORT_L19_DVP_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 7)
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#define M4U_PORT_L19_DHZE_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 8)
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#define M4U_PORT_L19_DHZE_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 9)
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#define M4U_PORT_L19_CCU_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 10)
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#define M4U_PORT_L19_CCU_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 19, 11)
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|
|
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/* larb20--dummy */
|
|
/* larb21--dummy */
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|
|
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/* larb22 */
|
|
#define M4U_PORT_L22_WPE_RDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 0)
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#define M4U_PORT_L22_WPE_RDMA_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 1)
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#define M4U_PORT_L22_WPE_RDMA_4P_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 2)
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#define M4U_PORT_L22_WPE_RDMA_4P_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 3)
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#define M4U_PORT_L22_PIMGI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 4)
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#define M4U_PORT_L22_PIMGBI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 5)
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#define M4U_PORT_L22_WPE_WDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 6)
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#define M4U_PORT_L22_WPE_WDMA_4P_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 7)
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#define M4U_PORT_L22_WROT_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 8)
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#define M4U_PORT_L22_TESCO_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 9)
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|
|
|
/* larb23 */
|
|
#define M4U_PORT_L23_WPE_RDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 0)
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#define M4U_PORT_L23_WPE_RDMA_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 1)
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#define M4U_PORT_L23_WPE_RDMA_4P_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 2)
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#define M4U_PORT_L23_WPE_RDMA_4P_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 3)
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#define M4U_PORT_L23_PIMGI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 4)
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#define M4U_PORT_L23_PIMGBI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 5)
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#define M4U_PORT_L23_WPE_WDMA_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 6)
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|
#define M4U_PORT_L23_WPE_WDMA_4P_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 7)
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|
#define M4U_PORT_L23_WROT_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 8)
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|
#define M4U_PORT_L23_TESCO_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 9)
|
|
|
|
/* larb24--dummy */
|
|
|
|
/* larb25 */
|
|
#define M4U_PORT_L25_MRAW0_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 0)
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#define M4U_PORT_L25_MRAW0_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 1)
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#define M4U_PORT_L25_MRAW2_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 2)
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#define M4U_PORT_L25_MRAW2_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 3)
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|
#define M4U_PORT_L25_PDAI_A_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 4)
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|
#define M4U_PORT_L25_PDAI_A_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 5)
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#define M4U_PORT_L25_PDAI_A_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 6)
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#define M4U_PORT_L25_PDAI_A_3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 7)
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#define M4U_PORT_L25_PDAI_A_4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 8)
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#define M4U_PORT_L25_PDAO_A_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 9)
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#define M4U_PORT_L25_PDAI_B_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 10)
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#define M4U_PORT_L25_PDAI_B_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 11)
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#define M4U_PORT_L25_PDAI_B_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 12)
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#define M4U_PORT_L25_PDAI_B_3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 13)
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#define M4U_PORT_L25_PDAI_B_4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 14)
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#define M4U_PORT_L25_PDAO_B_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 15)
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#define M4U_PORT_L25_MRAW0_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 16)
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#define M4U_PORT_L25_MRAW2_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 17)
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#define M4U_PORT_L25_MRAW_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 18)
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#define M4U_PORT_L25_MRAW_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 19)
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/* larb26 */
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#define M4U_PORT_L26_MRAW1_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 0)
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#define M4U_PORT_L26_MRAW1_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 1)
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#define M4U_PORT_L26_MRAW3_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 2)
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#define M4U_PORT_L26_MRAW3_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 3)
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#define M4U_PORT_L26_MRAW4_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 4)
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#define M4U_PORT_L26_MRAW4_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 5)
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#define M4U_PORT_L26_MRAW1_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 6)
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#define M4U_PORT_L26_MRAW3_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 7)
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#define M4U_PORT_L26_MRAW4_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 8)
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#define M4U_PORT_L26_MRAW_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 9)
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#define M4U_PORT_L26_MRAW_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 10)
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|
|
|
/* larb27 */
|
|
#define M4U_PORT_L27_ADL_IPUI MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 0)
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#define M4U_PORT_L27_ADL_IPUO MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 1)
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#define M4U_PORT_L27_ADL_IPU3O MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 2)
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#define M4U_PORT_L27_UISP_CQI_U1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 3)
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#define M4U_PORT_L27_UISP_IMGO_U1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 4)
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#define M4U_PORT_L27_UISP_YUVO_U1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 5)
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#define M4U_PORT_L27_UISP_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 6)
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#define M4U_PORT_L27_UISP_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 7)
|
|
|
|
/* larb28 */
|
|
#define M4U_PORT_L28_IMGI_TI_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 0)
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|
#define M4U_PORT_L28_IMGI_TI_N_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 1)
|
|
#define M4U_PORT_L28_IMGCI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 2)
|
|
#define M4U_PORT_L28_IMGCI_T1_N_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 3)
|
|
#define M4U_PORT_L28_SMTI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 4)
|
|
#define M4U_PORT_L28_SMTI_T4_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 5)
|
|
#define M4U_PORT_L28_TNCSTI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 6)
|
|
#define M4U_PORT_L28_TNCSTI_T4_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 7)
|
|
#define M4U_PORT_L28_LTMSTI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 8)
|
|
#define M4U_PORT_L28_YUVO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 9)
|
|
#define M4U_PORT_L28_YUVBO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 10)
|
|
#define M4U_PORT_L28_YUVCO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 11)
|
|
#define M4U_PORT_L28_YUVO_T2_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 12)
|
|
#define M4U_PORT_L28_YUVO_T4_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 13)
|
|
#define M4U_PORT_L28_TNCSO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 14)
|
|
#define M4U_PORT_L28_TMCSTO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 15)
|
|
#define M4U_PORT_L28_SMTO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 16)
|
|
#define M4U_PORT_L28_SMTO_T4_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 17)
|
|
#define M4U_PORT_L28_LTMSO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 18)
|
|
#define M4U_PORT_L28_DBGO_T1_N_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 19)
|
|
|
|
/* larb29 */
|
|
#define M4U_PORT_L29_CAMSV_CQI_E2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 0)
|
|
#define M4U_PORT_L29_CAMSV_CQI_E3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 1)
|
|
#define M4U_PORT_L29_CAMSV_CQI_E4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 2)
|
|
#define M4U_PORT_L29_CAMSV_CQI_E5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 3)
|
|
#define M4U_PORT_L29_CAMSV_E2_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 4)
|
|
#define M4U_PORT_L29_CAMSV_E3_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 5)
|
|
#define M4U_PORT_L29_CAMSV_E4_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 6)
|
|
#define M4U_PORT_L29_CAMSV_E5_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 7)
|
|
#define M4U_PORT_L29_CAMSV_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 8)
|
|
#define M4U_PORT_L29_CAMSV_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 9)
|
|
|
|
/* larb30 */
|
|
#define M4U_PORT_L30_CQI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 0)
|
|
#define M4U_PORT_L30_RAWI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 1)
|
|
#define M4U_PORT_L30_RAWI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 2)
|
|
#define M4U_PORT_L30_RAWI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 3)
|
|
#define M4U_PORT_L30_IMGO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 4)
|
|
#define M4U_PORT_L30_BPCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 5)
|
|
#define M4U_PORT_L30_LSCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 6)
|
|
#define M4U_PORT_L30_UFEO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 7)
|
|
#define M4U_PORT_L30_LTMSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 8)
|
|
#define M4U_PORT_L30_DRZB2NO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 9)
|
|
#define M4U_PORT_L30_AAO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 10)
|
|
#define M4U_PORT_L30_AFO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 11)
|
|
#define M4U_PORT_L30_RGBWI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 12)
|
|
#define M4U_PORT_L30_RAW_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 13)
|
|
#define M4U_PORT_L30_RAW_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 14)
|
|
#define M4U_PORT_L30_RAW_R_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 15)
|
|
|
|
/* larb31--dummy */
|
|
/* larb32--dummy */
|
|
/* larb33--dummy */
|
|
|
|
/* larb34 */
|
|
#define M4U_PORT_L34_YUVO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 0)
|
|
#define M4U_PORT_L34_YUVO_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 1)
|
|
#define M4U_PORT_L34_YUVO_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 2)
|
|
#define M4U_PORT_L34_YUVO_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 3)
|
|
#define M4U_PORT_L34_YUV_R_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 4)
|
|
#define M4U_PORT_L34_TCYSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 5)
|
|
#define M4U_PORT_L34_DRZHNO_R9 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 6)
|
|
#define M4U_PORT_L34_YUV_R_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 34, 7)
|
|
|
|
/* fake larb35 */
|
|
#define M4U_PORT_L35_CCU0 MTK_M4U_PORT_ID(MM_TAB, CCU0_DOM, 35, 0)
|
|
#define M4U_PORT_L35_CCU1 MTK_M4U_PORT_ID(MM_TAB, CCU1_DOM, 35, 1)
|
|
|
|
/* fake larb36 */
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#define M4U_PORT_L36_VIDEO_uP MTK_M4U_PORT_ID(MM_TAB, VDO_DOM, 36, 0)
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#define M4U_PORT_L36_GCE_D_M MTK_M4U_PORT_ID(MM_TAB, GCE_DOM, 36, 1)
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#define M4U_PORT_L36_GCE_M_M MTK_M4U_PORT_ID(MM_TAB, GCE_DOM, 36, 2)
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/* fake larb37 */
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#define M4U_PORT_L37_APU_CODE MTK_M4U_PORT_ID(APU_TAB, APU_CODE_DOM, 37, 0)
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#define M4U_PORT_L37_APU_DATA MTK_M4U_PORT_ID(APU_TAB, APU_DATA_DOM, 37, 1)
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#endif /* _DTS_IOMMU_PORT_MT6886_H_ */
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