1118 lines
40 KiB
Text
1118 lines
40 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/*
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* Device Tree defines for LCM settings
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include "mtk_lcm_settings.h"
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&pio {
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r66451_fhdp_dphy_cmd_tianma_120hz: r66451-fhdp-dphy-cmd-tianma-120hz {
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compatible = "mediatek,r66451_fhdp_dphy_cmd_tianma_120hz";
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lcm-version = <0>;
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lcm-params{
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compatible = "mediatek,lcm-params";
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lcm-params-name = "r66451-fhdp-dphy-cmd-tianma-120hz";
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lcm-params-types = <MTK_LCM_FUNC_DSI>;
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lcm-params-resolution = <1080 2340>;
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lcm-params-physical-width = <70>;
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lcm-params-physical-height = <152>;
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/* lk support */
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lcm-params-lk {
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compatible = "mediatek,lcm-params-lk";
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lcm-params-lk-ctrl;
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lcm-params-lk-lcm-if;
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lcm-params-lk-lcm-cmd-if;
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lcm-params-lk-io-select-mode;
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lcm-params-lk-lcm-x;
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lcm-params-lk-lcm-y;
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lcm-params-lk-virtual-resolution = <0 0>;
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lcm-params-lk-od-table-size;
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lcm-params-lk-od-table;
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};
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lcm-params-lk-round-corner {
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compatible = "mediatek,lcm-params-lk-round-corner";
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lcm-params-lk-rc-round-corner-en = <0>;
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lcm-params-lk-rc-is-notch;
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lcm-params-lk-rc-full-content = <0>;
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lcm-params-lk-rc-width;
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lcm-params-lk-rc-height;
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lcm-params-lk-rc-width-bot;
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lcm-params-lk-rc-height-bot;
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lcm-params-lk-rc-top-size;
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lcm-params-lk-rc-top-size-left;
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lcm-params-lk-rc-top-size-right;
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lcm-params-lk-rc-bottom-size;
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lcm-params-lk-rc-pattern-name;
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};
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lcm-params-dbi {
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compatible = "mediatek,lcm-params-dbi";
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/* future reserved for dbi interfaces */
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};
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lcm-params-dpi {
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compatible = "mediatek,lcm-params-dpi";
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/* future reserved for dpi interfaces */
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};
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lcm-params-dsi {
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compatible = "mediatek,lcm-params-dsi";
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lcm-params-dsi-density = <480>;
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lcm-params-dsi-lanes = <4>;
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lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
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lcm-params-dsi-phy-type = <MTK_LCM_MIPI_DPHY>;
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lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_LPM>,
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<MTK_MIPI_DSI_MODE_EOT_PACKET>,
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<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
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lcm-params-dsi-mode-flags-doze-on;
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lcm-params-dsi-mode-flags-doze-off;
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lcm-params-dsi-need-fake-resolution;
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lcm-params-dsi-fake-resolution = <1080 2340>;
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lcm-gpio-list = <&pio 42 0>, /* gpio list*/
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<&pio 28 0>,
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<&pio 29 0>;
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pinctrl-names = "gpio1", "gpio2", "gpio3";
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pinctrl-0;
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pinctrl-1;
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pinctrl-2;
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status = "okay";
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lcm-params-dsi-default-mode = <0>;
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lcm-params-dsi-mode-count = <3>;
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lcm-params-dsi-mode-list =
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<0 1080 2340 60>,
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<1 1080 2340 90>,
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<2 1080 2340 120>;
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lcm-params-dsi-fps-0-1080-2340-60 {
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compatible = "mediatek,lcm-dsi-fps-0-1080-2340-60";
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lcm-params-dsi-voltage;
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lcm-params-dsi-fake = <0>;
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/* drm-display-mode */
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lcm-params-dsi-vrefresh = <60>;
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lcm-params-dsi-vertical-sync-active = <2>;
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lcm-params-dsi-vertical-backporch = <8>;
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lcm-params-dsi-vertical-frontporch = <20>;
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lcm-params-dsi-vertical-active-line = <2340>;
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lcm-params-dsi-horizontal-sync-active = <10>;
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lcm-params-dsi-horizontal-backporch = <20>;
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lcm-params-dsi-horizontal-frontporch = <40>;
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lcm-params-dsi-horizontal-active-pixel = <1080>;
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lcm-params-dsi-pixel-clock = <163530>;
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lcm-params-dsi-hskew;
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lcm-params-dsi-vscan;
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/* mtk-panel-params */
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lcm-params-dsi-lk-pll-clock = <215>;
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lcm-params-dsi-lk-data-rate = <0>;
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lcm-params-dsi-pll-clock = <420>;
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lcm-params-dsi-data-rate = <840>;
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lcm-params-dsi-vfp-for-low-power = <620>;
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lcm-params-dsi-ssc-enable;
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lcm-params-dsi-ssc-range;
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lcm-params-dsi-lcm-color-mode =
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<MTK_LCM_COLOR_MODE_DISPLAY_P3>;
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lcm-params-dsi-min-luminance;
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lcm-params-dsi-average-luminance;
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lcm-params-dsi-max-luminance;
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lcm-params-dsi-round-corner-en = <0>;
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lcm-params-dsi-corner-pattern-height;
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lcm-params-dsi-corner-pattern-height-bot;
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lcm-params-dsi-corner-pattern-tp-size;
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lcm-params-dsi-corner-pattern-tp-size-left;
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lcm-params-dsi-corner-pattern-tp-size-right;
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lcm-params-dsi-corner-pattern-name;
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lcm-params-dsi-physical-width-um = <70200>;
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lcm-params-dsi-physical-height-um = <152100>;
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lcm-params-dsi-output-mode =
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<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
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lcm-params-dsi-lcm-cmd-if;
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lcm-params-dsi-hbm-en-time;
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lcm-params-dsi-hbm-dis-time;
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lcm-params-dsi-lcm-index;
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lcm-params-dsi-wait-sof-before-dec-vfp;
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lcm-params-dsi-doze-delay;
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lcm-params-dsi-lfr-enable;
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lcm-params-dsi-lfr-minimum-fps;
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lcm-params-dsi-msync2-enable;
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lcm-params-dsi-max-vfp-for-msync;
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/* lane swap */
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lcm-params-dsi-lane-swap-en;
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lcm-params-dsi-lane-swap0;
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lcm-params-dsi-lane-swap1;
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/* esd check table */
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lcm-params-dsi-cust-esd-check = <0>;
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lcm-params-dsi-esd-check-enable = <1>;
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lcm-params-dsi-lcm-esd-check-table0 = [53 01 24];
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lcm-params-dsi-lcm-esd-check-table1;
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lcm-params-dsi-lcm-esd-check-table2;
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/* fpga support */
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lcm-params-dsi-fpga-params-0-1080-2340-60 {
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compatible = "mediatek,lcm-dsi-fpga-params";
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lcm-params-dsi-lk-pll-div = <0 0>;
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lcm-params-dsi-lk-fbk-div = <1>;
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};
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/* lk support */
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lcm-params-dsi-lk-params-0-1080-2340-60 {
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compatible = "mediatek,lcm-dsi-lk-params";
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lcm-params-dsi-lk-mode = <MTK_LK_CMD_MODE>;
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lcm-params-dsi-lk-switch-mode =
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<MTK_LK_SYNC_PULSE_VDO_MODE>;
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lcm-params-dsi-lk-switch-mode-enable = <0>;
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lcm-params-dsi-lk-dsi-wmem-conti;
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lcm-params-dsi-lk-dsi-rmem-conti;
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lcm-params-dsi-lk-vc-num;
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lcm-params-dsi-lk-data-format =
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<MTK_LCM_COLOR_ORDER_RGB>,
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<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
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<MTK_LCM_DSI_PADDING_ON_LSB>,
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<MTK_LCM_DSI_FORMAT_RGB888>;
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lcm-params-dsi-lk-intermediat-buffer-num;
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lcm-params-dsi-lk-ps =
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<MTK_LCM_PACKED_PS_24BIT_RGB888>;
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lcm-params-dsi-lk-word-count;
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lcm-params-dsi-lk-packet-size = <256>;
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lcm-params-dsi-lk-horizontal-blanking-pixel;
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lcm-params-dsi-lk-bllp;
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lcm-params-dsi-lk-line-byte;
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lcm-params-dsi-lk-horizontal-sync-active-byte;
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lcm-params-dsi-lk-horizontal-backporch-byte;
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lcm-params-dsi-lk-horizontal-frontporch-byte;
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lcm-params-dsi-lk-rgb-byte;
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lcm-params-dsi-lk-horizontal-sync-active-word-count;
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lcm-params-dsi-lk-horizontal-backporch-word-count;
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lcm-params-dsi-lk-horizontal-frontporch-word-count;
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lcm-params-dsi-lk-pll-select;
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lcm-params-dsi-lk-pll-div;
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lcm-params-dsi-lk-fbk-div;
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lcm-params-dsi-lk-fbk-sel;
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lcm-params-dsi-lk-rg = <0 0 0>;
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lcm-params-dsi-lk-dsi-clock;
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lcm-params-dsi-lk-ssc-disable;
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lcm-params-dsi-lk-ssc-range;
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lcm-params-dsi-lk-compatibility-for-nvk;
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lcm-params-dsi-lk-cont-clock;
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lcm-params-dsi-lk-ufoe-enable;
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lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
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lcm-params-dsi-lk-edp-panel;
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lcm-params-dsi-lk-lcm-int-te-monitor;
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lcm-params-dsi-lk-lcm-int-te-period;
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lcm-params-dsi-lk-lcm-ext-te-monitor;
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lcm-params-dsi-lk-lcm-ext-te-period;
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lcm-params-dsi-lk-noncont-clock;
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lcm-params-dsi-lk-noncont-clock-period;
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lcm-params-dsi-lk-clk-lp-per-line-enable = <0>;
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lcm-params-dsi-lk-dual-dsi-type;
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lcm-params-dsi-lk-mixmode-enable;
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lcm-params-dsi-lk-mixmode-mipi-clock;
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lcm-params-dsi-lk-pwm-fps;
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lcm-params-dsi-lk-pll-clock-lp;
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lcm-params-dsi-lk-ulps-sw-enable;
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lcm-params-dsi-lk-null-packet-en;
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lcm-params-dsi-lk-vact-fps;
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lcm-params-dsi-lk-send-frame-enable;
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lcm-params-dsi-lk-lfr-enable;
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lcm-params-dsi-lk-lfr-mode;
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lcm-params-dsi-lk-lfr-type;
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lcm-params-dsi-lk-lfr-skip-num;
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lcm-params-dsi-lk-ext-te-edge;
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lcm-params-dsi-lk-eint-disable;
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lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
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};
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lcm-params-dsi-dsc-params-0-1080-2340-60 {
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compatible =
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"mediatek,lcm-params-dsi-dsc-params";
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lcm-params-dsi-dsc-enable = <1>;
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lcm-params-dsi-dsc-enable-lk = <1>;
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lcm-params-dsi-dsc-ver = <17>;
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lcm-params-dsi-dsc-slice-mode = <1>;
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lcm-params-dsi-dsc-rgb-swap = <0>;
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lcm-params-dsi-dsc-cfg = <34>;
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lcm-params-dsi-dsc-rct-on = <1>;
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lcm-params-dsi-dsc-bit-per-channel = <8>;
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lcm-params-dsi-dsc-line-buf-depth = <9>;
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lcm-params-dsi-dsc-bp-enable = <1>;
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lcm-params-dsi-dsc-bit-per-pixel = <128>;
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lcm-params-dsi-dsc-pic-height = <2340>;
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lcm-params-dsi-dsc-pic-width = <1080>;
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lcm-params-dsi-dsc-slice-height = <20>;
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lcm-params-dsi-dsc-slice-width = <540>;
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lcm-params-dsi-dsc-chunk-size = <540>;
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lcm-params-dsi-dsc-xmit-delay = <512>;
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lcm-params-dsi-dsc-dec-delay = <526>;
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lcm-params-dsi-dsc-scale-value = <32>;
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lcm-params-dsi-dsc-increment-interval = <488>;
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lcm-params-dsi-dsc-decrement-interval = <7>;
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lcm-params-dsi-dsc-line-bpg-offset = <12>;
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lcm-params-dsi-dsc-nfl-bpg-offset = <1294>;
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lcm-params-dsi-dsc-slice-bpg-offset = <1302>;
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lcm-params-dsi-dsc-initial-offset = <6144>;
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lcm-params-dsi-dsc-final-offset = <4336>;
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lcm-params-dsi-dsc-flatness-minqp = <3>;
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lcm-params-dsi-dsc-flatness-maxqp = <12>;
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lcm-params-dsi-dsc-rc-model-size = <8192>;
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lcm-params-dsi-dsc-rc-edge-factor = <6>;
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lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
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lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
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lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
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lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
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};
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lcm-params-dsi-phy-timcon-params-0-1080-2340-60 {
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compatible =
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"mediatek,lcm-params-dsi-phy-timcon";
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lcm-params-dsi-phy-timcon-hs-trail;
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lcm-params-dsi-phy-timcon-hs-prpr;
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lcm-params-dsi-phy-timcon-hs-zero;
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lcm-params-dsi-phy-timcon-lpx;
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lcm-params-dsi-phy-timcon-ta-get;
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lcm-params-dsi-phy-timcon-ta-sure;
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lcm-params-dsi-phy-timcon-ta-go;
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lcm-params-dsi-phy-timcon-da-hs-exit;
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lcm-params-dsi-phy-timcon-clk-trail;
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lcm-params-dsi-phy-timcon-cont-det;
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lcm-params-dsi-phy-timcon-da-hs-sync;
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lcm-params-dsi-phy-timcon-clk-zero;
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lcm-params-dsi-phy-timcon-clk-prpr;
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lcm-params-dsi-phy-timcon-clk-exit;
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lcm-params-dsi-phy-timcon-clk-post;
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/* lk support */
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lcm-params-dsi-phy-timcon-lk-hs-trail;
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lcm-params-dsi-phy-timcon-lk-hs-zero;
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lcm-params-dsi-phy-timcon-lk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-lpx;
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lcm-params-dsi-phy-timcon-lk-ta-sack;
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lcm-params-dsi-phy-timcon-lk-ta-get;
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lcm-params-dsi-phy-timcon-lk-ta-sure;
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lcm-params-dsi-phy-timcon-lk-ta-go;
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lcm-params-dsi-phy-timcon-lk-clk-trail;
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lcm-params-dsi-phy-timcon-lk-clk-zero;
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lcm-params-dsi-phy-timcon-lk-lpx-wait;
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lcm-params-dsi-phy-timcon-lk-cont-det;
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lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-clk-hs-post = <36>;
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lcm-params-dsi-phy-timcon-lk-da-hs-exit;
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lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
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};
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lcm-params-dsi-dyn-params-0-1080-2340-60 {
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compatible =
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"mediatek,lcm-params-dsi-dyn";
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lcm-params-dsi-dyn-switch-en;
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lcm-params-dsi-dyn-pll-clk;
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lcm-params-dsi-dyn-data-rate;
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lcm-params-dsi-dyn-vsa;
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lcm-params-dsi-dyn-vbp;
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lcm-params-dsi-dyn-vfp;
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lcm-params-dsi-dyn-vfp-lp-dyn;
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lcm-params-dsi-dyn-vac;
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lcm-params-dsi-dyn-hsa;
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lcm-params-dsi-dyn-hbp;
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lcm-params-dsi-dyn-hfp;
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lcm-params-dsi-dyn-hac;
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lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
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};
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lcm-params-dsi-dyn-fps-params-0-1080-2340-60 {
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compatible =
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"mediatek,lcm-params-dsi-dyn-fps";
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lcm-params-dsi-dyn-fps-switch-en;
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lcm-params-dsi-dyn-fps-vact-timing-fps;
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lcm-params-dsi-dyn-fps-data-rate = <400>;
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lcm-params-dsi-dyn-fps-dfps-cmd-table0;
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lcm-params-dsi-dyn-fps-dfps-cmd-table1;
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lcm-params-dsi-dyn-fps-dfps-cmd-table2;
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lcm-params-dsi-dyn-fps-dfps-cmd-table3;
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lcm-params-dsi-dyn-fps-dfps-cmd-table4;
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lcm-params-dsi-dyn-fps-dfps-cmd-table5;
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lcm-params-dsi-dyn-fps-dfps-cmd-table6;
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lcm-params-dsi-dyn-fps-dfps-cmd-table7;
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lcm-params-dsi-dyn-fps-dfps-cmd-table8;
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lcm-params-dsi-dyn-fps-dfps-cmd-table9;
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lcm-params-dsi-dyn-fps-dfps-cmd-table10;
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lcm-params-dsi-dyn-fps-dfps-cmd-table11;
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lcm-params-dsi-dyn-fps-dfps-cmd-table12;
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lcm-params-dsi-dyn-fps-dfps-cmd-table13;
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lcm-params-dsi-dyn-fps-dfps-cmd-table14;
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lcm-params-dsi-dyn-fps-dfps-cmd-table15;
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lcm-params-dsi-dyn-fps-dfps-cmd-table16;
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lcm-params-dsi-dyn-fps-dfps-cmd-table17;
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lcm-params-dsi-dyn-fps-dfps-cmd-table18;
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lcm-params-dsi-dyn-fps-dfps-cmd-table19;
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};
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};
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lcm-params-dsi-fps-1-1080-2340-90 {
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compatible = "mediatek,lcm-dsi-fps-1-1080-2340-90";
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lcm-params-dsi-voltage;
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lcm-params-dsi-fake = <0>;
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/* drm-display-mode */
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lcm-params-dsi-vrefresh = <90>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <8>;
|
|
lcm-params-dsi-vertical-frontporch = <20>;
|
|
lcm-params-dsi-vertical-active-line = <2340>;
|
|
lcm-params-dsi-horizontal-sync-active = <10>;
|
|
lcm-params-dsi-horizontal-backporch = <20>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <245295>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock;
|
|
lcm-params-dsi-data-rate = <840>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode =
|
|
<MTK_LCM_COLOR_MODE_DISPLAY_P3>;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um = <70200>;
|
|
lcm-params-dsi-physical-height-um = <152100>;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [53 01 24];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
lcm-params-dsi-dsc-params-1-1080-2340-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <0>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2340>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <20>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <488>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <1294>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <1302>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-1-1080-2340-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-1-1080-2340-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en;
|
|
lcm-params-dsi-dyn-pll-clk;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-1-1080-2340-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate = <570>;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-2-1080-2340-120 {
|
|
compatible = "mediatek,lcm-dsi-fps-2-1080-2340-120";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <120>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <8>;
|
|
lcm-params-dsi-vertical-frontporch = <20>;
|
|
lcm-params-dsi-vertical-active-line = <2340>;
|
|
lcm-params-dsi-horizontal-sync-active = <10>;
|
|
lcm-params-dsi-horizontal-backporch = <20>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <327060>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock;
|
|
lcm-params-dsi-data-rate = <840>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode =
|
|
<MTK_LCM_COLOR_MODE_DISPLAY_P3>;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um = <70200>;
|
|
lcm-params-dsi-physical-height-um = <152100>;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [53 01 24];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
lcm-params-dsi-dsc-params-2-1080-2340-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <0>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2340>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <20>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <488>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <1294>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <1302>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-2-1080-2340-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-2-1080-2340-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en;
|
|
lcm-params-dsi-dyn-pll-clk;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-2-1080-2340-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate = <840>;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lcm-ops {
|
|
compatible = "mediatek,lcm-ops";
|
|
lcm-ops-dbi {
|
|
compatible = "mediatek,lcm-ops-dbi";
|
|
/* future reserved for dbi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dpi {
|
|
compatible = "mediatek,lcm-ops-dpi";
|
|
/* future reserved for dpi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dsi {
|
|
compatible = "mediatek,lcm-ops-dsi";
|
|
prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 c8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0d],
|
|
[B6 51 00 06 23 8A 13 1A 05 04],
|
|
[FA 05 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 51 0F ff],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 44 08 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 2a 00 00 04 37],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 2b 00 00 09 23],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 c8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 D4 93],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 2a],
|
|
[50 42 58 81 2D 00 00 00],
|
|
[00 00 00 6B 00 00 00 00],
|
|
[00 00 00 00 10 00 FF D4],
|
|
[0E 00 00 00 00 00 0F 00],
|
|
[53 18 0F 00 00 00 00 00],
|
|
[00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F7 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 81],
|
|
[F8 11 00 00 89 30],
|
|
[80 09 24 04 38],
|
|
[00 14 02 1c 02 1c 02 00 02 0e],
|
|
[00 20 01 e8 00 07 00 0c 05 0e],
|
|
[05 16 18 00 10 f0 03 0c 20 00],
|
|
[06 0b 0b 33 0e 1c 2a 38 46 54],
|
|
[62 69 70 77 79 7b 7d 7e 01 02],
|
|
[01 00 09 40 09 be 19 fc 19 fa],
|
|
[19 f8 1a 38 1a 78 1a b6 2a f6],
|
|
[2b 34 2b 74 3b 74 6b f4 00 00],
|
|
[00 00 00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 EB 8B 8B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 DF 50 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F3 50 00 00 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F2 11],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F3 01 00 00 00 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 F4 00 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F2 19],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 DF 50 42],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 84],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E6 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 11],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
unprepare-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 28],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 10],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-display-on-table;
|
|
|
|
lcm-update-table = [MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 05 39 02],
|
|
/*2a is of data[1] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2a],
|
|
/*x0-msb is of data[1] bit8 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_MSB_BIT 03 01 08 00],
|
|
/*x0-lsb is of data[1] bit16 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_LSB_BIT 03 01 10 00],
|
|
/*x1-msb is of data[1] bit24 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_MSB_BIT 03 01 18 00],
|
|
/*x0-lsb is of data[2] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_LSB_BIT 03 02 00 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 05 39 02],
|
|
/*2b is of data[1] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2b],
|
|
/*y0-msb is of data[1] bit8 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_MSB_BIT 03 01 08 00],
|
|
/*y0-lsb is of data[1] bit16 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_LSB_BIT 03 01 10 00],
|
|
/*y1-msb is of data[1] bit24 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_MSB_BIT 03 01 18 00],
|
|
/*y0-lsb is of data[2] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_LSB_BIT 03 02 00 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 2c 39 09],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM_UNFORCE 00],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-backlight-mask = <0xfff>;
|
|
set-backlight-cmdq-table =
|
|
/* runtime input count, data id*/
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 0f ff],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-aod-light-mask = <0xfff>;
|
|
set-aod-light-table =
|
|
/* runtime input count, data id*/
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 0f ff],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
ata-id-value-data;
|
|
ata-check-table;
|
|
|
|
compare-id-value-data = [02];
|
|
compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 bf],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-enable-start-table;
|
|
|
|
doze-enable-table;
|
|
|
|
doze-disable-table;
|
|
|
|
doze-area-table;
|
|
|
|
doze-post-disp-on-table;
|
|
|
|
hbm-set-cmdq-switch-id;
|
|
hbm-set-cmdq-switch-on;
|
|
hbm-set-cmdq-switch-off;
|
|
hbm-set-cmdq-table;
|
|
|
|
/* fps switch cmd for high frame rate feature */
|
|
lcm-ops-dsi-fps-switch-after-poweron {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
|
|
fps-switch-0-1080-2340-60-table;
|
|
|
|
fps-switch-1-1080-2340-90-table;
|
|
|
|
fps-switch-2-1080-2340-120-table;
|
|
};
|
|
|
|
lcm-ops-dsi-fps-switch-before-powerdown {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
|
|
fps-switch-0-1080-2340-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0d],
|
|
[B6 51 00 06 23 8A 13 1A],
|
|
[05 04 FA 05 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F1 2A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C1 0C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 07],
|
|
[C2 09 24 0E 00 00 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[C1 94 42 00 16 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 86],
|
|
[CF 64 0B 00],
|
|
[28 02 4B 02 DE 0B 77 0B],
|
|
[8B 00 00 00 00 00 00 00],
|
|
[00 00 01 01 01 00 3D 00],
|
|
[CD 00 CD 00 CD 00 CD 01],
|
|
[00 01 00 03 98 03 98 03],
|
|
[98 03 98 03 98 00 3D 00],
|
|
[CD 00 CD 00 CD 00 CD 01],
|
|
[00 01 00 03 98 03 98 03],
|
|
[98 03 98 03 98 01 42 01],
|
|
[42 01 42 01 42 01 42 01],
|
|
[42 01 42 01 42 01 42 01],
|
|
[42 01 42 01 42 1C 1C 1C],
|
|
[1C 1C 1C 1C 1C 1C 1C 1C],
|
|
[1C 00 88 00 B1 00 B1 09],
|
|
[A6 09 A6 09 A4 09 A4 09],
|
|
[A4 09 A4 09 A4 09 A4 0F],
|
|
[C3 19],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 13],
|
|
[C4 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[02 00 00 00 68 00 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0a],
|
|
[D7 00 69 34],
|
|
[00 A0 0A 00 00 75],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 3c],
|
|
[D8 00 00 00],
|
|
[00 00 00 00 00 00 74 00],
|
|
[74 00 74 00 74 00 74 05],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 75 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 22 00 65 00 00 00 2F],
|
|
[00 00 00 00 00 00 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 32],
|
|
[BB 59 C8 C8],
|
|
[C8 C8 C8 C8 C8 C8 C8 4A],
|
|
[48 46 44 42 40 3E 3C 3A],
|
|
[00 FF FF FF FF FF FF FF],
|
|
[FF FF 04 00 01 01 00 04],
|
|
[69 5A 00 0B 76 0F FF 0F],
|
|
[FF 0F FF 14 81 F4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 E8 00 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 E4 00 0A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 84],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0a],
|
|
[E4 33 B4 00],
|
|
[00 00 75 04 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E6 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-1-1080-2340-90-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0d],
|
|
[B6 59 00 06],
|
|
[23 8A 13 1A],
|
|
[05 04 FA 05 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F1 2A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C1 0C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 07],
|
|
[C2 09 24 0E 00 00 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[C1 94 42 00 16 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 86],
|
|
[CF 64 0B 00],
|
|
[28 02 4B 02 DE 0B 77 0B],
|
|
[8B 02 02 02 02 02 02 02],
|
|
[02 02 03 03 03 00 3D 00],
|
|
[CD 00 CD 00 CD 00 CD 01],
|
|
[00 01 00 03 98 03 98 03],
|
|
[98 03 98 03 98 00 3D 00],
|
|
[CD 00 CD 00 CD 00 CD 01],
|
|
[00 01 00 03 98 03 98 03],
|
|
[98 03 98 03 98 01 42 01],
|
|
[42 01 42 01 42 01 42 01],
|
|
[42 01 42 01 42 01 42 01],
|
|
[42 01 42 01 42 1C 1C 1C],
|
|
[1C 1C 1C 1C 1C 1C 1C 1C],
|
|
[1C 00 88 00 B1 00 B1 09],
|
|
[A6 09 A6 09 A4 09 A4 09],
|
|
[A4 09 A4 09 A4 09 A4 0F],
|
|
[C3 19],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 13],
|
|
[C4 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[02 00 00 00 48 00 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0a],
|
|
[D7 00 69 34],
|
|
[00 A0 0A 00 00 4E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 3c],
|
|
[D8 00 00 00],
|
|
[00 00 00 00 00 00 4D 00],
|
|
[4D 00 4D 00 4D 00 4D 05],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 4E 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 16 00 44 00 00 00 1F],
|
|
[00 00 00 00 00 00 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 32],
|
|
[BB 59 C8 C8],
|
|
[C8 C8 C8 C8 C8 C8 C8 4A],
|
|
[48 46 44 42 40 3E 3C 3A],
|
|
[00 FF FF FF FF FF FF FF],
|
|
[FF FF 04 00 02 02 00 04],
|
|
[69 5A 00 0B 76 0F FF 0F],
|
|
[FF 0F FF 14 81 F4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 E8 00 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 E4 00 0A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 84],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0a],
|
|
[E4 33 B4 00],
|
|
[00 00 4E 04 04 9A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E6 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1080-2340-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0d],
|
|
[B6 6A 00 06 23],
|
|
[8A 13 1A 05 04 FA 05 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 2c],
|
|
[C1 94 42 00],
|
|
[16 05 00 00 00 10 00 10],
|
|
[00 AA 8A 02 10 00 10 00],
|
|
[00 3F 3F 03 FF 03 FF 23],
|
|
[FF 03 FF 23 FF 03 FF 00],
|
|
[40 40 00 00 10 01 00 0C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 07],
|
|
[C2 09 24 0E 00 00 0E],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 13],
|
|
[C4 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[02 00 00 00 35 00 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 86],
|
|
[CF 64 0B 00],
|
|
[28 02 4B 02 DE 0B 77 0B],
|
|
[8B 04 04 04 04 04 04 04],
|
|
[04 04 05 05 05 00 3D 00],
|
|
[CD 00 CD 00 CD 00 CD 01],
|
|
[00 01 00 03 98 03 A9 03],
|
|
[A9 03 A9 03 A9 00 3D 00],
|
|
[CD 00 CD 00 CD 00 CD 01],
|
|
[00 01 00 03 98 03 A9 03],
|
|
[A9 03 A9 03 A9 01 42 01],
|
|
[42 01 42 01 42 01 42 01],
|
|
[42 01 42 01 42 01 42 01],
|
|
[42 01 42 01 42 1C 1C 1C],
|
|
[1C 1C 1C 1C 1C 1C 1C 1C],
|
|
[1C 00 88 00 B1 00 B1 09],
|
|
[A6 09 A6 09 A4 09 A4 09],
|
|
[A4 09 A4 09 A4 09 A4 0F],
|
|
[C3 19],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0a],
|
|
[D7 00 69 34],
|
|
[00 A0 0A 00 00 39],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 3c],
|
|
[D8 00 00 00],
|
|
[00 00 00 00 00 00 3A 00],
|
|
[3A 00 3A 00 3A 00 3A 05],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 20 40 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 0F 00 32 00 00 00 17],
|
|
[00 00 00 00 00 00 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 32],
|
|
[BB 59 C8 C8],
|
|
[C8 C8 C8 C8 C8 C8 C8 4A],
|
|
[48 46 44 42 40 3E 3C 3A],
|
|
[00 FF FF FF FF FF FF FF],
|
|
[FF FF 04 00 02 02 00 04],
|
|
[69 5A 00 0B 76 0F FF 0F],
|
|
[FF 0F FF 14 81 F4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 E8 00 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 E4 00 0A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 84],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0a],
|
|
[E4 33 B4 00 00 00 39 04],
|
|
[09 34],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E6 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|