1663 lines
58 KiB
Text
1663 lines
58 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/*
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* Device Tree defines for LCM settings
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include "mtk_lcm_settings.h"
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&pio {
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nt37801_wqhd_dphy_cmd_120hz: nt37801-wqhd-dphy-cmd-120hz {
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compatible = "mediatek,nt37801_wqhd_dphy_cmd_120hz";
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lcm-version = <0>;
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lcm-params{
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compatible = "mediatek,lcm-params";
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lcm-params-name = "nt37801-wqhd-dphy-cmd-120hz";
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lcm-params-types = <MTK_LCM_FUNC_DSI>;
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lcm-params-resolution = <1440 3200>;
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lcm-params-physical-width = <64>;
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lcm-params-physical-height = <129>;
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/* lk support */
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lcm-params-lk {
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compatible = "mediatek,lcm-params-lk";
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lcm-params-lk-ctrl;
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lcm-params-lk-lcm-if;
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lcm-params-lk-lcm-cmd-if;
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lcm-params-lk-io-select-mode;
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lcm-params-lk-lcm-x;
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lcm-params-lk-lcm-y;
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lcm-params-lk-virtual-resolution = <0 0>;
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lcm-params-lk-od-table-size;
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lcm-params-lk-od-table;
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};
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lcm-params-lk-round-corner {
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compatible = "mediatek,lcm-params-lk-round-corner";
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lcm-params-lk-rc-round-corner-en = <0>;
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lcm-params-lk-rc-is-notch;
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lcm-params-lk-rc-full-content = <0>;
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lcm-params-lk-rc-width;
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lcm-params-lk-rc-height;
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lcm-params-lk-rc-width-bot;
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lcm-params-lk-rc-height-bot;
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lcm-params-lk-rc-top-size;
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lcm-params-lk-rc-top-size-left;
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lcm-params-lk-rc-top-size-right;
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lcm-params-lk-rc-bottom-size;
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lcm-params-lk-rc-pattern-name;
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};
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lcm-params-dbi {
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compatible = "mediatek,lcm-params-dbi";
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/* future reserved for dbi interfaces */
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};
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lcm-params-dpi {
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compatible = "mediatek,lcm-params-dpi";
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/* future reserved for dpi interfaces */
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};
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lcm-params-dsi {
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compatible = "mediatek,lcm-params-dsi";
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lcm-params-dsi-density = <560>;
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lcm-params-dsi-lanes = <4>;
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lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
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lcm-params-dsi-phy-type = <MTK_LCM_MIPI_DPHY>;
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lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_LPM>,
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<MTK_MIPI_DSI_MODE_EOT_PACKET>,
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<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
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lcm-params-dsi-mode-flags-doze-on;
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lcm-params-dsi-mode-flags-doze-off;
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lcm-params-dsi-need-fake-resolution;
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lcm-params-dsi-fake-resolution = <1440 3200>;
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lcm-params-dsi-default-mode = <0>;
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lcm-params-dsi-mode-count = <6>;
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lcm-params-dsi-mode-list =
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<0 1440 3200 120>,
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<1 1440 3200 90>,
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<2 1440 3200 60>,
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<3 1440 3200 30>,
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<4 1440 3200 24>,
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<5 1440 3200 10>;
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/* backlight mode */
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lcm-params-dsi-backlight-mode {
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compatible = "mediatek,lcm-dsi-backlight-mode";
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lcm-bl-compatible = "mediatek,disp-leds";
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lcm-bl-max-brightness = <2047>;
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lcm-bl-min-brightness = <4>;
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lcm-bl-max-hw-brightness = <2047>;
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lcm-bl-led-mode = <4>;
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lcm-bl-gate-enable;
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lcm-bl-pwm-config;
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};
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lcm-params-dsi-fps-0-1440-3200-120 {
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compatible = "mediatek,lcm-dsi-fps-0-1440-3200-120";
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lcm-params-dsi-voltage;
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lcm-params-dsi-fake = <0>;
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/* drm-display-mode */
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lcm-params-dsi-vrefresh = <120>;
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lcm-params-dsi-vertical-sync-active = <2>;
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lcm-params-dsi-vertical-backporch = <16>;
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lcm-params-dsi-vertical-frontporch = <10>;
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lcm-params-dsi-vertical-active-line = <3200>;
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lcm-params-dsi-horizontal-sync-active = <20>;
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lcm-params-dsi-horizontal-backporch = <40>;
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lcm-params-dsi-horizontal-frontporch = <40>;
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lcm-params-dsi-horizontal-active-pixel = <1440>;
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lcm-params-dsi-pixel-clock = <596534>;
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lcm-params-dsi-hskew;
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lcm-params-dsi-vscan;
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/* mtk-panel-params */
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lcm-params-dsi-pll-clock = <750>;
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lcm-params-dsi-data-rate = <1500>;
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lcm-params-dsi-vfp-for-low-power;
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lcm-params-dsi-ssc-enable;
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lcm-params-dsi-ssc-range;
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lcm-params-dsi-lcm-color-mode;
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lcm-params-dsi-min-luminance;
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lcm-params-dsi-average-luminance;
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lcm-params-dsi-max-luminance;
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lcm-params-dsi-round-corner-en = <0>;
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lcm-params-dsi-corner-pattern-height;
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lcm-params-dsi-corner-pattern-height-bot;
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lcm-params-dsi-corner-pattern-tp-size;
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lcm-params-dsi-corner-pattern-tp-size-left;
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lcm-params-dsi-corner-pattern-tp-size-right;
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lcm-params-dsi-corner-pattern-name;
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lcm-params-dsi-physical-width-um;
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lcm-params-dsi-physical-height-um;
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lcm-params-dsi-output-mode =
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<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
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lcm-params-dsi-lcm-cmd-if;
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lcm-params-dsi-hbm-en-time;
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lcm-params-dsi-hbm-dis-time;
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lcm-params-dsi-lcm-index;
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lcm-params-dsi-wait-sof-before-dec-vfp;
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lcm-params-dsi-doze-delay;
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lcm-params-dsi-lp-perline-en = <1>;
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lcm-params-dsi-lfr-enable;
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lcm-params-dsi-lfr-minimum-fps;
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lcm-params-dsi-msync2-enable;
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lcm-params-dsi-max-vfp-for-msync;
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/* lane swap */
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lcm-params-dsi-lane-swap-en;
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lcm-params-dsi-lane-swap0;
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lcm-params-dsi-lane-swap1;
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/* esd check table */
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lcm-params-dsi-cust-esd-check = <0>;
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lcm-params-dsi-esd-check-enable = <1>;
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lcm-params-dsi-lcm-esd-check-table0 = [0a 01 1c];
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lcm-params-dsi-lcm-esd-check-table1;
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lcm-params-dsi-lcm-esd-check-table2;
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/* Msync 3.0 */
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lcm-params-dsi-skip-vblank = <0>;
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lcm-params-dsi-lcm-is-support-od = <1>;
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lcm-params-dsi-lcm-is-support-dmr;
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/* fpga support */
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lcm-params-dsi-fpga-params-0-1440-3200-120 {
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compatible = "mediatek,lcm-dsi-fpga-params";
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lcm-params-dsi-lk-pll-div = <0 0>;
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lcm-params-dsi-lk-fbk-div = <1>;
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};
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/* lk support */
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lcm-params-dsi-lk-params-0-1440-3200-120 {
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compatible = "mediatek,lcm-dsi-lk-params";
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lcm-params-dsi-lk-mode = <MTK_LK_CMD_MODE>;
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lcm-params-dsi-lk-switch-mode =
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<MTK_LK_SYNC_PULSE_VDO_MODE>;
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lcm-params-dsi-lk-switch-mode-enable = <0>;
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lcm-params-dsi-lk-dsi-wmem-conti;
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lcm-params-dsi-lk-dsi-rmem-conti;
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lcm-params-dsi-lk-vc-num;
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lcm-params-dsi-lk-data-format =
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<MTK_LCM_COLOR_ORDER_RGB>,
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<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
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<MTK_LCM_DSI_PADDING_ON_LSB>,
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<MTK_LCM_DSI_FORMAT_RGB888>;
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lcm-params-dsi-lk-intermediat-buffer-num;
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lcm-params-dsi-lk-ps =
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<MTK_LCM_PACKED_PS_24BIT_RGB888>;
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lcm-params-dsi-lk-word-count;
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lcm-params-dsi-lk-packet-size = <256>;
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lcm-params-dsi-lk-horizontal-blanking-pixel;
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lcm-params-dsi-lk-bllp;
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lcm-params-dsi-lk-line-byte;
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lcm-params-dsi-lk-horizontal-sync-active-byte;
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lcm-params-dsi-lk-horizontal-backporch-byte;
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lcm-params-dsi-lk-horizontal-frontporch-byte;
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lcm-params-dsi-lk-rgb-byte;
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lcm-params-dsi-lk-horizontal-sync-active-word-count;
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lcm-params-dsi-lk-horizontal-backporch-word-count;
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lcm-params-dsi-lk-horizontal-frontporch-word-count;
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lcm-params-dsi-lk-pll-select;
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lcm-params-dsi-lk-pll-div;
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lcm-params-dsi-lk-fbk-div;
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lcm-params-dsi-lk-fbk-sel;
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lcm-params-dsi-lk-rg = <0 0 0>;
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lcm-params-dsi-lk-dsi-clock;
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lcm-params-dsi-lk-ssc-disable = <1>;
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lcm-params-dsi-lk-ssc-range;
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lcm-params-dsi-lk-compatibility-for-nvk;
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lcm-params-dsi-lk-cont-clock;
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lcm-params-dsi-lk-ufoe-enable;
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lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
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lcm-params-dsi-lk-edp-panel;
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lcm-params-dsi-lk-lcm-int-te-monitor;
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lcm-params-dsi-lk-lcm-int-te-period;
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lcm-params-dsi-lk-lcm-ext-te-monitor;
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lcm-params-dsi-lk-lcm-ext-te-period;
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lcm-params-dsi-lk-noncont-clock;
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lcm-params-dsi-lk-noncont-clock-period;
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lcm-params-dsi-lk-lp-perline-en = <1>;
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lcm-params-dsi-lk-clk-lp-per-line-enable = <0>;
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lcm-params-dsi-lk-dual-dsi-type;
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lcm-params-dsi-lk-mixmode-enable;
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lcm-params-dsi-lk-mixmode-mipi-clock;
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lcm-params-dsi-lk-pwm-fps;
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lcm-params-dsi-lk-pll-clock-lp;
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lcm-params-dsi-lk-ulps-sw-enable;
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lcm-params-dsi-lk-null-packet-en;
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lcm-params-dsi-lk-vact-fps;
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lcm-params-dsi-lk-send-frame-enable;
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lcm-params-dsi-lk-lfr-enable;
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lcm-params-dsi-lk-lfr-mode;
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lcm-params-dsi-lk-lfr-type;
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lcm-params-dsi-lk-lfr-skip-num;
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lcm-params-dsi-lk-ext-te-edge;
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lcm-params-dsi-lk-eint-disable;
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lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
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};
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lcm-params-dsi-dsc-params-0-1440-3200-120 {
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compatible =
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"mediatek,lcm-params-dsi-dsc-params";
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lcm-params-dsi-dsc-enable = <1>;
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lcm-params-dsi-dsc-enable-lk = <1>;
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lcm-params-dsi-dsc-ver = <18>;
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lcm-params-dsi-dsc-slice-mode = <1>;
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lcm-params-dsi-dsc-rgb-swap = <0>;
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lcm-params-dsi-dsc-cfg = <40>;
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lcm-params-dsi-dsc-rct-on = <1>;
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lcm-params-dsi-dsc-bit-per-channel = <10>;
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lcm-params-dsi-dsc-line-buf-depth = <11>;
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lcm-params-dsi-dsc-bp-enable = <1>;
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lcm-params-dsi-dsc-bit-per-pixel = <128>;
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lcm-params-dsi-dsc-pic-height = <3200>;
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lcm-params-dsi-dsc-pic-width = <1440>;
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lcm-params-dsi-dsc-slice-height = <40>;
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lcm-params-dsi-dsc-slice-width = <720>;
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lcm-params-dsi-dsc-chunk-size = <720>;
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lcm-params-dsi-dsc-xmit-delay = <512>;
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lcm-params-dsi-dsc-dec-delay = <646>;
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lcm-params-dsi-dsc-scale-value = <32>;
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lcm-params-dsi-dsc-increment-interval = <1082>;
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lcm-params-dsi-dsc-decrement-interval = <10>;
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lcm-params-dsi-dsc-line-bpg-offset = <13>;
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lcm-params-dsi-dsc-nfl-bpg-offset = <683>;
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lcm-params-dsi-dsc-slice-bpg-offset = <489>;
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lcm-params-dsi-dsc-initial-offset = <6144>;
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lcm-params-dsi-dsc-final-offset = <4336>;
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lcm-params-dsi-dsc-flatness-minqp = <7>;
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lcm-params-dsi-dsc-flatness-maxqp = <16>;
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lcm-params-dsi-dsc-rc-model-size = <8192>;
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lcm-params-dsi-dsc-rc-edge-factor = <6>;
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lcm-params-dsi-dsc-rc-quant-incr-limit0 = <15>;
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lcm-params-dsi-dsc-rc-quant-incr-limit1 = <15>;
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lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
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lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
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lcm-params-dsi-dsc-ext-pps-cfg {
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compatible =
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"mediatek,lcm-params-dsi-dsc-ext-pps-cfg";
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pps-enable = <1>;
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pps-rc-buf-thresh =
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<896 1792 2688 3584 4480>,
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<5376 6272 6720 7168 7616>,
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<7744 7872 8000 8064>;
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pps-range-min-qp =
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<0 4 5 5 7>,
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<7 7 7 7 8>,
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<9 9 9 12 16>;
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pps-range-max-qp =
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<8 8 9 10 11>,
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<11 11 12 13 14>,
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<14 15 15 16 17>;
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pps-range-bpg-ofs =
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<0x00000002 0x00000000 0x00000000>,
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<0xfffffffe 0xfffffffc 0xfffffffa>,
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<0xfffffff8 0xfffffff8 0xfffffff8>,
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<0xfffffff6 0xfffffff6 0xfffffff6>,
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<0xfffffff4 0xfffffff4 0xfffffff4>;
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};
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};
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lcm-params-dsi-phy-timcon-params-0-1440-3200-120 {
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compatible =
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"mediatek,lcm-params-dsi-phy-timcon";
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lcm-params-dsi-phy-timcon-hs-trail;
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lcm-params-dsi-phy-timcon-hs-prpr;
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lcm-params-dsi-phy-timcon-hs-zero;
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lcm-params-dsi-phy-timcon-lpx;
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lcm-params-dsi-phy-timcon-ta-get;
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lcm-params-dsi-phy-timcon-ta-sure;
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lcm-params-dsi-phy-timcon-ta-go;
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lcm-params-dsi-phy-timcon-da-hs-exit;
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lcm-params-dsi-phy-timcon-clk-trail;
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lcm-params-dsi-phy-timcon-cont-det;
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lcm-params-dsi-phy-timcon-da-hs-sync;
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lcm-params-dsi-phy-timcon-clk-zero;
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lcm-params-dsi-phy-timcon-clk-prpr;
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lcm-params-dsi-phy-timcon-clk-exit;
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lcm-params-dsi-phy-timcon-clk-post;
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/* lk support */
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lcm-params-dsi-phy-timcon-lk-hs-trail;
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lcm-params-dsi-phy-timcon-lk-hs-zero;
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lcm-params-dsi-phy-timcon-lk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-lpx;
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lcm-params-dsi-phy-timcon-lk-ta-sack;
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lcm-params-dsi-phy-timcon-lk-ta-get;
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lcm-params-dsi-phy-timcon-lk-ta-sure;
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lcm-params-dsi-phy-timcon-lk-ta-go;
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lcm-params-dsi-phy-timcon-lk-clk-trail;
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lcm-params-dsi-phy-timcon-lk-clk-zero;
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lcm-params-dsi-phy-timcon-lk-lpx-wait;
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lcm-params-dsi-phy-timcon-lk-cont-det;
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lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-clk-hs-post;
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lcm-params-dsi-phy-timcon-lk-da-hs-exit;
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lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
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};
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lcm-params-dsi-dyn-params-0-1440-3200-120 {
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compatible =
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"mediatek,lcm-params-dsi-dyn";
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lcm-params-dsi-dyn-switch-en = <1>;
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lcm-params-dsi-dyn-pll-clk = <751>;
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lcm-params-dsi-dyn-data-rate;
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lcm-params-dsi-dyn-vsa;
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lcm-params-dsi-dyn-vbp;
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lcm-params-dsi-dyn-vfp;
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lcm-params-dsi-dyn-vfp-lp-dyn;
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lcm-params-dsi-dyn-vac;
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lcm-params-dsi-dyn-hsa;
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lcm-params-dsi-dyn-hbp;
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lcm-params-dsi-dyn-hfp;
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lcm-params-dsi-dyn-hac;
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lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
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};
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lcm-params-dsi-dyn-fps-params-0-1440-3200-120 {
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compatible =
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"mediatek,lcm-params-dsi-dyn-fps";
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lcm-params-dsi-dyn-fps-switch-en;
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lcm-params-dsi-dyn-fps-vact-timing-fps;
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lcm-params-dsi-dyn-fps-data-rate;
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lcm-params-dsi-dyn-fps-dfps-cmd-table0;
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lcm-params-dsi-dyn-fps-dfps-cmd-table1;
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lcm-params-dsi-dyn-fps-dfps-cmd-table2;
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lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-1-1440-3200-90 {
|
|
compatible = "mediatek,lcm-dsi-fps-1-1440-3200-90";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <90>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <16>;
|
|
lcm-params-dsi-vertical-frontporch = <10>;
|
|
lcm-params-dsi-vertical-active-line = <3200>;
|
|
lcm-params-dsi-horizontal-sync-active = <20>;
|
|
lcm-params-dsi-horizontal-backporch = <40>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1440>;
|
|
lcm-params-dsi-pixel-clock = <447401>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <750>;
|
|
lcm-params-dsi-data-rate = <1500>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lp-perline-en = <1>;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 1c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <0>;
|
|
|
|
lcm-params-dsi-lcm-is-support-od = <1>;
|
|
lcm-params-dsi-lcm-is-support-dmr;
|
|
|
|
lcm-params-dsi-dsc-params-1-1440-3200-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-ver = <18>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <40>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <10>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <3200>;
|
|
lcm-params-dsi-dsc-pic-width = <1440>;
|
|
lcm-params-dsi-dsc-slice-height = <40>;
|
|
lcm-params-dsi-dsc-slice-width = <720>;
|
|
lcm-params-dsi-dsc-chunk-size = <720>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <646>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <1082>;
|
|
lcm-params-dsi-dsc-decrement-interval = <10>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <13>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <683>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <489>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <7>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <16>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <15>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <15>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
|
|
lcm-params-dsi-dsc-ext-pps-cfg {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-ext-pps-cfg";
|
|
|
|
pps-enable = <1>;
|
|
pps-rc-buf-thresh =
|
|
<896 1792 2688 3584 4480>,
|
|
<5376 6272 6720 7168 7616>,
|
|
<7744 7872 8000 8064>;
|
|
pps-range-min-qp =
|
|
<0 4 5 5 7>,
|
|
<7 7 7 7 8>,
|
|
<9 9 9 12 16>;
|
|
pps-range-max-qp =
|
|
<8 8 9 10 11>,
|
|
<11 11 12 13 14>,
|
|
<14 15 15 16 17>;
|
|
pps-range-bpg-ofs =
|
|
<0x00000002 0x00000000 0x00000000>,
|
|
<0xfffffffe 0xfffffffc 0xfffffffa>,
|
|
<0xfffffff8 0xfffffff8 0xfffffff8>,
|
|
<0xfffffff6 0xfffffff6 0xfffffff6>,
|
|
<0xfffffff4 0xfffffff4 0xfffffff4>;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-1-1440-3200-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-1-1440-3200-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <751>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-1-1440-3200-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-2-1440-3200-60 {
|
|
compatible = "mediatek,lcm-dsi-fps-2-1440-3200-60";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <60>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <16>;
|
|
lcm-params-dsi-vertical-frontporch = <10>;
|
|
lcm-params-dsi-vertical-active-line = <3200>;
|
|
lcm-params-dsi-horizontal-sync-active = <20>;
|
|
lcm-params-dsi-horizontal-backporch = <40>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1440>;
|
|
lcm-params-dsi-pixel-clock = <298267>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <750>;
|
|
lcm-params-dsi-data-rate = <1500>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lp-perline-en = <1>;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 1c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <0>;
|
|
|
|
lcm-params-dsi-lcm-is-support-od = <1>;
|
|
lcm-params-dsi-lcm-is-support-dmr;
|
|
|
|
lcm-params-dsi-dsc-params-2-1440-3200-60 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-ver = <18>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <40>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <10>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <3200>;
|
|
lcm-params-dsi-dsc-pic-width = <1440>;
|
|
lcm-params-dsi-dsc-slice-height = <40>;
|
|
lcm-params-dsi-dsc-slice-width = <720>;
|
|
lcm-params-dsi-dsc-chunk-size = <720>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <646>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <1082>;
|
|
lcm-params-dsi-dsc-decrement-interval = <10>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <13>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <683>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <489>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <7>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <16>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <15>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <15>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
|
|
lcm-params-dsi-dsc-ext-pps-cfg {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-ext-pps-cfg";
|
|
|
|
pps-enable = <1>;
|
|
pps-rc-buf-thresh =
|
|
<896 1792 2688 3584 4480>,
|
|
<5376 6272 6720 7168 7616>,
|
|
<7744 7872 8000 8064>;
|
|
pps-range-min-qp =
|
|
<0 4 5 5 7>,
|
|
<7 7 7 7 8>,
|
|
<9 9 9 12 16>;
|
|
pps-range-max-qp =
|
|
<8 8 9 10 11>,
|
|
<11 11 12 13 14>,
|
|
<14 15 15 16 17>;
|
|
pps-range-bpg-ofs =
|
|
<0x00000002 0x00000000 0x00000000>,
|
|
<0xfffffffe 0xfffffffc 0xfffffffa>,
|
|
<0xfffffff8 0xfffffff8 0xfffffff8>,
|
|
<0xfffffff6 0xfffffff6 0xfffffff6>,
|
|
<0xfffffff4 0xfffffff4 0xfffffff4>;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-2-1440-3200-60 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-2-1440-3200-60 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <751>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-2-1440-3200-60 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-3-1440-3200-30 {
|
|
compatible = "mediatek,lcm-dsi-fps-3-1440-3200-30";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <30>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <16>;
|
|
lcm-params-dsi-vertical-frontporch = <10>;
|
|
lcm-params-dsi-vertical-active-line = <3200>;
|
|
lcm-params-dsi-horizontal-sync-active = <20>;
|
|
lcm-params-dsi-horizontal-backporch = <40>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1440>;
|
|
lcm-params-dsi-pixel-clock = <596534>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <750>;
|
|
lcm-params-dsi-data-rate = <1500>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lp-perline-en = <1>;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 1c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <4>;
|
|
|
|
lcm-params-dsi-lcm-is-support-od = <1>;
|
|
lcm-params-dsi-lcm-is-support-dmr;
|
|
|
|
lcm-params-dsi-dsc-params-3-1440-3200-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-ver = <18>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <40>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <10>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <3200>;
|
|
lcm-params-dsi-dsc-pic-width = <1440>;
|
|
lcm-params-dsi-dsc-slice-height = <40>;
|
|
lcm-params-dsi-dsc-slice-width = <720>;
|
|
lcm-params-dsi-dsc-chunk-size = <720>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <646>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <1082>;
|
|
lcm-params-dsi-dsc-decrement-interval = <10>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <13>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <683>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <489>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <7>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <16>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <15>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <15>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
|
|
lcm-params-dsi-dsc-ext-pps-cfg {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-ext-pps-cfg";
|
|
|
|
pps-enable = <1>;
|
|
pps-rc-buf-thresh =
|
|
<896 1792 2688 3584 4480>,
|
|
<5376 6272 6720 7168 7616>,
|
|
<7744 7872 8000 8064>;
|
|
pps-range-min-qp =
|
|
<0 4 5 5 7>,
|
|
<7 7 7 7 8>,
|
|
<9 9 9 12 16>;
|
|
pps-range-max-qp =
|
|
<8 8 9 10 11>,
|
|
<11 11 12 13 14>,
|
|
<14 15 15 16 17>;
|
|
pps-range-bpg-ofs =
|
|
<0x00000002 0x00000000 0x00000000>,
|
|
<0xfffffffe 0xfffffffc 0xfffffffa>,
|
|
<0xfffffff8 0xfffffff8 0xfffffff8>,
|
|
<0xfffffff6 0xfffffff6 0xfffffff6>,
|
|
<0xfffffff4 0xfffffff4 0xfffffff4>;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-3-1440-3200-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-3-1440-3200-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <751>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-3-1440-3200-30 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-4-1440-3200-24 {
|
|
compatible = "mediatek,lcm-dsi-fps-4-1440-3200-24";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <24>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <16>;
|
|
lcm-params-dsi-vertical-frontporch = <10>;
|
|
lcm-params-dsi-vertical-active-line = <3200>;
|
|
lcm-params-dsi-horizontal-sync-active = <20>;
|
|
lcm-params-dsi-horizontal-backporch = <40>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1440>;
|
|
lcm-params-dsi-pixel-clock = <596534>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <750>;
|
|
lcm-params-dsi-data-rate = <1500>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lp-perline-en = <1>;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 1c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <5>;
|
|
|
|
lcm-params-dsi-lcm-is-support-od = <1>;
|
|
lcm-params-dsi-lcm-is-support-dmr;
|
|
|
|
lcm-params-dsi-dsc-params-4-1440-3200-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-ver = <18>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <40>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <10>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <3200>;
|
|
lcm-params-dsi-dsc-pic-width = <1440>;
|
|
lcm-params-dsi-dsc-slice-height = <40>;
|
|
lcm-params-dsi-dsc-slice-width = <720>;
|
|
lcm-params-dsi-dsc-chunk-size = <720>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <646>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <1082>;
|
|
lcm-params-dsi-dsc-decrement-interval = <10>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <13>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <683>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <489>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <7>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <16>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <15>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <15>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
|
|
lcm-params-dsi-dsc-ext-pps-cfg {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-ext-pps-cfg";
|
|
|
|
pps-enable = <1>;
|
|
pps-rc-buf-thresh =
|
|
<896 1792 2688 3584 4480>,
|
|
<5376 6272 6720 7168 7616>,
|
|
<7744 7872 8000 8064>;
|
|
pps-range-min-qp =
|
|
<0 4 5 5 7>,
|
|
<7 7 7 7 8>,
|
|
<9 9 9 12 16>;
|
|
pps-range-max-qp =
|
|
<8 8 9 10 11>,
|
|
<11 11 12 13 14>,
|
|
<14 15 15 16 17>;
|
|
pps-range-bpg-ofs =
|
|
<0x00000002 0x00000000 0x00000000>,
|
|
<0xfffffffe 0xfffffffc 0xfffffffa>,
|
|
<0xfffffff8 0xfffffff8 0xfffffff8>,
|
|
<0xfffffff6 0xfffffff6 0xfffffff6>,
|
|
<0xfffffff4 0xfffffff4 0xfffffff4>;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-4-1440-3200-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-4-1440-3200-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <751>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-4-1440-3200-24 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-5-1440-3200-10 {
|
|
compatible = "mediatek,lcm-dsi-fps-5-1440-3200-10";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <10>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <16>;
|
|
lcm-params-dsi-vertical-frontporch = <10>;
|
|
lcm-params-dsi-vertical-active-line = <3200>;
|
|
lcm-params-dsi-horizontal-sync-active = <20>;
|
|
lcm-params-dsi-horizontal-backporch = <40>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1440>;
|
|
lcm-params-dsi-pixel-clock = <596534>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <750>;
|
|
lcm-params-dsi-data-rate = <1500>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lp-perline-en = <1>;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 1c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* Msync 3.0 */
|
|
lcm-params-dsi-skip-vblank = <12>;
|
|
|
|
lcm-params-dsi-lcm-is-support-od = <1>;
|
|
lcm-params-dsi-lcm-is-support-dmr;
|
|
|
|
lcm-params-dsi-dsc-params-5-1440-3200-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-ver = <18>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <40>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <10>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <3200>;
|
|
lcm-params-dsi-dsc-pic-width = <1440>;
|
|
lcm-params-dsi-dsc-slice-height = <40>;
|
|
lcm-params-dsi-dsc-slice-width = <720>;
|
|
lcm-params-dsi-dsc-chunk-size = <720>;
|
|
lcm-params-dsi-dsc-xmit-delay = <512>;
|
|
lcm-params-dsi-dsc-dec-delay = <646>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <1082>;
|
|
lcm-params-dsi-dsc-decrement-interval = <10>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <13>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <683>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <489>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <4336>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <7>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <16>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <15>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <15>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
|
|
lcm-params-dsi-dsc-ext-pps-cfg {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-ext-pps-cfg";
|
|
|
|
pps-enable = <1>;
|
|
pps-rc-buf-thresh =
|
|
<896 1792 2688 3584 4480>,
|
|
<5376 6272 6720 7168 7616>,
|
|
<7744 7872 8000 8064>;
|
|
pps-range-min-qp =
|
|
<0 4 5 5 7>,
|
|
<7 7 7 7 8>,
|
|
<9 9 9 12 16>;
|
|
pps-range-max-qp =
|
|
<8 8 9 10 11>,
|
|
<11 11 12 13 14>,
|
|
<14 15 15 16 17>;
|
|
pps-range-bpg-ofs =
|
|
<0x00000002 0x00000000 0x00000000>,
|
|
<0xfffffffe 0xfffffffc 0xfffffffa>,
|
|
<0xfffffff8 0xfffffff8 0xfffffff8>,
|
|
<0xfffffff6 0xfffffff6 0xfffffff6>,
|
|
<0xfffffff4 0xfffffff4 0xfffffff4>;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-5-1440-3200-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-5-1440-3200-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <1>;
|
|
lcm-params-dsi-dyn-pll-clk = <751>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-5-1440-3200-10 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
|
|
lcm-ops {
|
|
compatible = "mediatek,lcm-ops";
|
|
lcm-ops-dbi {
|
|
compatible = "mediatek,lcm-ops-dbi";
|
|
/* future reserved for dbi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dpi {
|
|
compatible = "mediatek,lcm-ops-dpi";
|
|
/* future reserved for dpi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dsi {
|
|
compatible = "mediatek,lcm-ops-dsi";
|
|
prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06 F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04 C5 0B 0B 0B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 FF AA 55 A5 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F4 55],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 90 03 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 13],
|
|
[91 AB A8 00 28 D2],
|
|
[00 02 86 04 3A 00],
|
|
[0A 02 AB 01 E9 10 F0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 2A 00 00 05 9F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 2B 00 00 0C 7F],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05 3B 00 18 00 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 07 51 07 FF 07 FF 0F FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9C 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5F 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 26 00],
|
|
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 07 FF],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 11],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02],
|
|
[MTK_LCM_PHASE_HEX_KERNEL MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 8C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02],
|
|
[MTK_LCM_PHASE_HEX_KERNEL MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
unprepare-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 28],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 32],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 10],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 96],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-display-on-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 64],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
lcm-update-table;
|
|
|
|
set-backlight-mask = <0x7ff>;
|
|
set-backlight-cmdq-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 07 FF],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-elvss-cmdq-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
|
|
[MTK_LCM_INPUT_TYPE_HEX_MISC 01 01],
|
|
[02 83 ff],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-backlight-elvss-cmdq-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 07 FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
|
|
[MTK_LCM_INPUT_TYPE_HEX_MISC 01 01],
|
|
[02 83 ff],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-aod-light-mask = <0x7ff>;
|
|
set-aod-light-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 07 FF],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
ata-id-value-data = [01 25 00];
|
|
ata-check-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_CMD 03 00 03 04],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
compare-id-value-data = [78 01];
|
|
compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 02 bc],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-enable-start-table;
|
|
|
|
doze-enable-table;
|
|
|
|
doze-disable-table;
|
|
|
|
doze-area-table;
|
|
|
|
doze-post-disp-on-table;
|
|
|
|
hbm-set-cmdq-switch-id;
|
|
hbm-set-cmdq-switch-on;
|
|
hbm-set-cmdq-switch-off;
|
|
hbm-set-cmdq-table;
|
|
|
|
read-panelid-len = <0>;
|
|
read-panelid-table;
|
|
|
|
/* fps switch cmd for high frame rate feature */
|
|
lcm-ops-dsi-fps-switch-after-poweron {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
|
|
|
|
fps-switch-0-1440-3200-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-1-1440-3200-90-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 07],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03],
|
|
[BA 00 4f],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1440-3200-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 01 01 00 01 01 01 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-3-1440-3200-30-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 03 03 00 01 03 03 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-4-1440-3200-24-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 04 04 00 01 04 04 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-5-1440-3200-10-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 0B 0B 00 01 0B 0B 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
|
|
lcm-ops-dsi-fps-switch-before-powerdown {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
|
|
|
|
fps-switch-0-1440-3200-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-1-1440-3200-90-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 07],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03],
|
|
[BA 00 4f],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1440-3200-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 01 01 00 01 01 01 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-3-1440-3200-30-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 03 03 00 01 03 03 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-4-1440-3200-24-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 04 04 00 01 04 04 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-5-1440-3200-10-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 09],
|
|
[BA 91 0B 0B 00 01 0B 0B 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 30],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|