969 lines
35 KiB
Text
969 lines
35 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/*
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* Device Tree defines for LCM settings
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include "mtk_lcm_settings.h"
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#include "spr/mt6985_nt37701_dphy_cmd_120hz_spr.dtsi"
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&pio {
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nt37701_fhdp_dphy_cmd_hx_120hz: nt37701-fhdp-dphy-cmd-hx-120hz {
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compatible = "mediatek,nt37701_fhdp_dphy_cmd_hx_120hz";
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lcm-version = <0>;
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lcm-params{
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compatible = "mediatek,lcm-params";
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lcm-params-name = "nt37701-fhdp-dphy-cmd-hx-120hz";
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lcm-params-types = <MTK_LCM_FUNC_DSI>;
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lcm-params-resolution = <1080 2400>;
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lcm-params-physical-width;
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lcm-params-physical-height;
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/* lk support */
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lcm-params-lk {
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compatible = "mediatek,lcm-params-lk";
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lcm-params-lk-ctrl;
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lcm-params-lk-lcm-if;
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lcm-params-lk-lcm-cmd-if;
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lcm-params-lk-io-select-mode;
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lcm-params-lk-lcm-x;
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lcm-params-lk-lcm-y;
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lcm-params-lk-virtual-resolution = <0 0>;
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lcm-params-lk-od-table-size;
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lcm-params-lk-od-table;
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};
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lcm-params-lk-round-corner {
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compatible = "mediatek,lcm-params-lk-round-corner";
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lcm-params-lk-rc-round-corner-en = <0>;
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lcm-params-lk-rc-is-notch;
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lcm-params-lk-rc-full-content = <0>;
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lcm-params-lk-rc-width;
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lcm-params-lk-rc-height;
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lcm-params-lk-rc-width-bot;
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lcm-params-lk-rc-height-bot;
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lcm-params-lk-rc-top-size;
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lcm-params-lk-rc-top-size-left;
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lcm-params-lk-rc-top-size-right;
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lcm-params-lk-rc-bottom-size;
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lcm-params-lk-rc-pattern-name;
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};
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lcm-params-dbi {
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compatible = "mediatek,lcm-params-dbi";
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/* future reserved for dbi interfaces */
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};
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lcm-params-dpi {
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compatible = "mediatek,lcm-params-dpi";
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/* future reserved for dpi interfaces */
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};
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lcm-params-dsi {
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compatible = "mediatek,lcm-params-dsi";
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lcm-params-dsi-density = <480>;
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lcm-params-dsi-lanes = <4>;
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lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
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lcm-params-dsi-phy-type = <MTK_LCM_MIPI_DPHY>;
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lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_LPM>,
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<MTK_MIPI_DSI_MODE_EOT_PACKET>,
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<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
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lcm-params-dsi-mode-flags-doze-on;
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lcm-params-dsi-mode-flags-doze-off;
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lcm-params-dsi-need-fake-resolution;
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lcm-params-dsi-fake-resolution = <1080 2400>;
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lcm-gpio-list = <&pio 42 0>, /* gpio list*/
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<&pio 28 0>,
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<&pio 29 0>;
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pinctrl-names = "gpio1", "gpio2", "gpio3";
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pinctrl-0;
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pinctrl-1;
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pinctrl-2;
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status = "okay";
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lcm-params-dsi-default-mode = <0>;
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lcm-params-dsi-mode-count = <2>;
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lcm-params-dsi-mode-list =
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<0 1080 2400 60>,
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<1 1080 2400 120>;
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lcm-params-dsi-fps-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-fps-0-1080-2400-60";
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lcm-params-dsi-voltage;
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lcm-params-dsi-fake = <0>;
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/* drm-display-mode */
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lcm-params-dsi-vrefresh = <60>;
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lcm-params-dsi-vertical-sync-active = <2>;
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lcm-params-dsi-vertical-backporch = <8>;
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lcm-params-dsi-vertical-frontporch = <20>;
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lcm-params-dsi-lk-vertical-frontporch = <50>;
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lcm-params-dsi-vertical-active-line = <2400>;
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lcm-params-dsi-horizontal-sync-active = <10>;
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lcm-params-dsi-horizontal-backporch = <20>;
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lcm-params-dsi-horizontal-frontporch = <40>;
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lcm-params-dsi-horizontal-active-pixel = <1080>;
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lcm-params-dsi-pixel-clock = <167670>;
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lcm-params-dsi-hskew;
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lcm-params-dsi-vscan;
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/* mtk-panel-params */
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lcm-params-dsi-lk-pll-clock = <330>;
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lcm-params-dsi-lk-data-rate = <660>;
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lcm-params-dsi-pll-clock = <410>;
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lcm-params-dsi-data-rate = <820>;
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lcm-params-dsi-vfp-for-low-power;
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lcm-params-dsi-ssc-enable;
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lcm-params-dsi-ssc-range;
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lcm-params-dsi-lcm-color-mode;
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lcm-params-dsi-min-luminance;
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lcm-params-dsi-average-luminance;
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lcm-params-dsi-max-luminance;
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lcm-params-dsi-round-corner-en = <0>;
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lcm-params-dsi-corner-pattern-height;
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lcm-params-dsi-corner-pattern-height-bot;
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lcm-params-dsi-corner-pattern-tp-size;
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lcm-params-dsi-corner-pattern-tp-size-left;
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lcm-params-dsi-corner-pattern-tp-size-right;
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lcm-params-dsi-corner-pattern-name;
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lcm-params-dsi-physical-width-um;
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lcm-params-dsi-physical-height-um;
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lcm-params-dsi-output-mode =
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<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
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lcm-params-dsi-lcm-cmd-if;
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lcm-params-dsi-hbm-en-time;
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lcm-params-dsi-hbm-dis-time;
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lcm-params-dsi-lcm-index;
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lcm-params-dsi-wait-sof-before-dec-vfp;
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lcm-params-dsi-doze-delay;
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lcm-params-dsi-lp-perline-en = <1>;
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lcm-params-dsi-lfr-enable;
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lcm-params-dsi-lfr-minimum-fps;
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lcm-params-dsi-msync2-enable;
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lcm-params-dsi-max-vfp-for-msync;
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/* lane swap */
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lcm-params-dsi-lane-swap-en;
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lcm-params-dsi-lane-swap0;
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lcm-params-dsi-lane-swap1;
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lcm-params-dsi-lcm-is-support-od = <1>;
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lcm-params-dsi-lcm-is-support-dmr = <1>;
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/* esd check table */
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lcm-params-dsi-cust-esd-check = <0>;
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lcm-params-dsi-esd-check-enable = <1>;
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lcm-params-dsi-lcm-esd-check-table0 = [0a 01 9c];
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lcm-params-dsi-lcm-esd-check-table1;
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lcm-params-dsi-lcm-esd-check-table2;
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/* fpga support */
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lcm-params-dsi-fpga-params-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-fpga-params";
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lcm-params-dsi-lk-pll-div = <0 0>;
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lcm-params-dsi-lk-fbk-div = <1>;
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};
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/* lk support */
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lcm-params-dsi-lk-params-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-lk-params";
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lcm-params-dsi-lk-mode = <MTK_LK_CMD_MODE>;
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lcm-params-dsi-lk-switch-mode =
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<MTK_LK_SYNC_PULSE_VDO_MODE>;
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lcm-params-dsi-lk-switch-mode-enable = <0>;
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lcm-params-dsi-lk-dsi-wmem-conti;
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lcm-params-dsi-lk-dsi-rmem-conti;
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lcm-params-dsi-lk-vc-num;
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lcm-params-dsi-lk-data-format =
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<MTK_LCM_COLOR_ORDER_RGB>,
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<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
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<MTK_LCM_DSI_PADDING_ON_LSB>,
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<MTK_LCM_DSI_FORMAT_RGB888>;
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lcm-params-dsi-lk-intermediat-buffer-num;
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lcm-params-dsi-lk-ps =
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<MTK_LCM_PACKED_PS_8BIT_SPR>;
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lcm-params-dsi-lk-word-count;
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lcm-params-dsi-lk-packet-size = <256>;
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lcm-params-dsi-lk-horizontal-blanking-pixel;
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lcm-params-dsi-lk-bllp;
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lcm-params-dsi-lk-line-byte;
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lcm-params-dsi-lk-horizontal-sync-active-byte;
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lcm-params-dsi-lk-horizontal-backporch-byte;
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lcm-params-dsi-lk-horizontal-frontporch-byte;
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lcm-params-dsi-lk-rgb-byte;
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lcm-params-dsi-lk-horizontal-sync-active-word-count;
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lcm-params-dsi-lk-horizontal-backporch-word-count;
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lcm-params-dsi-lk-horizontal-frontporch-word-count;
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lcm-params-dsi-lk-pll-select;
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lcm-params-dsi-lk-pll-div;
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lcm-params-dsi-lk-fbk-div;
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lcm-params-dsi-lk-fbk-sel;
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lcm-params-dsi-lk-rg = <0 0 0>;
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lcm-params-dsi-lk-dsi-clock;
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lcm-params-dsi-lk-ssc-disable = <1>;
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lcm-params-dsi-lk-ssc-range;
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lcm-params-dsi-lk-compatibility-for-nvk;
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lcm-params-dsi-lk-cont-clock;
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lcm-params-dsi-lk-ufoe-enable;
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lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
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lcm-params-dsi-lk-edp-panel;
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lcm-params-dsi-lk-lcm-int-te-monitor;
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lcm-params-dsi-lk-lcm-int-te-period;
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lcm-params-dsi-lk-lcm-ext-te-monitor;
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lcm-params-dsi-lk-lcm-ext-te-period;
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lcm-params-dsi-lk-noncont-clock;
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lcm-params-dsi-lk-noncont-clock-period;
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lcm-params-dsi-lk-clk-lp-per-line-enable = <0>;
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lcm-params-dsi-lk-dual-dsi-type;
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lcm-params-dsi-lk-mixmode-enable;
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lcm-params-dsi-lk-mixmode-mipi-clock;
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lcm-params-dsi-lk-pwm-fps;
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lcm-params-dsi-lk-pll-clock-lp;
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lcm-params-dsi-lk-ulps-sw-enable;
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lcm-params-dsi-lk-null-packet-en;
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lcm-params-dsi-lk-vact-fps;
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lcm-params-dsi-lk-send-frame-enable;
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lcm-params-dsi-lk-lfr-enable;
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lcm-params-dsi-lk-lfr-mode;
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lcm-params-dsi-lk-lfr-type;
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lcm-params-dsi-lk-lfr-skip-num;
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lcm-params-dsi-lk-ext-te-edge;
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lcm-params-dsi-lk-eint-disable;
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lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
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};
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lcm-params-dsi-cm-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-cm-params";
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lcm-params-dsi-cm-enable = <1>;
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lcm-params-dsi-cm-relay = <1>;
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lcm-params-dsi-cm-c00 = <920>;
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lcm-params-dsi-cm-c01 = <72>;
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lcm-params-dsi-cm-c02 = <32>;
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lcm-params-dsi-cm-c10 = <4>;
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lcm-params-dsi-cm-c11 = <956>;
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lcm-params-dsi-cm-c12 = <20>;
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lcm-params-dsi-cm-c20 = <0>;
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lcm-params-dsi-cm-c21 = <4>;
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lcm-params-dsi-cm-c22 = <872>;
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lcm-params-dsi-cm-coeff-round-en;
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lcm-params-dsi-cm-precision-mask;
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lcm-params-dsi-cm-bits-switch;
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lcm-params-dsi-cm-gray-en = <1>;
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};
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lcm-params-dsi-spr-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-spr-params";
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lcm-params-dsi-spr-enable = <1>;
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lcm-params-dsi-spr-relay = <0>;
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lcm-params-dsi-spr-rgb-swap;
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lcm-params-dsi-spr-bypass-dither = <1>;
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lcm-params-dsi-spr-postalign-en = <1>;
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lcm-params-dsi-spr-wrap-mode;
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lcm-params-dsi-spr-specialcaseen;
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lcm-params-dsi-spr-indata-res-sel;
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lcm-params-dsi-spr-outdata-res-sel;
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lcm-params-dsi-spr-padding-repeat-en;
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lcm-params-dsi-spr-postalign-6type-mode-en;
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lcm-params-dsi-spr-custom-header-en;
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lcm-params-dsi-spr-custom-header = <11>;
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lcm-params-dsi-spr-format-type =
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<MTK_LCM_RGBG_BGRG_TYPE>;
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lcm-params-dsi-spr-rg-xy-swap = <0>;
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lcm-params-dsi-spr-ip-params =
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<&mt6985_nt37701_dphy_cmd_120hz_spr>;
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lcm-params-dsi-spr-color-param0-type =
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<MTK_LCM_SPR_WEIGHT_SET>;
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lcm-params-dsi-spr-color-param0-param-list =
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[00 00 88 78 48 b8 48 b8 88 78],
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[00 00 00 00 00 00 00 00 48 b8],
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[88 78 00 00 00 00 88 78 48 b8],
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[00 00 00 00 00 00];
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lcm-params-dsi-spr-color-param0-tune-list;
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lcm-params-dsi-spr-color-param1-type =
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<MTK_LCM_SPR_BORDER_SET>;
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lcm-params-dsi-spr-color-param1-param-list =
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[00 01 00 00 01 00 00 00 00 00],
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 00 00 00 01 00 00],
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[00 00 00 00 00 04 00 00 00 00],
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[00 00 40 80 80 80 80 80 60 80];
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lcm-params-dsi-spr-color-param1-tune-list;
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lcm-params-dsi-spr-color-param2-type =
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<MTK_LCM_SPR_SPE_SET>;
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lcm-params-dsi-spr-color-param2-param-list =
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 00 00 00 00 00 00],
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[00 00 00 00 a0 11 a0 11 a0 11],
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[a0 11 98 11 98 11 98 11 98 11];
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lcm-params-dsi-spr-color-param2-tune-list;
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lcm-params-dsi-spr-output-mode =
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<MTK_LCM_PACKED_SPR_8_BITS>;
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};
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lcm-params-dsi-dsc-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-dsc-params";
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lcm-params-dsi-dsc-enable = <1>;
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lcm-params-dsi-dsc-enable-lk = <1>;
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lcm-params-dsi-dsc-ver = <2>;
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lcm-params-dsi-dsc-slice-mode = <0>;
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lcm-params-dsi-dsc-rgb-swap = <0>;
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lcm-params-dsi-dsc-cfg = <0x0001d822>;
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lcm-params-dsi-dsc-rct-on = <0>;
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lcm-params-dsi-dsc-bit-per-channel = <8>;
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lcm-params-dsi-dsc-line-buf-depth = <0>;
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lcm-params-dsi-dsc-bp-enable = <1>;
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lcm-params-dsi-dsc-bit-per-pixel = <256>;
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lcm-params-dsi-dsc-pic-height = <2400>;
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lcm-params-dsi-dsc-pic-width = <1080>;
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lcm-params-dsi-dsc-slice-height = <60>;
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lcm-params-dsi-dsc-slice-width = <1080>;
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lcm-params-dsi-dsc-chunk-size = <1080>;
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lcm-params-dsi-dsc-xmit-delay = <341>;
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lcm-params-dsi-dsc-dec-delay = <552>;
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lcm-params-dsi-dsc-scale-value = <10>;
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lcm-params-dsi-dsc-increment-interval = <1185>;
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lcm-params-dsi-dsc-decrement-interval = <90>;
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lcm-params-dsi-dsc-line-bpg-offset = <15>;
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lcm-params-dsi-dsc-nfl-bpg-offset = <521>;
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lcm-params-dsi-dsc-slice-bpg-offset = <1220>;
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lcm-params-dsi-dsc-initial-offset = <2048>;
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lcm-params-dsi-dsc-final-offset = <3024>;
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lcm-params-dsi-dsc-flatness-minqp = <3>;
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lcm-params-dsi-dsc-flatness-maxqp = <12>;
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lcm-params-dsi-dsc-rc-model-size = <8192>;
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lcm-params-dsi-dsc-rc-edge-factor = <6>;
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lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
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lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
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lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
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lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
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};
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lcm-params-dsi-phy-timcon-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-phy-timcon";
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lcm-params-dsi-phy-timcon-hs-trail;
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lcm-params-dsi-phy-timcon-hs-prpr;
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lcm-params-dsi-phy-timcon-hs-zero;
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lcm-params-dsi-phy-timcon-lpx;
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lcm-params-dsi-phy-timcon-ta-get;
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lcm-params-dsi-phy-timcon-ta-sure;
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lcm-params-dsi-phy-timcon-ta-go;
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lcm-params-dsi-phy-timcon-da-hs-exit;
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lcm-params-dsi-phy-timcon-clk-trail;
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lcm-params-dsi-phy-timcon-cont-det;
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lcm-params-dsi-phy-timcon-da-hs-sync;
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lcm-params-dsi-phy-timcon-clk-zero;
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lcm-params-dsi-phy-timcon-clk-prpr;
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lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-0-1080-2400-60 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en;
|
|
lcm-params-dsi-dyn-pll-clk;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-0-1080-2400-60 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-2-1080-2400-120 {
|
|
compatible = "mediatek,lcm-dsi-fps-2-1080-2400-120";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <120>;
|
|
lcm-params-dsi-vertical-sync-active = <2>;
|
|
lcm-params-dsi-vertical-backporch = <8>;
|
|
lcm-params-dsi-vertical-frontporch = <20>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <10>;
|
|
lcm-params-dsi-horizontal-backporch = <20>;
|
|
lcm-params-dsi-horizontal-frontporch = <40>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <335340>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <410>;
|
|
lcm-params-dsi-data-rate = <820>;
|
|
lcm-params-dsi-vfp-for-low-power;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lp-perline-en = <1>;
|
|
lcm-params-dsi-lfr-enable;
|
|
lcm-params-dsi-lfr-minimum-fps;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
lcm-params-dsi-lcm-is-support-od = <1>;
|
|
lcm-params-dsi-lcm-is-support-dmr = <1>;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 9c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
lcm-params-dsi-cm-params-0-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-cm-params";
|
|
lcm-params-dsi-cm-enable = <1>;
|
|
lcm-params-dsi-cm-relay = <1>;
|
|
lcm-params-dsi-cm-c00 = <920>;
|
|
lcm-params-dsi-cm-c01 = <72>;
|
|
lcm-params-dsi-cm-c02 = <32>;
|
|
lcm-params-dsi-cm-c10 = <4>;
|
|
lcm-params-dsi-cm-c11 = <956>;
|
|
lcm-params-dsi-cm-c12 = <20>;
|
|
lcm-params-dsi-cm-c20 = <0>;
|
|
lcm-params-dsi-cm-c21 = <4>;
|
|
lcm-params-dsi-cm-c22 = <872>;
|
|
lcm-params-dsi-cm-coeff-round-en;
|
|
lcm-params-dsi-cm-precision-mask;
|
|
lcm-params-dsi-cm-bits-switch;
|
|
lcm-params-dsi-cm-gray-en = <1>;
|
|
};
|
|
|
|
lcm-params-dsi-spr-params-0-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-spr-params";
|
|
lcm-params-dsi-spr-enable = <1>;
|
|
lcm-params-dsi-spr-relay = <0>;
|
|
lcm-params-dsi-spr-rgb-swap;
|
|
lcm-params-dsi-spr-bypass-dither = <1>;
|
|
lcm-params-dsi-spr-postalign-en = <1>;
|
|
lcm-params-dsi-spr-wrap-mode;
|
|
lcm-params-dsi-spr-specialcaseen;
|
|
lcm-params-dsi-spr-indata-res-sel;
|
|
lcm-params-dsi-spr-outdata-res-sel;
|
|
lcm-params-dsi-spr-padding-repeat-en;
|
|
lcm-params-dsi-spr-postalign-6type-mode-en;
|
|
lcm-params-dsi-spr-custom-header-en;
|
|
lcm-params-dsi-spr-custom-header = <11>;
|
|
lcm-params-dsi-spr-format-type =
|
|
<MTK_LCM_RGBG_BGRG_TYPE>;
|
|
lcm-params-dsi-spr-rg-xy-swap = <0>;
|
|
lcm-params-dsi-spr-ip-params =
|
|
<&mt6985_nt37701_dphy_cmd_120hz_spr>;
|
|
|
|
lcm-params-dsi-spr-color-param0-type =
|
|
<MTK_LCM_SPR_WEIGHT_SET>;
|
|
lcm-params-dsi-spr-color-param0-param-list =
|
|
[40 40 80 80 00 00 00 00],
|
|
[80 80 40 40 00 00 00 00],
|
|
[00 00 00 00 80 80 40 40],
|
|
[40 40 80 80 00 00 00 00],
|
|
[00 00 00 00];
|
|
lcm-params-dsi-spr-color-param0-tune-list;
|
|
|
|
lcm-params-dsi-spr-color-param1-type =
|
|
<MTK_LCM_SPR_BORDER_SET>;
|
|
lcm-params-dsi-spr-color-param1-param-list =
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 00 00 00 00 00 00 00],
|
|
[00 01 00 00 00 00 00 00],
|
|
[00 04 00 00 00 00 00 00],
|
|
[40 80 40 80 40 80 40 80];
|
|
lcm-params-dsi-spr-color-param1-tune-list;
|
|
|
|
lcm-params-dsi-spr-color-param2-type =
|
|
<MTK_LCM_SPR_SPE_SET>;
|
|
lcm-params-dsi-spr-color-param2-param-list =
|
|
[10 65 10 9D 10 E5 11 79],
|
|
[11 79 11 79 10 05 10 05],
|
|
[10 78 10 78 10 05 10 9D],
|
|
[10 65 10 E5 11 1D 11 79],
|
|
[11 79 11 79 11 79 11 79],
|
|
[11 79 11 79 01 79 00 00],
|
|
[00 00 00 00 01 79 00 00],
|
|
[00 00 00 00];
|
|
lcm-params-dsi-spr-color-param2-tune-list;
|
|
lcm-params-dsi-spr-output-mode =
|
|
<MTK_LCM_PACKED_SPR_8_BITS>;
|
|
};
|
|
|
|
lcm-params-dsi-dsc-params-0-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-ver = <2>;
|
|
lcm-params-dsi-dsc-slice-mode = <0>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <0x0001d822>;
|
|
lcm-params-dsi-dsc-rct-on = <0>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <0>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <256>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <60>;
|
|
lcm-params-dsi-dsc-slice-width = <1080>;
|
|
lcm-params-dsi-dsc-chunk-size = <1080>;
|
|
lcm-params-dsi-dsc-xmit-delay = <341>;
|
|
lcm-params-dsi-dsc-dec-delay = <552>;
|
|
lcm-params-dsi-dsc-scale-value = <10>;
|
|
lcm-params-dsi-dsc-increment-interval = <1185>;
|
|
lcm-params-dsi-dsc-decrement-interval = <90>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <15>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <521>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <1220>;
|
|
lcm-params-dsi-dsc-initial-offset = <2048>;
|
|
lcm-params-dsi-dsc-final-offset = <3024>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en;
|
|
lcm-params-dsi-dyn-pll-clk;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lcm-ops {
|
|
compatible = "mediatek,lcm-ops";
|
|
lcm-ops-dbi {
|
|
compatible = "mediatek,lcm-ops-dbi";
|
|
/* future reserved for dbi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dpi {
|
|
compatible = "mediatek,lcm-ops-dpi";
|
|
/* future reserved for dpi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dsi {
|
|
compatible = "mediatek,lcm-ops-dsi";
|
|
prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 06],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04],
|
|
[B5 2B 06 33],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 0B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04],
|
|
[B5 2B 23 33],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[B5 06 06 06 06 06],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04],
|
|
[C0 76 F3 C1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 B9 00 96],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 BD 04 B0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C9 84],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[CB 05 0F 1F 3E 7C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 06],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0b],
|
|
[CB 00 08 00 3C 01 48 07 FF 0F],
|
|
[FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C2 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B1 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B2 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04],
|
|
[B2 00 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04],
|
|
[B2 09 E3 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 07],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04],
|
|
[B2 09 E4 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6F 0A],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 04],
|
|
[B2 09 E3 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 CB 86],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05],
|
|
[D0 00 00 00 10],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[f0 55 aa 52 08 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6f 08],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 de 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6f 09],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 07],
|
|
[de 10 34 25 30 14 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[f0 55 aa 52 08 07],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 b0 24],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
|
|
[F0 55 AA 52 08 08],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 C0 8E FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05],
|
|
[3B 00 14 00 1C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 03 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 90 91],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 13],
|
|
[91 80 f0 00 3c f1 55 02 28 04],
|
|
[a1 00 5a 02 09 04 c4 0b d0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 2C],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05],
|
|
[51 07 FF 0F FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 28],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05],
|
|
[2A 00 00 04 37],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 05],
|
|
[2B 00 00 09 5F],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_CONDITION 04],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_MODE 00 2F 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_CONDITION 04],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_MODE 01 2F 02],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02 MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 01],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02 MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 0F FF],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 11],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
unprepare-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 28],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 10],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 c8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4f 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-display-on-table = [MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
lcm-update-table = [MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 05 39 02],
|
|
/*2a is of data[1] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2a],
|
|
/*x0-msb is of data[1] bit8 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_MSB_BIT 03 01 08 00],
|
|
/*x0-lsb is of data[1] bit16 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_LSB_BIT 03 01 10 00],
|
|
/*x1-msb is of data[1] bit24 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_MSB_BIT 03 01 18 00],
|
|
/*x0-lsb is of data[2] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_LSB_BIT 03 02 00 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 05 39 02],
|
|
/*2b is of data[1] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2b],
|
|
/*y0-msb is of data[1] bit8 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_MSB_BIT 03 01 08 00],
|
|
/*y0-lsb is of data[1] bit16 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_LSB_BIT 03 01 10 00],
|
|
/*y1-msb is of data[1] bit24 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_MSB_BIT 03 01 18 00],
|
|
/*y0-lsb is of data[2] bit0 */
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_LSB_BIT 03 02 00 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
|
|
[00 00 2c 39 09],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM_UNFORCE 00],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-backlight-mask = <0xfff>;
|
|
set-backlight-cmdq-table =
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 0F FF],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01],
|
|
[02 51 FF],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02],
|
|
[MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-elvss-cmdq-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
|
|
[MTK_LCM_INPUT_TYPE_HEX_MISC 01 01],
|
|
[02 83 ff],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-backlight-elvss-cmdq-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
|
|
[03 51 0F FF],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
|
|
[MTK_LCM_INPUT_TYPE_HEX_MISC 01 01],
|
|
[02 83 ff],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-aod-light-mask = <0xfff>;
|
|
set-aod-light-table;
|
|
|
|
ata-id-value-data;
|
|
ata-check-table;
|
|
|
|
compare-id-value-data = [00];
|
|
compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 da],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-enable-start-table;
|
|
|
|
doze-enable-table;
|
|
|
|
doze-disable-table;
|
|
|
|
doze-area-table;
|
|
|
|
doze-post-disp-on-table;
|
|
|
|
hbm-set-cmdq-switch-id;
|
|
hbm-set-cmdq-switch-on;
|
|
hbm-set-cmdq-switch-off;
|
|
hbm-set-cmdq-table;
|
|
|
|
/* fps switch cmd for high frame rate feature */
|
|
lcm-ops-dsi-fps-switch-after-poweron {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
|
|
fps-switch-0-1080-2400-60-table;
|
|
|
|
fps-switch-2-1080-2400-120-table;
|
|
};
|
|
|
|
lcm-ops-dsi-fps-switch-before-powerdown {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
|
|
fps-switch-0-1080-2400-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1080-2400-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2F 02],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|