1344 lines
52 KiB
Text
1344 lines
52 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/*
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* Device Tree defines for LCM settings
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include "mtk_lcm_settings.h"
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&pio {
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nt36672e_fhdp_cphy_vdo_jdi_120hz: nt36672e-fhdp-cphy-vdo-jdi-120hz {
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compatible = "mediatek,nt36672e_fhdp_cphy_vdo_jdi_120hz";
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lcm-version = <0>;
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lcm-params{
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compatible = "mediatek,lcm-params";
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lcm-params-name = "nt36672e-fhdp-cphy-vdo-jdi-120hz";
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lcm-params-types = <MTK_LCM_FUNC_DSI>;
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lcm-params-resolution = <1080 2400>;
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lcm-params-physical-width;
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lcm-params-physical-height;
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/* lk support */
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lcm-params-lk {
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compatible = "mediatek,lcm-params-lk";
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lcm-params-lk-ctrl;
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lcm-params-lk-lcm-if;
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lcm-params-lk-lcm-cmd-if;
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lcm-params-lk-io-select-mode;
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lcm-params-lk-lcm-x;
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lcm-params-lk-lcm-y;
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lcm-params-lk-virtual-resolution = <0 0>;
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lcm-params-lk-od-table-size;
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lcm-params-lk-od-table;
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};
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lcm-params-lk-round-corner {
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compatible = "mediatek,lcm-params-lk-round-corner";
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lcm-params-lk-rc-round-corner-en = <0>;
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lcm-params-lk-rc-is-notch;
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lcm-params-lk-rc-full-content = <0>;
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lcm-params-lk-rc-width;
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lcm-params-lk-rc-height;
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lcm-params-lk-rc-width-bot;
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lcm-params-lk-rc-height-bot;
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lcm-params-lk-rc-top-size;
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lcm-params-lk-rc-top-size-left;
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lcm-params-lk-rc-top-size-right;
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lcm-params-lk-rc-bottom-size;
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lcm-params-lk-rc-pattern-name;
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};
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lcm-params-dbi {
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compatible = "mediatek,lcm-params-dbi";
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/* future reserved for dbi interfaces */
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};
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lcm-params-dpi {
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compatible = "mediatek,lcm-params-dpi";
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/* future reserved for dpi interfaces */
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};
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lcm-params-dsi {
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compatible = "mediatek,lcm-params-dsi";
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lcm-params-dsi-density = <480>;
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lcm-params-dsi-lanes = <3>;
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lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
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lcm-params-dsi-phy-type = <MTK_LCM_MIPI_CPHY>;
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lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_VIDEO>,
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<MTK_MIPI_DSI_MODE_VIDEO_SYNC_PULSE>,
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<MTK_MIPI_DSI_MODE_LPM>,
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<MTK_MIPI_DSI_MODE_EOT_PACKET>,
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<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
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lcm-params-dsi-mode-flags-doze-on;
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lcm-params-dsi-mode-flags-doze-off;
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lcm-params-dsi-need-fake-resolution;
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lcm-params-dsi-fake-resolution = <1080 2400>;
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lcm-gpio-list = <&pio 42 0>, /* gpio list*/
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<&pio 28 0>,
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<&pio 29 0>;
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pinctrl-names = "gpio1", "gpio2", "gpio3";
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pinctrl-0;
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pinctrl-1;
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pinctrl-2;
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status = "okay";
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lcm-params-dsi-default-mode = <0>;
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lcm-params-dsi-mode-count = <3>;
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lcm-params-dsi-mode-list =
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<0 1080 2400 60>,
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<1 1080 2400 90>,
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<2 1080 2400 120>;
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lcm-params-dsi-fps-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-fps-0-1080-2400-60";
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lcm-params-dsi-voltage;
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lcm-params-dsi-fake = <0>;
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/* drm-display-mode */
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lcm-params-dsi-vrefresh = <60>;
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lcm-params-dsi-vertical-sync-active = <10>;
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lcm-params-dsi-vertical-backporch = <10>;
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lcm-params-dsi-vertical-frontporch = <3524>;
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lcm-params-dsi-vertical-active-line = <2400>;
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lcm-params-dsi-horizontal-sync-active = <12>;
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lcm-params-dsi-horizontal-backporch = <80>;
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lcm-params-dsi-horizontal-frontporch = <76>;
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lcm-params-dsi-horizontal-active-pixel = <1080>;
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lcm-params-dsi-pixel-clock = <443290>;
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lcm-params-dsi-hskew;
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lcm-params-dsi-vscan;
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/* mtk-panel-params */
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lcm-params-dsi-pll-clock = <422>;
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lcm-params-dsi-data-rate = <844>;
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lcm-params-dsi-vfp-for-low-power = <5500>;
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lcm-params-dsi-ssc-enable;
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lcm-params-dsi-ssc-range;
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lcm-params-dsi-lcm-color-mode;
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lcm-params-dsi-min-luminance;
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lcm-params-dsi-average-luminance;
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lcm-params-dsi-max-luminance;
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lcm-params-dsi-round-corner-en = <0>;
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lcm-params-dsi-corner-pattern-height;
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lcm-params-dsi-corner-pattern-height-bot;
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lcm-params-dsi-corner-pattern-tp-size;
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lcm-params-dsi-corner-pattern-tp-size-left;
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lcm-params-dsi-corner-pattern-tp-size-right;
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lcm-params-dsi-corner-pattern-name;
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lcm-params-dsi-physical-width-um;
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lcm-params-dsi-physical-height-um;
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lcm-params-dsi-output-mode =
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<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
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lcm-params-dsi-lcm-cmd-if;
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lcm-params-dsi-hbm-en-time;
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lcm-params-dsi-hbm-dis-time;
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lcm-params-dsi-lcm-index;
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lcm-params-dsi-wait-sof-before-dec-vfp;
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lcm-params-dsi-doze-delay;
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lcm-params-dsi-lfr-enable;
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lcm-params-dsi-lfr-minimum-fps;
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lcm-params-dsi-msync2-enable;
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lcm-params-dsi-max-vfp-for-msync;
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/* lane swap */
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lcm-params-dsi-lane-swap-en = <0>;
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lcm-params-dsi-lane-swap0;
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lcm-params-dsi-lane-swap1;
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/* esd check table */
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lcm-params-dsi-cust-esd-check = <0>;
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lcm-params-dsi-esd-check-enable = <1>;
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lcm-params-dsi-lcm-esd-check-table0 = [0a 01 9c];
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lcm-params-dsi-lcm-esd-check-table1;
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lcm-params-dsi-lcm-esd-check-table2;
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/* fpga support */
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lcm-params-dsi-fpga-params-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-fpga-params";
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lcm-params-dsi-lk-pll-div = <0 0>;
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lcm-params-dsi-lk-fbk-div = <1>;
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};
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/* lk support */
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lcm-params-dsi-lk-params-0-1080-2400-60 {
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compatible = "mediatek,lcm-dsi-lk-params";
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lcm-params-dsi-lk-mode =
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<MTK_LK_SYNC_PULSE_VDO_MODE>;
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lcm-params-dsi-lk-switch-mode = <MTK_LK_CMD_MODE>;
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lcm-params-dsi-lk-switch-mode-enable = <0>;
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lcm-params-dsi-lk-dsi-wmem-conti;
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lcm-params-dsi-lk-dsi-rmem-conti;
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lcm-params-dsi-lk-vc-num;
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lcm-params-dsi-lk-data-format =
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<MTK_LCM_COLOR_ORDER_RGB>,
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<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
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<MTK_LCM_DSI_PADDING_ON_LSB>,
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<MTK_LCM_DSI_FORMAT_RGB888>;
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lcm-params-dsi-lk-intermediat-buffer-num;
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lcm-params-dsi-lk-ps =
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<MTK_LCM_PACKED_PS_24BIT_RGB888>;
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lcm-params-dsi-lk-word-count;
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lcm-params-dsi-lk-packet-size = <256>;
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lcm-params-dsi-lk-horizontal-blanking-pixel;
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lcm-params-dsi-lk-bllp;
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lcm-params-dsi-lk-line-byte;
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lcm-params-dsi-lk-horizontal-sync-active-byte;
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lcm-params-dsi-lk-horizontal-backporch-byte;
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lcm-params-dsi-lk-horizontal-frontporch-byte;
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lcm-params-dsi-lk-rgb-byte;
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lcm-params-dsi-lk-horizontal-sync-active-word-count;
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lcm-params-dsi-lk-horizontal-backporch-word-count;
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lcm-params-dsi-lk-horizontal-frontporch-word-count;
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lcm-params-dsi-lk-pll-select;
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lcm-params-dsi-lk-pll-div;
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lcm-params-dsi-lk-fbk-div;
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lcm-params-dsi-lk-fbk-sel;
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lcm-params-dsi-lk-rg = <0 0 0>;
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lcm-params-dsi-lk-dsi-clock;
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lcm-params-dsi-lk-ssc-disable = <1>;
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lcm-params-dsi-lk-ssc-range;
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lcm-params-dsi-lk-compatibility-for-nvk;
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lcm-params-dsi-lk-cont-clock;
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lcm-params-dsi-lk-ufoe-enable;
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lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
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lcm-params-dsi-lk-edp-panel;
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lcm-params-dsi-lk-lcm-int-te-monitor;
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lcm-params-dsi-lk-lcm-int-te-period;
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lcm-params-dsi-lk-lcm-ext-te-monitor;
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lcm-params-dsi-lk-lcm-ext-te-period;
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lcm-params-dsi-lk-noncont-clock;
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lcm-params-dsi-lk-noncont-clock-period;
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lcm-params-dsi-lk-clk-lp-per-line-enable = <0>;
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lcm-params-dsi-lk-dual-dsi-type;
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lcm-params-dsi-lk-mixmode-enable;
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lcm-params-dsi-lk-mixmode-mipi-clock;
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lcm-params-dsi-lk-pwm-fps;
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lcm-params-dsi-lk-pll-clock-lp;
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lcm-params-dsi-lk-ulps-sw-enable;
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lcm-params-dsi-lk-null-packet-en;
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lcm-params-dsi-lk-vact-fps;
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lcm-params-dsi-lk-send-frame-enable;
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lcm-params-dsi-lk-lfr-enable;
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lcm-params-dsi-lk-lfr-mode;
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lcm-params-dsi-lk-lfr-type;
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lcm-params-dsi-lk-lfr-skip-num;
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lcm-params-dsi-lk-ext-te-edge;
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lcm-params-dsi-lk-eint-disable;
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lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
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};
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lcm-params-dsi-dsc-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-dsc-params";
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lcm-params-dsi-dsc-enable = <1>;
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lcm-params-dsi-dsc-enable-lk = <1>;
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lcm-params-dsi-dsc-ver = <17>;
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lcm-params-dsi-dsc-slice-mode = <1>;
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lcm-params-dsi-dsc-rgb-swap = <0>;
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lcm-params-dsi-dsc-cfg = <34>;
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lcm-params-dsi-dsc-rct-on = <1>;
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lcm-params-dsi-dsc-bit-per-channel = <8>;
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lcm-params-dsi-dsc-line-buf-depth = <11>;
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lcm-params-dsi-dsc-bp-enable = <1>;
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lcm-params-dsi-dsc-bit-per-pixel = <128>;
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lcm-params-dsi-dsc-pic-height = <2400>;
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lcm-params-dsi-dsc-pic-width = <1080>;
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lcm-params-dsi-dsc-slice-height = <20>;
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lcm-params-dsi-dsc-slice-width = <540>;
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lcm-params-dsi-dsc-chunk-size = <540>;
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lcm-params-dsi-dsc-xmit-delay = <170>;
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lcm-params-dsi-dsc-dec-delay = <526>;
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lcm-params-dsi-dsc-scale-value = <32>;
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lcm-params-dsi-dsc-increment-interval = <113>;
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lcm-params-dsi-dsc-decrement-interval = <7>;
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lcm-params-dsi-dsc-line-bpg-offset = <12>;
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lcm-params-dsi-dsc-nfl-bpg-offset = <1294>;
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lcm-params-dsi-dsc-slice-bpg-offset = <1302>;
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lcm-params-dsi-dsc-initial-offset = <6144>;
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lcm-params-dsi-dsc-final-offset = <7072>;
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lcm-params-dsi-dsc-flatness-minqp = <3>;
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lcm-params-dsi-dsc-flatness-maxqp = <12>;
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lcm-params-dsi-dsc-rc-model-size = <8192>;
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lcm-params-dsi-dsc-rc-edge-factor = <6>;
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lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
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lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
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lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
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lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
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};
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lcm-params-dsi-phy-timcon-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-phy-timcon";
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lcm-params-dsi-phy-timcon-hs-trail;
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lcm-params-dsi-phy-timcon-hs-prpr;
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lcm-params-dsi-phy-timcon-hs-zero;
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lcm-params-dsi-phy-timcon-lpx;
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lcm-params-dsi-phy-timcon-ta-get;
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lcm-params-dsi-phy-timcon-ta-sure;
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lcm-params-dsi-phy-timcon-ta-go;
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lcm-params-dsi-phy-timcon-da-hs-exit;
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lcm-params-dsi-phy-timcon-clk-trail;
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lcm-params-dsi-phy-timcon-cont-det;
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lcm-params-dsi-phy-timcon-da-hs-sync;
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lcm-params-dsi-phy-timcon-clk-zero;
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lcm-params-dsi-phy-timcon-clk-prpr;
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lcm-params-dsi-phy-timcon-clk-exit;
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lcm-params-dsi-phy-timcon-clk-post;
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/* lk support */
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lcm-params-dsi-phy-timcon-lk-hs-trail;
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lcm-params-dsi-phy-timcon-lk-hs-zero;
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lcm-params-dsi-phy-timcon-lk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-lpx;
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lcm-params-dsi-phy-timcon-lk-ta-sack;
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lcm-params-dsi-phy-timcon-lk-ta-get;
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lcm-params-dsi-phy-timcon-lk-ta-sure;
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lcm-params-dsi-phy-timcon-lk-ta-go;
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lcm-params-dsi-phy-timcon-lk-clk-trail;
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lcm-params-dsi-phy-timcon-lk-clk-zero;
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lcm-params-dsi-phy-timcon-lk-lpx-wait;
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lcm-params-dsi-phy-timcon-lk-cont-det;
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lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
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lcm-params-dsi-phy-timcon-lk-clk-hs-post;
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lcm-params-dsi-phy-timcon-lk-da-hs-exit;
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lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
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};
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lcm-params-dsi-dyn-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-dyn";
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lcm-params-dsi-dyn-switch-en = <0>;
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lcm-params-dsi-dyn-pll-clk = <428>;
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lcm-params-dsi-dyn-data-rate;
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lcm-params-dsi-dyn-vsa;
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lcm-params-dsi-dyn-vbp;
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lcm-params-dsi-dyn-vfp = <2528>;
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lcm-params-dsi-dyn-vfp-lp-dyn = <4178>;
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lcm-params-dsi-dyn-vac;
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lcm-params-dsi-dyn-hsa;
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lcm-params-dsi-dyn-hbp;
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lcm-params-dsi-dyn-hfp = <396>;
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lcm-params-dsi-dyn-hac;
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lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
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};
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lcm-params-dsi-dyn-fps-params-0-1080-2400-60 {
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compatible =
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"mediatek,lcm-params-dsi-dyn-fps";
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lcm-params-dsi-dyn-fps-switch-en = <0>;
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lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
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lcm-params-dsi-dyn-fps-data-rate;
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lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
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[00 02 ff 25];
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lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
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[00 02 fb 01];
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lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
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[00 02 18 21];
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lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
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[00 02 ff 10];
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lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
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[00 02 fb 01];
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lcm-params-dsi-dyn-fps-dfps-cmd-table5;
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lcm-params-dsi-dyn-fps-dfps-cmd-table6;
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lcm-params-dsi-dyn-fps-dfps-cmd-table7;
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lcm-params-dsi-dyn-fps-dfps-cmd-table8;
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lcm-params-dsi-dyn-fps-dfps-cmd-table9;
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lcm-params-dsi-dyn-fps-dfps-cmd-table10;
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lcm-params-dsi-dyn-fps-dfps-cmd-table11;
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lcm-params-dsi-dyn-fps-dfps-cmd-table12;
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lcm-params-dsi-dyn-fps-dfps-cmd-table13;
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lcm-params-dsi-dyn-fps-dfps-cmd-table14;
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lcm-params-dsi-dyn-fps-dfps-cmd-table15;
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lcm-params-dsi-dyn-fps-dfps-cmd-table16;
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lcm-params-dsi-dyn-fps-dfps-cmd-table17;
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lcm-params-dsi-dyn-fps-dfps-cmd-table18;
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lcm-params-dsi-dyn-fps-dfps-cmd-table19;
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};
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};
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lcm-params-dsi-fps-1-1080-2400-90 {
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compatible = "mediatek,lcm-dsi-fps-1-1080-2400-90";
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lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <90>;
|
|
lcm-params-dsi-vertical-sync-active = <10>;
|
|
lcm-params-dsi-vertical-backporch = <10>;
|
|
lcm-params-dsi-vertical-frontporch = <1542>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <12>;
|
|
lcm-params-dsi-horizontal-backporch = <80>;
|
|
lcm-params-dsi-horizontal-frontporch = <76>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <443290>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <422>;
|
|
lcm-params-dsi-data-rate = <844>;
|
|
lcm-params-dsi-vfp-for-low-power = <3524>;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable = <1>;
|
|
lcm-params-dsi-lfr-minimum-fps = <60>;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 9c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
lcm-params-dsi-dsc-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-dsc-slice-height = <20>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <170>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-dsc-increment-interval = <113>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <1294>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <1302>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <7072>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <0>;
|
|
lcm-params-dsi-dyn-pll-clk = <428>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp = <879>;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn = <2528>;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp = <396>;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-1-1080-2400-90 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
|
|
[00 02 ff 25];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
|
|
[00 02 fb 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
|
|
[00 02 18 20];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
|
|
[00 02 ff 10];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
|
|
[00 02 fb 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
|
|
lcm-params-dsi-fps-2-1080-2400-120 {
|
|
compatible = "mediatek,lcm-dsi-fps-2-1080-2400-120";
|
|
lcm-params-dsi-voltage;
|
|
lcm-params-dsi-fake = <0>;
|
|
|
|
/* drm-display-mode */
|
|
lcm-params-dsi-vrefresh = <120>;
|
|
lcm-params-dsi-vertical-sync-active = <10>;
|
|
lcm-params-dsi-vertical-backporch = <10>;
|
|
lcm-params-dsi-vertical-frontporch = <500>;
|
|
lcm-params-dsi-vertical-active-line = <2400>;
|
|
lcm-params-dsi-horizontal-sync-active = <12>;
|
|
lcm-params-dsi-horizontal-backporch = <80>;
|
|
lcm-params-dsi-horizontal-frontporch = <76>;
|
|
lcm-params-dsi-horizontal-active-pixel = <1080>;
|
|
lcm-params-dsi-pixel-clock = <437299>;
|
|
lcm-params-dsi-hskew;
|
|
lcm-params-dsi-vscan;
|
|
|
|
/* mtk-panel-params */
|
|
lcm-params-dsi-pll-clock = <422>;
|
|
lcm-params-dsi-data-rate = <844>;
|
|
lcm-params-dsi-vfp-for-low-power = <3524>;
|
|
lcm-params-dsi-ssc-enable;
|
|
lcm-params-dsi-ssc-range;
|
|
lcm-params-dsi-lcm-color-mode;
|
|
lcm-params-dsi-min-luminance;
|
|
lcm-params-dsi-average-luminance;
|
|
lcm-params-dsi-max-luminance;
|
|
lcm-params-dsi-round-corner-en = <0>;
|
|
lcm-params-dsi-corner-pattern-height;
|
|
lcm-params-dsi-corner-pattern-height-bot;
|
|
lcm-params-dsi-corner-pattern-tp-size;
|
|
lcm-params-dsi-corner-pattern-tp-size-left;
|
|
lcm-params-dsi-corner-pattern-tp-size-right;
|
|
lcm-params-dsi-corner-pattern-name;
|
|
lcm-params-dsi-physical-width-um;
|
|
lcm-params-dsi-physical-height-um;
|
|
lcm-params-dsi-output-mode =
|
|
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
|
|
lcm-params-dsi-lcm-cmd-if;
|
|
lcm-params-dsi-hbm-en-time;
|
|
lcm-params-dsi-hbm-dis-time;
|
|
lcm-params-dsi-lcm-index;
|
|
lcm-params-dsi-wait-sof-before-dec-vfp;
|
|
lcm-params-dsi-doze-delay;
|
|
lcm-params-dsi-lfr-enable = <1>;
|
|
lcm-params-dsi-lfr-minimum-fps = <60>;
|
|
lcm-params-dsi-msync2-enable;
|
|
lcm-params-dsi-max-vfp-for-msync;
|
|
|
|
/* lane swap */
|
|
lcm-params-dsi-lane-swap-en;
|
|
lcm-params-dsi-lane-swap0;
|
|
lcm-params-dsi-lane-swap1;
|
|
|
|
/* esd check table */
|
|
lcm-params-dsi-cust-esd-check = <0>;
|
|
lcm-params-dsi-esd-check-enable = <1>;
|
|
lcm-params-dsi-lcm-esd-check-table0 = [0a 01 9c];
|
|
lcm-params-dsi-lcm-esd-check-table1;
|
|
lcm-params-dsi-lcm-esd-check-table2;
|
|
|
|
/* fpga support */
|
|
lcm-params-dsi-fpga-params-2-1080-2400-120 {
|
|
compatible = "mediatek,lcm-dsi-fpga-params";
|
|
|
|
lcm-params-dsi-lk-pll-div = <0 0>;
|
|
lcm-params-dsi-lk-fbk-div = <1>;
|
|
};
|
|
|
|
lcm-params-dsi-dsc-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dsc-params";
|
|
lcm-params-dsi-dsc-enable = <1>;
|
|
lcm-params-dsi-dsc-enable-lk = <1>;
|
|
lcm-params-dsi-dsc-ver = <17>;
|
|
lcm-params-dsi-dsc-slice-mode = <1>;
|
|
lcm-params-dsi-dsc-rgb-swap = <0>;
|
|
lcm-params-dsi-dsc-cfg = <34>;
|
|
lcm-params-dsi-dsc-rct-on = <1>;
|
|
lcm-params-dsi-dsc-bit-per-channel = <8>;
|
|
lcm-params-dsi-lk-dsc-line-buf-depth = <9>;
|
|
lcm-params-dsi-dsc-line-buf-depth = <11>;
|
|
lcm-params-dsi-dsc-bp-enable = <1>;
|
|
lcm-params-dsi-dsc-bit-per-pixel = <128>;
|
|
lcm-params-dsi-dsc-pic-height = <2400>;
|
|
lcm-params-dsi-dsc-pic-width = <1080>;
|
|
lcm-params-dsi-lk-dsc-slice-height = <8>;
|
|
lcm-params-dsi-dsc-slice-height = <20>;
|
|
lcm-params-dsi-dsc-slice-width = <540>;
|
|
lcm-params-dsi-dsc-chunk-size = <540>;
|
|
lcm-params-dsi-dsc-xmit-delay = <170>;
|
|
lcm-params-dsi-dsc-dec-delay = <526>;
|
|
lcm-params-dsi-dsc-scale-value = <32>;
|
|
lcm-params-dsi-lk-dsc-increment-interval = <43>;
|
|
lcm-params-dsi-dsc-increment-interval = <113>;
|
|
lcm-params-dsi-dsc-decrement-interval = <7>;
|
|
lcm-params-dsi-dsc-line-bpg-offset = <12>;
|
|
lcm-params-dsi-lk-dsc-nfl-bpg-offset = <3511>;
|
|
lcm-params-dsi-dsc-nfl-bpg-offset = <1294>;
|
|
lcm-params-dsi-lk-dsc-slice-bpg-offset = <3255>;
|
|
lcm-params-dsi-dsc-slice-bpg-offset = <1302>;
|
|
lcm-params-dsi-dsc-initial-offset = <6144>;
|
|
lcm-params-dsi-dsc-final-offset = <7072>;
|
|
lcm-params-dsi-dsc-flatness-minqp = <3>;
|
|
lcm-params-dsi-dsc-flatness-maxqp = <12>;
|
|
lcm-params-dsi-dsc-rc-model-size = <8192>;
|
|
lcm-params-dsi-dsc-rc-edge-factor = <6>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
|
|
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
|
|
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
|
|
};
|
|
|
|
lcm-params-dsi-phy-timcon-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-phy-timcon";
|
|
lcm-params-dsi-phy-timcon-hs-trail;
|
|
lcm-params-dsi-phy-timcon-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lpx;
|
|
lcm-params-dsi-phy-timcon-ta-get;
|
|
lcm-params-dsi-phy-timcon-ta-sure;
|
|
lcm-params-dsi-phy-timcon-ta-go;
|
|
lcm-params-dsi-phy-timcon-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-clk-trail;
|
|
lcm-params-dsi-phy-timcon-cont-det;
|
|
lcm-params-dsi-phy-timcon-da-hs-sync;
|
|
lcm-params-dsi-phy-timcon-clk-zero;
|
|
lcm-params-dsi-phy-timcon-clk-prpr;
|
|
lcm-params-dsi-phy-timcon-clk-exit;
|
|
lcm-params-dsi-phy-timcon-clk-post;
|
|
|
|
/* lk support */
|
|
lcm-params-dsi-phy-timcon-lk-hs-trail;
|
|
lcm-params-dsi-phy-timcon-lk-hs-zero;
|
|
lcm-params-dsi-phy-timcon-lk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-lpx;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sack;
|
|
lcm-params-dsi-phy-timcon-lk-ta-get;
|
|
lcm-params-dsi-phy-timcon-lk-ta-sure;
|
|
lcm-params-dsi-phy-timcon-lk-ta-go;
|
|
lcm-params-dsi-phy-timcon-lk-clk-trail;
|
|
lcm-params-dsi-phy-timcon-lk-clk-zero;
|
|
lcm-params-dsi-phy-timcon-lk-lpx-wait;
|
|
lcm-params-dsi-phy-timcon-lk-cont-det;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
|
|
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
|
|
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn";
|
|
lcm-params-dsi-dyn-switch-en = <0>;
|
|
lcm-params-dsi-dyn-pll-clk = <428>;
|
|
lcm-params-dsi-dyn-data-rate;
|
|
lcm-params-dsi-dyn-vsa;
|
|
lcm-params-dsi-dyn-vbp;
|
|
lcm-params-dsi-dyn-vfp = <54>;
|
|
lcm-params-dsi-dyn-vfp-lp-dyn = <2528>;
|
|
lcm-params-dsi-dyn-vac;
|
|
lcm-params-dsi-dyn-hsa;
|
|
lcm-params-dsi-dyn-hbp;
|
|
lcm-params-dsi-dyn-hfp = <396>;
|
|
lcm-params-dsi-dyn-hac;
|
|
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
|
|
};
|
|
|
|
lcm-params-dsi-dyn-fps-params-2-1080-2400-120 {
|
|
compatible =
|
|
"mediatek,lcm-params-dsi-dyn-fps";
|
|
lcm-params-dsi-dyn-fps-switch-en = <0>;
|
|
lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
|
|
lcm-params-dsi-dyn-fps-data-rate;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table0 =
|
|
[00 02 ff 25];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table1 =
|
|
[00 02 fb 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table2 =
|
|
[00 02 18 22];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table3 =
|
|
[00 02 ff 10];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table4 =
|
|
[00 02 fb 01];
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
|
|
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lcm-ops {
|
|
compatible = "mediatek,lcm-ops";
|
|
lcm-ops-dbi {
|
|
compatible = "mediatek,lcm-ops-dbi";
|
|
/* future reserved for dbi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dpi {
|
|
compatible = "mediatek,lcm-ops-dpi";
|
|
/* future reserved for dpi interfaces*/
|
|
};
|
|
|
|
lcm-ops-dsi {
|
|
compatible = "mediatek,lcm-ops-dsi";
|
|
prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 b0 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 c0 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[c1 89 28 00 08 00 aa 02 0e 00],
|
|
[2b 00 07 0d b7 0c b7],
|
|
//dSc ON && set PPS
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 c0 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[c1 89 28 00 14 00 aa],
|
|
[02 0e 00 71 00 07 05 0e],
|
|
[05 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 c2 1b a0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 e9 01],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 01 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 06 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 07 38],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 77],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 69 91],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 95 d1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 96 d1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f2 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f3 74],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f4 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f5 74],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f6 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f7 74],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f8 65],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f9 74],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 89 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8a 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8d 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8e 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8f 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 91 15],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 24],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 01 0f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 03 0c],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 1d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 08 2f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 09 2e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0a 2d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0b 2c],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 11 17],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 12 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 13 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 15 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 16 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 17 18],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1b 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1d 1d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 20 2f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 21 2e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 22 2d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 23 2c],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 29 17],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2a 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2b 15],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2f 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 30 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 31 18],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 32 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 34 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 1f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 36 1f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4d 1b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4e 4b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4f 4b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 4b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 71 30],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 79 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7a 82],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7b 96],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7d 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 80 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 81 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 82 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 84 31],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 85 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 86 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 87 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 90 13],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 92 31],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 93 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 94 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 95 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9c f4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9d 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a0 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a2 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a3 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a4 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a5 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 c6 c0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 c9 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 d9 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 e9 02],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 19 e4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 21 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 66 d8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 68 50],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 69 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6b 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6d 0d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6e 48],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 72 41],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 73 4a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 74 d0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 77 62],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 79 81],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7d 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7e 1d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7f 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 80 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 84 0d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 cf 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 d6 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 d7 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ef 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 f0 84],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 26],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 15 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 81 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 83 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 84 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 85 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 86 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 87 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8a 1a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8b 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8c 24],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8e 42],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8f 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 90 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 91 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9a 81],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9b 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9c 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9d 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9e 00],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 27],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 01 60],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 20 81],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 21 ea],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 25 82],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 26 3f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6e 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6f 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 70 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 71 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 72 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 75 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 76 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 77 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7d 09],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7e 5f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 80 23],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 82 09],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 83 5f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 88 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 89 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a5 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a6 23],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a7 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 b6 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 e3 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 e4 e0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 e5 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 e6 33],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 e9 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ea 5e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 eb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ec 67],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 2a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 91],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 03 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 04 73],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 07 64],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0a 60],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0c 06],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0d 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0e 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0f 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 11 58],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 15 0e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 16 79],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 19 0d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1a f2],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1b 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1d 36],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1e 55],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1f 55],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 20 55],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 28 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 29 0b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2a 4b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2b 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2d 08],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2f 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 30 47],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 31 23],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 33 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 34 ff],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 2c],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 36 75],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 37 fb],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 38 2e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 39 73],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 3a 47],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 46 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 47 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4a f0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4e 0e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4f 8b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 52 0e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 54 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 56 36],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 57 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 58 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 59 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 60 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 61 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 62 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 63 ed],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 65 05],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 66 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 67 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 68 4d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6a 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6b c9],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6c 1f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6d e3],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6e c6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6f 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 70 e2],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 71 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7a 04],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7b 40],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7c 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7d 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7f e0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 83 0f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 84 c5],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 87 0f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 88 42],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 89 14],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8b 36],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8c 33],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8d 33],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 8e 33],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 95 80],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 96 fd],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 97 19],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 98 4a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 99 07],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9a 0b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9b 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9c 8b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9d ff],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9f 8b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a0 ff],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a2 4e],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a3 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a4 f8],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a5 52],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a6 fd],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 a7 4b],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 2c],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 00 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 01 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 02 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 03 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 04 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0d 1f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0e 1f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 16 1b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 17 4b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 4b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 19 4b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 2a 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4d 16],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4e 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 54 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 55 02],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 56 0b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 58 0b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 59 0b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 61 19],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 62 19],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6a 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6b 2a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6c 2a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 6d 2a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 7e 03],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9d 0b],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9e 04],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b0 00 00 00 1f 00 49 00 6b 00],
|
|
[85 00 9c 00 b1 00 c4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b1 00 d1 01 07 01 30 01 6e 01],
|
|
[9e 01 e5 02 1e 02 1f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b2 02 56 02 96 02 bf 02 f4 03],
|
|
[16 03 41 03 51 03 5f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0f],
|
|
[b3 03 6e 03 82 03 98 03 ac 03],
|
|
[cc 03 d8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b4 00 00 00 1e 00 49 00 69 00],
|
|
[84 00 9b 00 af 00 c1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b5 00 d2 01 07 01 30 01 6e 01],
|
|
[9d 01 e5 02 1f 02 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b6 02 57 02 96 02 bf 02 f3 03],
|
|
[16 03 3f 03 4f 03 5d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0f],
|
|
[b7 03 6d 03 81 03 98 03 ac 03],
|
|
[cc 03 d8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b8 00 00 00 20 00 48 00 6a 00],
|
|
[86 00 9f 00 b5 00 c6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b9 00 d8 01 0d 01 36 01 73 01],
|
|
[a1 01 e8 02 21 02 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[ba 02 58 02 98 02 c1 02 f7 03],
|
|
[1b 03 41 03 54 03 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0f],
|
|
[bb 03 6e 03 82 03 98 03 ac 03],
|
|
[d0 03 d8 00 00],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 21],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b0 00 00 00 1f 00 49 00 6b 00],
|
|
[85 00 9c 00 b1 00 c4],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b1 00 d1 01 07 01 30 01 6e 01],
|
|
[9e 01 e5 02 1e 02 1f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b2 02 56 02 96 02 bf 02 f4 03],
|
|
[16 03 41 03 51 03 5f],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0f],
|
|
[b3 03 6e 03 82 03 98 03 ac 03],
|
|
[cc 03 d8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b4 00 00 00 1e 00 49 00 69 00],
|
|
[84 00 9b 00 af 00 c1],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b5 00 d2 01 07 01 30 01 6e 01],
|
|
[9d 01 e5 02 1f 02 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b6 02 57 02 96 02 bf 02 f3 03],
|
|
[16 03 3f 03 4f 03 5d],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0f],
|
|
[b7 03 6d 03 81 03 98 03 ac 03],
|
|
[cc 03 d8 00 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b8 00 00 00 20 00 48 00 6a 00],
|
|
[86 00 9f 00 b5 00 c6],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[b9 00 d8 01 0d 01 36 01 73 01],
|
|
[a1 01 e8 02 21 02 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
|
|
[ba 02 58 02 98 02 c1 02 f7 03],
|
|
[1b 03 41 03 54 03 66],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 0f],
|
|
[bb 03 6e 03 82 03 98 03 ac 03],
|
|
[d0 03 d8 00 00],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff e0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 82],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff f0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5a 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 d2 52],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9f 12],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff d0],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 54 02],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff c0],
|
|
//CCMON
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9c 11],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9d 11],
|
|
//CCMOFF CCMRUN
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 51 ff],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 0c],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 55 00],
|
|
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 11],
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 02],
|
|
[MTK_LCM_PHASE_HEX_KERNEL MTK_LCM_PHASE_HEX_LK],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 02],
|
|
[MTK_LCM_PHASE_HEX_KERNEL MTK_LCM_PHASE_HEX_LK],
|
|
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01],
|
|
[02 51 FF],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 01 MTK_LCM_PHASE_HEX_KERNEL],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
unprepare-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 28],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 c8],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-display-on-table =
|
|
[MTK_LCM_PHASE_TYPE_HEX_START 01],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_UTIL_TYPE_HEX_TDELAY 01 78],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
|
|
[MTK_LCM_PHASE_TYPE_HEX_END 01],
|
|
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
lcm-update-table;
|
|
|
|
set-backlight-mask = <0xff>;
|
|
set-backlight-cmdq-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
|
|
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01],
|
|
[02 51 FF],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
set-aod-light-mask = <0xff>;
|
|
set-aod-light-table;
|
|
|
|
ata-id-value-data = [00 80 00];
|
|
ata-check-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_CMD 03 00 03 04],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
compare-id-value-data = [6E];
|
|
compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
|
|
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 20],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
|
|
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
|
|
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
|
|
[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 3B],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
doze-enable-start-table;
|
|
|
|
doze-enable-table;
|
|
|
|
doze-disable-table;
|
|
|
|
doze-area-table;
|
|
|
|
doze-post-disp-on-table;
|
|
|
|
hbm-set-cmdq-switch-id;
|
|
hbm-set-cmdq-switch-on;
|
|
hbm-set-cmdq-switch-off;
|
|
hbm-set-cmdq-table;
|
|
|
|
/* fps switch cmd for high frame rate feature */
|
|
lcm-ops-dsi-fps-switch-after-poweron {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
|
|
fps-switch-0-1080-2400-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 21],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-1-1080-2400-90-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1080-2400-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
|
|
lcm-ops-dsi-fps-switch-before-powerdown {
|
|
compatible =
|
|
"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
|
|
fps-switch-0-1080-2400-60-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 21],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
fps-switch-1-1080-2400-90-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 20],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
|
|
fps-switch-2-1080-2400-120-table =
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 25],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 18 22],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ff 10],
|
|
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 fb 01],
|
|
[MTK_LCM_TYPE_HEX_END];
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|