UbuntuTouchOs/kernel-brax3-ubuntu-touch
4
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity
kernel-brax3-ubuntu-touch/include/dt-bindings/lcm/nt36672c_fhdp_dphy_vdo_tianma_144hz.dtsi
erascape f319b992b1 kernel-5.15: Initial import brax3 UT kernel 
* halium configs enabled

Signed-off-by: erascape <erascape@proton.me>
2025-09-23 15:17:10 +00:00

910 lines
33 KiB
Text
Raw Permalink Blame History

// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
/*
* Device Tree defines for LCM settings
* Copyright (c) 2021 MediaTek Inc.
*/
#include "mtk_lcm_settings.h"
&pio {
nt36672c_fhdp_dphy_vdo_tianma_144hz: nt36672c-fhdp-dphy-vdo-tianma-144hz {
compatible = "mediatek,nt36672c_fhdp_dphy_vdo_tianma_144hz";
lcm-version = <0>;
lcm-params{
compatible = "mediatek,lcm-params";
lcm-params-name = "nt36672c-fhdp-dphy-vdo-tianma-144hz";
lcm-params-types = <MTK_LCM_FUNC_DSI>;
lcm-params-resolution = <1080 2408>;
lcm-params-physical-width = <68>;
lcm-params-physical-height = <152>;
/* lk support */
lcm-params-lk {
compatible = "mediatek,lcm-params-lk";
lcm-params-lk-ctrl;
lcm-params-lk-lcm-if;
lcm-params-lk-lcm-cmd-if;
lcm-params-lk-io-select-mode;
lcm-params-lk-lcm-x;
lcm-params-lk-lcm-y;
lcm-params-lk-virtual-resolution = <0 0>;
lcm-params-lk-od-table-size;
lcm-params-lk-od-table;
};
lcm-params-lk-round-corner {
compatible = "mediatek,lcm-params-lk-round-corner";
lcm-params-lk-rc-round-corner-en = <0>;
lcm-params-lk-rc-is-notch;
lcm-params-lk-rc-full-content = <0>;
lcm-params-lk-rc-width;
lcm-params-lk-rc-height;
lcm-params-lk-rc-width-bot;
lcm-params-lk-rc-height-bot;
lcm-params-lk-rc-top-size;
lcm-params-lk-rc-top-size-left;
lcm-params-lk-rc-top-size-right;
lcm-params-lk-rc-bottom-size;
lcm-params-lk-rc-pattern-name;
};
lcm-params-dbi {
compatible = "mediatek,lcm-params-dbi";
/* future reserved for dbi interfaces */
};
lcm-params-dpi {
compatible = "mediatek,lcm-params-dpi";
/* future reserved for dpi interfaces */
};
lcm-params-dsi {
compatible = "mediatek,lcm-params-dsi";
lcm-params-dsi-density = <480>;
lcm-params-dsi-lanes = <4>;
lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
lcm-params-dsi-phy-type = <MTK_LCM_MIPI_DPHY>;
lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_VIDEO>,
<MTK_MIPI_DSI_MODE_VIDEO_SYNC_PULSE>,
<MTK_MIPI_DSI_MODE_LPM>,
<MTK_MIPI_DSI_MODE_EOT_PACKET>,
<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
lcm-params-dsi-mode-flags-doze-on;
lcm-params-dsi-mode-flags-doze-off;
lcm-params-dsi-need-fake-resolution;
lcm-params-dsi-fake-resolution = <1080 2408>;
lcm-gpio-list = <&pio 42 0>, /* gpio list*/
<&pio 28 0>,
<&pio 29 0>;
pinctrl-names = "gpio1", "gpio2", "gpio3";
pinctrl-0;
pinctrl-1;
pinctrl-2;
status = "okay";
lcm-params-dsi-default-mode = <0>;
lcm-params-dsi-mode-count = <3>;
lcm-params-dsi-mode-list =
<0 1080 2408 144>,
<1 1080 2408 90>,
<2 1080 2408 60>;
lcm-params-dsi-fps-2-1080-2408-60 {
compatible = "mediatek,lcm-dsi-fps-2-1080-2408-60";
lcm-params-dsi-voltage;
lcm-params-dsi-fake = <0>;
/* drm-display-mode */
lcm-params-dsi-vrefresh = <60>;
lcm-params-dsi-vertical-sync-active = <4>;
lcm-params-dsi-vertical-backporch = <16>;
lcm-params-dsi-vertical-frontporch = <3478>;
lcm-params-dsi-vertical-active-line = <2408>;
lcm-params-dsi-horizontal-sync-active = <4>;
lcm-params-dsi-horizontal-backporch = <16>;
lcm-params-dsi-horizontal-frontporch = <72>;
lcm-params-dsi-horizontal-active-pixel = <1080>;
lcm-params-dsi-pixel-clock = <414831>;
lcm-params-dsi-hskew;
lcm-params-dsi-vscan;
/* mtk-panel-params */
lcm-params-dsi-pll-clock = <570>;
lcm-params-dsi-data-rate = <1140>;
lcm-params-dsi-vfp-for-low-power = <4205>;
lcm-params-dsi-ssc-enable;
lcm-params-dsi-ssc-range;
lcm-params-dsi-lcm-color-mode;
lcm-params-dsi-min-luminance;
lcm-params-dsi-average-luminance;
lcm-params-dsi-max-luminance;
lcm-params-dsi-round-corner-en = <0>;
lcm-params-dsi-corner-pattern-height;
lcm-params-dsi-corner-pattern-height-bot;
lcm-params-dsi-corner-pattern-tp-size;
lcm-params-dsi-corner-pattern-tp-size-left;
lcm-params-dsi-corner-pattern-tp-size-right;
lcm-params-dsi-corner-pattern-name;
lcm-params-dsi-physical-width-um = <68364>;
lcm-params-dsi-physical-height-um = <152300>;
lcm-params-dsi-output-mode =
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
lcm-params-dsi-lcm-cmd-if;
lcm-params-dsi-hbm-en-time;
lcm-params-dsi-hbm-dis-time;
lcm-params-dsi-lcm-index;
lcm-params-dsi-wait-sof-before-dec-vfp;
lcm-params-dsi-doze-delay;
lcm-params-dsi-lfr-enable = <1>;
lcm-params-dsi-lfr-minimum-fps = <60>;
lcm-params-dsi-msync2-enable;
lcm-params-dsi-max-vfp-for-msync;
/* lane swap */
lcm-params-dsi-lane-swap-en;
lcm-params-dsi-lane-swap0;
lcm-params-dsi-lane-swap1;
/* esd check table */
lcm-params-dsi-cust-esd-check = <1>;
lcm-params-dsi-esd-check-enable = <1>;
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
lcm-params-dsi-lcm-esd-check-table1;
lcm-params-dsi-lcm-esd-check-table2;
lcm-params-dsi-dsc-params-2-1080-2408-60 {
compatible =
"mediatek,lcm-params-dsi-dsc-params";
lcm-params-dsi-dsc-enable = <1>;
lcm-params-dsi-dsc-enable-lk = <0>;
lcm-params-dsi-dsc-ver = <17>;
lcm-params-dsi-dsc-slice-mode = <1>;
lcm-params-dsi-dsc-rgb-swap = <0>;
lcm-params-dsi-dsc-cfg = <34>;
lcm-params-dsi-dsc-rct-on = <1>;
lcm-params-dsi-dsc-bit-per-channel = <8>;
lcm-params-dsi-dsc-line-buf-depth = <9>;
lcm-params-dsi-dsc-bp-enable = <1>;
lcm-params-dsi-dsc-bit-per-pixel = <128>;
lcm-params-dsi-dsc-pic-height = <2408>;
lcm-params-dsi-dsc-pic-width = <1080>;
lcm-params-dsi-dsc-slice-height = <8>;
lcm-params-dsi-dsc-slice-width = <540>;
lcm-params-dsi-dsc-chunk-size = <540>;
lcm-params-dsi-dsc-xmit-delay = <170>;
lcm-params-dsi-dsc-dec-delay = <526>;
lcm-params-dsi-dsc-scale-value = <32>;
lcm-params-dsi-dsc-increment-interval = <43>;
lcm-params-dsi-dsc-decrement-interval = <7>;
lcm-params-dsi-dsc-line-bpg-offset = <12>;
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
lcm-params-dsi-dsc-initial-offset = <6144>;
lcm-params-dsi-dsc-final-offset = <7072>;
lcm-params-dsi-dsc-flatness-minqp = <3>;
lcm-params-dsi-dsc-flatness-maxqp = <12>;
lcm-params-dsi-dsc-rc-model-size = <8192>;
lcm-params-dsi-dsc-rc-edge-factor = <6>;
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
};
lcm-params-dsi-phy-timcon-params-2-1080-2408-60 {
compatible =
"mediatek,lcm-params-dsi-phy-timcon";
lcm-params-dsi-phy-timcon-hs-trail;
lcm-params-dsi-phy-timcon-hs-prpr;
lcm-params-dsi-phy-timcon-hs-zero;
lcm-params-dsi-phy-timcon-lpx;
lcm-params-dsi-phy-timcon-ta-get;
lcm-params-dsi-phy-timcon-ta-sure;
lcm-params-dsi-phy-timcon-ta-go;
lcm-params-dsi-phy-timcon-da-hs-exit;
lcm-params-dsi-phy-timcon-clk-trail;
lcm-params-dsi-phy-timcon-cont-det;
lcm-params-dsi-phy-timcon-da-hs-sync;
lcm-params-dsi-phy-timcon-clk-zero;
lcm-params-dsi-phy-timcon-clk-prpr;
lcm-params-dsi-phy-timcon-clk-exit;
lcm-params-dsi-phy-timcon-clk-post;
/* lk support */
lcm-params-dsi-phy-timcon-lk-hs-trail;
lcm-params-dsi-phy-timcon-lk-hs-zero;
lcm-params-dsi-phy-timcon-lk-hs-prpr;
lcm-params-dsi-phy-timcon-lk-lpx;
lcm-params-dsi-phy-timcon-lk-ta-sack;
lcm-params-dsi-phy-timcon-lk-ta-get;
lcm-params-dsi-phy-timcon-lk-ta-sure;
lcm-params-dsi-phy-timcon-lk-ta-go;
lcm-params-dsi-phy-timcon-lk-clk-trail;
lcm-params-dsi-phy-timcon-lk-clk-zero;
lcm-params-dsi-phy-timcon-lk-lpx-wait;
lcm-params-dsi-phy-timcon-lk-cont-det;
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
};
lcm-params-dsi-dyn-params-2-1080-2408-60 {
compatible =
"mediatek,lcm-params-dsi-dyn";
lcm-params-dsi-dyn-switch-en = <0>;
lcm-params-dsi-dyn-pll-clk;
lcm-params-dsi-dyn-data-rate = <1140>;
lcm-params-dsi-dyn-vsa;
lcm-params-dsi-dyn-vbp;
lcm-params-dsi-dyn-vfp = <2528>;
lcm-params-dsi-dyn-vfp-lp-dyn = <4178>;
lcm-params-dsi-dyn-vac;
lcm-params-dsi-dyn-hsa;
lcm-params-dsi-dyn-hbp;
lcm-params-dsi-dyn-hfp;
lcm-params-dsi-dyn-hac;
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
};
lcm-params-dsi-dyn-fps-params-2-1080-2408-60 {
compatible =
"mediatek,lcm-params-dsi-dyn-fps";
lcm-params-dsi-dyn-fps-switch-en = <0>;
lcm-params-dsi-dyn-fps-vact-timing-fps = <60>;
lcm-params-dsi-dyn-fps-data-rate;
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
};
};
lcm-params-dsi-fps-1-1080-2408-90 {
compatible = "mediatek,lcm-dsi-fps-1-1080-2408-90";
lcm-params-dsi-voltage;
lcm-params-dsi-fake = <0>;
/* drm-display-mode */
lcm-params-dsi-vrefresh = <90>;
lcm-params-dsi-vertical-sync-active = <4>;
lcm-params-dsi-vertical-backporch = <16>;
lcm-params-dsi-vertical-frontporch = <1510>;
lcm-params-dsi-vertical-active-line = <2408>;
lcm-params-dsi-horizontal-sync-active = <4>;
lcm-params-dsi-horizontal-backporch = <16>;
lcm-params-dsi-horizontal-frontporch = <72>;
lcm-params-dsi-horizontal-active-pixel = <1080>;
lcm-params-dsi-pixel-clock = <414831>;
lcm-params-dsi-hskew;
lcm-params-dsi-vscan;
/* mtk-panel-params */
lcm-params-dsi-pll-clock = <570>;
lcm-params-dsi-data-rate = <1140>;
lcm-params-dsi-vfp-for-low-power = <2546>;
lcm-params-dsi-ssc-enable;
lcm-params-dsi-ssc-range;
lcm-params-dsi-lcm-color-mode;
lcm-params-dsi-min-luminance;
lcm-params-dsi-average-luminance;
lcm-params-dsi-max-luminance;
lcm-params-dsi-round-corner-en = <0>;
lcm-params-dsi-corner-pattern-height;
lcm-params-dsi-corner-pattern-height-bot;
lcm-params-dsi-corner-pattern-tp-size;
lcm-params-dsi-corner-pattern-tp-size-left;
lcm-params-dsi-corner-pattern-tp-size-right;
lcm-params-dsi-corner-pattern-name;
lcm-params-dsi-physical-width-um = <68364>;
lcm-params-dsi-physical-height-um = <152300>;
lcm-params-dsi-output-mode =
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
lcm-params-dsi-lcm-cmd-if;
lcm-params-dsi-hbm-en-time;
lcm-params-dsi-hbm-dis-time;
lcm-params-dsi-lcm-index;
lcm-params-dsi-wait-sof-before-dec-vfp;
lcm-params-dsi-doze-delay;
lcm-params-dsi-lfr-enable = <1>;
lcm-params-dsi-lfr-minimum-fps = <60>;
lcm-params-dsi-msync2-enable;
lcm-params-dsi-max-vfp-for-msync;
/* lane swap */
lcm-params-dsi-lane-swap-en;
lcm-params-dsi-lane-swap0;
lcm-params-dsi-lane-swap1;
/* esd check table */
lcm-params-dsi-cust-esd-check = <1>;
lcm-params-dsi-esd-check-enable = <1>;
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
lcm-params-dsi-lcm-esd-check-table1;
lcm-params-dsi-lcm-esd-check-table2;
lcm-params-dsi-dsc-params-1-1080-2408-90 {
compatible =
"mediatek,lcm-params-dsi-dsc-params";
lcm-params-dsi-dsc-enable = <1>;
lcm-params-dsi-dsc-enable-lk = <0>;
lcm-params-dsi-dsc-ver = <17>;
lcm-params-dsi-dsc-slice-mode = <1>;
lcm-params-dsi-dsc-rgb-swap = <0>;
lcm-params-dsi-dsc-cfg = <34>;
lcm-params-dsi-dsc-rct-on = <1>;
lcm-params-dsi-dsc-bit-per-channel = <8>;
lcm-params-dsi-dsc-line-buf-depth = <9>;
lcm-params-dsi-dsc-bp-enable = <1>;
lcm-params-dsi-dsc-bit-per-pixel = <128>;
lcm-params-dsi-dsc-pic-height = <2408>;
lcm-params-dsi-dsc-pic-width = <1080>;
lcm-params-dsi-dsc-slice-height = <8>;
lcm-params-dsi-dsc-slice-width = <540>;
lcm-params-dsi-dsc-chunk-size = <540>;
lcm-params-dsi-dsc-xmit-delay = <170>;
lcm-params-dsi-dsc-dec-delay = <526>;
lcm-params-dsi-dsc-scale-value = <32>;
lcm-params-dsi-dsc-increment-interval = <43>;
lcm-params-dsi-dsc-decrement-interval = <7>;
lcm-params-dsi-dsc-line-bpg-offset = <12>;
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
lcm-params-dsi-dsc-initial-offset = <6144>;
lcm-params-dsi-dsc-final-offset = <7072>;
lcm-params-dsi-dsc-flatness-minqp = <3>;
lcm-params-dsi-dsc-flatness-maxqp = <12>;
lcm-params-dsi-dsc-rc-model-size = <8192>;
lcm-params-dsi-dsc-rc-edge-factor = <6>;
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
};
lcm-params-dsi-phy-timcon-params-1-1080-2408-90 {
compatible =
"mediatek,lcm-params-dsi-phy-timcon";
lcm-params-dsi-phy-timcon-hs-trail;
lcm-params-dsi-phy-timcon-hs-prpr;
lcm-params-dsi-phy-timcon-hs-zero;
lcm-params-dsi-phy-timcon-lpx;
lcm-params-dsi-phy-timcon-ta-get;
lcm-params-dsi-phy-timcon-ta-sure;
lcm-params-dsi-phy-timcon-ta-go;
lcm-params-dsi-phy-timcon-da-hs-exit;
lcm-params-dsi-phy-timcon-clk-trail;
lcm-params-dsi-phy-timcon-cont-det;
lcm-params-dsi-phy-timcon-da-hs-sync;
lcm-params-dsi-phy-timcon-clk-zero;
lcm-params-dsi-phy-timcon-clk-prpr;
lcm-params-dsi-phy-timcon-clk-exit;
lcm-params-dsi-phy-timcon-clk-post;
/* lk support */
lcm-params-dsi-phy-timcon-lk-hs-trail;
lcm-params-dsi-phy-timcon-lk-hs-zero;
lcm-params-dsi-phy-timcon-lk-hs-prpr;
lcm-params-dsi-phy-timcon-lk-lpx;
lcm-params-dsi-phy-timcon-lk-ta-sack;
lcm-params-dsi-phy-timcon-lk-ta-get;
lcm-params-dsi-phy-timcon-lk-ta-sure;
lcm-params-dsi-phy-timcon-lk-ta-go;
lcm-params-dsi-phy-timcon-lk-clk-trail;
lcm-params-dsi-phy-timcon-lk-clk-zero;
lcm-params-dsi-phy-timcon-lk-lpx-wait;
lcm-params-dsi-phy-timcon-lk-cont-det;
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
};
lcm-params-dsi-dyn-params-1-1080-2408-90 {
compatible =
"mediatek,lcm-params-dsi-dyn";
lcm-params-dsi-dyn-switch-en = <0>;
lcm-params-dsi-dyn-pll-clk;
lcm-params-dsi-dyn-data-rate = <1140>;
lcm-params-dsi-dyn-vsa;
lcm-params-dsi-dyn-vbp;
lcm-params-dsi-dyn-vfp = <879>;
lcm-params-dsi-dyn-vfp-lp-dyn;
lcm-params-dsi-dyn-vac;
lcm-params-dsi-dyn-hsa;
lcm-params-dsi-dyn-hbp;
lcm-params-dsi-dyn-hfp;
lcm-params-dsi-dyn-hac;
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
};
lcm-params-dsi-dyn-fps-params-1-1080-2408-90 {
compatible =
"mediatek,lcm-params-dsi-dyn-fps";
lcm-params-dsi-dyn-fps-switch-en = <0>;
lcm-params-dsi-dyn-fps-vact-timing-fps = <90>;
lcm-params-dsi-dyn-fps-data-rate;
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
};
};
lcm-params-dsi-fps-0-1080-2408-144 {
compatible = "mediatek,lcm-dsi-fps-0-1080-2408-144";
lcm-params-dsi-voltage;
lcm-params-dsi-fake = <0>;
/* drm-display-mode */
lcm-params-dsi-vrefresh = <144>;
lcm-params-dsi-vertical-sync-active = <4>;
lcm-params-dsi-vertical-backporch = <16>;
lcm-params-dsi-vertical-frontporch = <30>;
lcm-params-dsi-vertical-active-line = <2408>;
lcm-params-dsi-horizontal-sync-active = <4>;
lcm-params-dsi-horizontal-backporch = <16>;
lcm-params-dsi-horizontal-frontporch = <72>;
lcm-params-dsi-horizontal-active-pixel = <1080>;
lcm-params-dsi-pixel-clock = <414831>;
lcm-params-dsi-hskew;
lcm-params-dsi-vscan;
/* mtk-panel-params */
lcm-params-dsi-pll-clock = <570>;
lcm-params-dsi-data-rate = <1140>;
lcm-params-dsi-vfp-for-low-power = <2546>;
lcm-params-dsi-ssc-enable;
lcm-params-dsi-ssc-range;
lcm-params-dsi-lcm-color-mode;
lcm-params-dsi-min-luminance;
lcm-params-dsi-average-luminance;
lcm-params-dsi-max-luminance;
lcm-params-dsi-round-corner-en = <0>;
lcm-params-dsi-corner-pattern-height;
lcm-params-dsi-corner-pattern-height-bot;
lcm-params-dsi-corner-pattern-tp-size;
lcm-params-dsi-corner-pattern-tp-size-left;
lcm-params-dsi-corner-pattern-tp-size-right;
lcm-params-dsi-corner-pattern-name;
lcm-params-dsi-physical-width-um = <68364>;
lcm-params-dsi-physical-height-um = <152300>;
lcm-params-dsi-output-mode =
<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
lcm-params-dsi-lcm-cmd-if;
lcm-params-dsi-hbm-en-time;
lcm-params-dsi-hbm-dis-time;
lcm-params-dsi-lcm-index;
lcm-params-dsi-wait-sof-before-dec-vfp;
lcm-params-dsi-doze-delay;
lcm-params-dsi-lfr-enable = <1>;
lcm-params-dsi-lfr-minimum-fps = <60>;
lcm-params-dsi-msync2-enable;
lcm-params-dsi-max-vfp-for-msync;
/* lane swap */
lcm-params-dsi-lane-swap-en;
lcm-params-dsi-lane-swap0;
lcm-params-dsi-lane-swap1;
/* esd check table */
lcm-params-dsi-cust-esd-check = <1>;
lcm-params-dsi-esd-check-enable = <1>;
lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
lcm-params-dsi-lcm-esd-check-table1;
lcm-params-dsi-lcm-esd-check-table2;
/* fpga support */
lcm-params-dsi-fpga-params-0-1080-2408-144 {
compatible = "mediatek,lcm-dsi-fpga-params";
lcm-params-dsi-lk-pll-div = <0 0>;
lcm-params-dsi-lk-fbk-div = <1>;
};
/* lk support */
lcm-params-dsi-lk-params-0-1080-2408-144 {
compatible = "mediatek,lcm-dsi-lk-params";
lcm-params-dsi-lk-mode =
<MTK_LK_SYNC_PULSE_VDO_MODE>;
lcm-params-dsi-lk-switch-mode = <MTK_LK_CMD_MODE>;
lcm-params-dsi-lk-switch-mode-enable = <0>;
lcm-params-dsi-lk-dsi-wmem-conti;
lcm-params-dsi-lk-dsi-rmem-conti;
lcm-params-dsi-lk-vc-num;
lcm-params-dsi-lk-data-format =
<MTK_LCM_COLOR_ORDER_RGB>,
<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
<MTK_LCM_DSI_PADDING_ON_LSB>,
<MTK_LCM_DSI_FORMAT_RGB888>;
lcm-params-dsi-lk-intermediat-buffer-num;
lcm-params-dsi-lk-ps =
<MTK_LCM_PACKED_PS_24BIT_RGB888>;
lcm-params-dsi-lk-word-count;
lcm-params-dsi-lk-packet-size = <256>;
lcm-params-dsi-lk-horizontal-blanking-pixel;
lcm-params-dsi-lk-bllp;
lcm-params-dsi-lk-line-byte;
lcm-params-dsi-lk-horizontal-sync-active-byte;
lcm-params-dsi-lk-horizontal-backporch-byte;
lcm-params-dsi-lk-horizontal-frontporch-byte;
lcm-params-dsi-lk-rgb-byte;
lcm-params-dsi-lk-horizontal-sync-active-word-count;
lcm-params-dsi-lk-horizontal-backporch-word-count;
lcm-params-dsi-lk-horizontal-frontporch-word-count;
lcm-params-dsi-lk-pll-select;
lcm-params-dsi-lk-pll-div;
lcm-params-dsi-lk-fbk-div;
lcm-params-dsi-lk-fbk-sel;
lcm-params-dsi-lk-rg = <0 0 0>;
lcm-params-dsi-lk-dsi-clock;
lcm-params-dsi-lk-ssc-disable = <1>;
lcm-params-dsi-lk-ssc-range;
lcm-params-dsi-lk-compatibility-for-nvk;
lcm-params-dsi-lk-cont-clock;
lcm-params-dsi-lk-ufoe-enable;
lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
lcm-params-dsi-lk-edp-panel;
lcm-params-dsi-lk-lcm-int-te-monitor;
lcm-params-dsi-lk-lcm-int-te-period;
lcm-params-dsi-lk-lcm-ext-te-monitor;
lcm-params-dsi-lk-lcm-ext-te-period;
lcm-params-dsi-lk-noncont-clock;
lcm-params-dsi-lk-noncont-clock-period;
lcm-params-dsi-lk-clk-lp-per-line-enable = <0>;
lcm-params-dsi-lk-dual-dsi-type;
lcm-params-dsi-lk-mixmode-enable;
lcm-params-dsi-lk-mixmode-mipi-clock;
lcm-params-dsi-lk-pwm-fps;
lcm-params-dsi-lk-pll-clock-lp;
lcm-params-dsi-lk-ulps-sw-enable;
lcm-params-dsi-lk-null-packet-en;
lcm-params-dsi-lk-vact-fps = <144>;
lcm-params-dsi-lk-send-frame-enable;
lcm-params-dsi-lk-lfr-enable;
lcm-params-dsi-lk-lfr-mode;
lcm-params-dsi-lk-lfr-type;
lcm-params-dsi-lk-lfr-skip-num;
lcm-params-dsi-lk-ext-te-edge;
lcm-params-dsi-lk-eint-disable;
lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
};
lcm-params-dsi-dsc-params-0-1080-2408-144 {
compatible =
"mediatek,lcm-params-dsi-dsc-params";
lcm-params-dsi-dsc-enable = <1>;
lcm-params-dsi-dsc-enable-lk = <1>;
lcm-params-dsi-dsc-ver = <17>;
lcm-params-dsi-dsc-slice-mode = <1>;
lcm-params-dsi-dsc-rgb-swap = <0>;
lcm-params-dsi-dsc-cfg = <34>;
lcm-params-dsi-dsc-rct-on = <1>;
lcm-params-dsi-dsc-bit-per-channel = <8>;
lcm-params-dsi-dsc-line-buf-depth = <9>;
lcm-params-dsi-dsc-bp-enable = <1>;
lcm-params-dsi-dsc-bit-per-pixel = <128>;
lcm-params-dsi-dsc-pic-height = <2408>;
lcm-params-dsi-dsc-pic-width = <1080>;
lcm-params-dsi-dsc-slice-height = <8>;
lcm-params-dsi-dsc-slice-width = <540>;
lcm-params-dsi-dsc-chunk-size = <540>;
lcm-params-dsi-dsc-xmit-delay = <170>;
lcm-params-dsi-dsc-dec-delay = <526>;
lcm-params-dsi-dsc-scale-value = <32>;
lcm-params-dsi-dsc-increment-interval = <43>;
lcm-params-dsi-dsc-decrement-interval = <7>;
lcm-params-dsi-dsc-line-bpg-offset = <12>;
lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
lcm-params-dsi-dsc-initial-offset = <6144>;
lcm-params-dsi-dsc-final-offset = <7072>;
lcm-params-dsi-dsc-flatness-minqp = <3>;
lcm-params-dsi-dsc-flatness-maxqp = <12>;
lcm-params-dsi-dsc-rc-model-size = <8192>;
lcm-params-dsi-dsc-rc-edge-factor = <6>;
lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
};
lcm-params-dsi-phy-timcon-params-0-1080-2408-144 {
compatible =
"mediatek,lcm-params-dsi-phy-timcon";
lcm-params-dsi-phy-timcon-hs-trail;
lcm-params-dsi-phy-timcon-hs-prpr;
lcm-params-dsi-phy-timcon-hs-zero;
lcm-params-dsi-phy-timcon-lpx;
lcm-params-dsi-phy-timcon-ta-get;
lcm-params-dsi-phy-timcon-ta-sure;
lcm-params-dsi-phy-timcon-ta-go;
lcm-params-dsi-phy-timcon-da-hs-exit;
lcm-params-dsi-phy-timcon-clk-trail;
lcm-params-dsi-phy-timcon-cont-det;
lcm-params-dsi-phy-timcon-da-hs-sync;
lcm-params-dsi-phy-timcon-clk-zero;
lcm-params-dsi-phy-timcon-clk-prpr;
lcm-params-dsi-phy-timcon-clk-exit;
lcm-params-dsi-phy-timcon-clk-post;
/* lk support */
lcm-params-dsi-phy-timcon-lk-hs-trail;
lcm-params-dsi-phy-timcon-lk-hs-zero;
lcm-params-dsi-phy-timcon-lk-hs-prpr = <10>;
lcm-params-dsi-phy-timcon-lk-lpx;
lcm-params-dsi-phy-timcon-lk-ta-sack;
lcm-params-dsi-phy-timcon-lk-ta-get;
lcm-params-dsi-phy-timcon-lk-ta-sure;
lcm-params-dsi-phy-timcon-lk-ta-go;
lcm-params-dsi-phy-timcon-lk-clk-trail;
lcm-params-dsi-phy-timcon-lk-clk-zero;
lcm-params-dsi-phy-timcon-lk-lpx-wait;
lcm-params-dsi-phy-timcon-lk-cont-det;
lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
lcm-params-dsi-phy-timcon-lk-clk-hs-post;
lcm-params-dsi-phy-timcon-lk-da-hs-exit;
lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
};
lcm-params-dsi-dyn-params-0-1080-2408-144 {
compatible =
"mediatek,lcm-params-dsi-dyn";
lcm-params-dsi-dyn-switch-en = <0>;
lcm-params-dsi-dyn-pll-clk;
lcm-params-dsi-dyn-data-rate = <1140>;
lcm-params-dsi-dyn-vsa;
lcm-params-dsi-dyn-vbp;
lcm-params-dsi-dyn-vfp;
lcm-params-dsi-dyn-vfp-lp-dyn;
lcm-params-dsi-dyn-vac;
lcm-params-dsi-dyn-hsa;
lcm-params-dsi-dyn-hbp;
lcm-params-dsi-dyn-hfp;
lcm-params-dsi-dyn-hac;
lcm-params-dsi-dyn-max-vfp-for-msync-dyn;
};
lcm-params-dsi-dyn-fps-params-0-1080-2408-144 {
compatible =
"mediatek,lcm-params-dsi-dyn-fps";
lcm-params-dsi-dyn-fps-switch-en = <0>;
lcm-params-dsi-dyn-fps-vact-timing-fps = <144>;
lcm-params-dsi-dyn-fps-data-rate;
lcm-params-dsi-dyn-fps-dfps-cmd-table0;
lcm-params-dsi-dyn-fps-dfps-cmd-table1;
lcm-params-dsi-dyn-fps-dfps-cmd-table2;
lcm-params-dsi-dyn-fps-dfps-cmd-table3;
lcm-params-dsi-dyn-fps-dfps-cmd-table4;
lcm-params-dsi-dyn-fps-dfps-cmd-table5;
lcm-params-dsi-dyn-fps-dfps-cmd-table6;
lcm-params-dsi-dyn-fps-dfps-cmd-table7;
lcm-params-dsi-dyn-fps-dfps-cmd-table8;
lcm-params-dsi-dyn-fps-dfps-cmd-table9;
lcm-params-dsi-dyn-fps-dfps-cmd-table10;
lcm-params-dsi-dyn-fps-dfps-cmd-table11;
lcm-params-dsi-dyn-fps-dfps-cmd-table12;
lcm-params-dsi-dyn-fps-dfps-cmd-table13;
lcm-params-dsi-dyn-fps-dfps-cmd-table14;
lcm-params-dsi-dyn-fps-dfps-cmd-table15;
lcm-params-dsi-dyn-fps-dfps-cmd-table16;
lcm-params-dsi-dyn-fps-dfps-cmd-table17;
lcm-params-dsi-dyn-fps-dfps-cmd-table18;
lcm-params-dsi-dyn-fps-dfps-cmd-table19;
};
};
};
};
lcm-ops {
compatible = "mediatek,lcm-ops";
lcm-ops-dbi {
compatible = "mediatek,lcm-ops-dbi";
/* future reserved for dbi interfaces*/
};
lcm-ops-dpi {
compatible = "mediatek,lcm-ops-dpi";
/* future reserved for dpi interfaces*/
};
lcm-ops-dsi {
compatible = "mediatek,lcm-ops-dsi";
prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 05],
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 05],
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 05],
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 06],
[3B 03 14 2E 04 04],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 B0 00],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
[C1 89 28 00 08 00 AA 02 0E 00],
[2B 00 07 0D B7 0C B7],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 C2 1B A0],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E9 01],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF F0],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9F 0F],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 51 FF],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 24],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 55 00],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 11],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 64],
[MTK_LCM_TYPE_HEX_END];
unprepare-table =
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 28 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 32],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 10 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 96],
[MTK_LCM_TYPE_HEX_END];
set-display-on-table =
[MTK_LCM_PHASE_TYPE_HEX_START 02],
[MTK_LCM_PHASE_HEX_LK],
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
[MTK_LCM_UTIL_TYPE_HEX_TDELAY 01 c8],
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 01 29],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 64],
[MTK_LCM_PHASE_TYPE_HEX_END 02],
[MTK_LCM_PHASE_HEX_LK],
[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
[MTK_LCM_TYPE_HEX_END];
lcm-update-table = [MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
[00 00 05 39 02],
/*2a is of data[1] bit0 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2a],
/*x0-msb is of data[1] bit8 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_MSB_BIT 03 01 08 00],
/*x0-lsb is of data[1] bit16 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X0_LSB_BIT 03 01 10 00],
/*x1-msb is of data[1] bit24 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_MSB_BIT 03 01 18 00],
/*x0-lsb is of data[2] bit0 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_X1_LSB_BIT 03 02 00 00],
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 03],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
[00 00 05 39 02],
/*2b is of data[1] bit0 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_FIX_BIT 03 01 00 2b],
/*y0-msb is of data[1] bit8 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_MSB_BIT 03 01 08 00],
/*y0-lsb is of data[1] bit16 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y0_LSB_BIT 03 01 10 00],
/*y1-msb is of data[1] bit24 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_MSB_BIT 03 01 18 00],
/*y0-lsb is of data[2] bit0 */
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_Y1_LSB_BIT 03 02 00 00],
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05],
[00 00 2c 39 09],
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM_UNFORCE 00],
[MTK_LCM_TYPE_HEX_END];
set-backlight-mask = <0xfff>;
set-backlight-cmdq-table =
/* runtime input count, data id*/
[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 08],
[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 02 01 02],
[03 51 0f ff],
[MTK_LCM_TYPE_HEX_END];
set-aod-light-mask = <0xfff>;
set-aod-light-table;
ata-id-value-data;
ata-check-table;
compare-id-value-data = [55];
compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 10 05 00],
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 14],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 DA],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 f0 ff 15 00],
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 02],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 02],
[MTK_LCM_TYPE_HEX_END];
doze-enable-start-table;
doze-enable-table;
doze-disable-table;
doze-area-table;
doze-post-disp-on-table;
hbm-set-cmdq-switch-id;
hbm-set-cmdq-switch-on;
hbm-set-cmdq-switch-off;
hbm-set-cmdq-table;
/* fps switch cmd for high frame rate feature */
lcm-ops-dsi-fps-switch-after-poweron {
compatible =
"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
fps-switch-2-1080-2408-60-table;
fps-switch-1-1080-2408-90-table;
fps-switch-0-1080-2408-144-table;
};
lcm-ops-dsi-fps-switch-before-powerdown {
compatible =
"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
fps-switch-2-1080-2408-60-table;
fps-switch-1-1080-2408-90-table;
fps-switch-0-1080-2408-144-table;
};
};
};
};
};
Reference in a new issue View git blame Copy permalink