43 lines
1.3 KiB
C
43 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H
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#define __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H
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#define MT8195_SLAVE_DDR_EMI 0
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#define MT8195_MASTER_MCUSYS 1
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#define MT8195_MASTER_GPUSYS 2
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#define MT8195_MASTER_MMSYS 3
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#define MT8195_MASTER_MM_VPU 4
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#define MT8195_MASTER_MM_DISP 5
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#define MT8195_MASTER_MM_VDEC 6
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#define MT8195_MASTER_MM_VENC 7
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#define MT8195_MASTER_MM_CAM 8
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#define MT8195_MASTER_MM_IMG 9
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#define MT8195_MASTER_MM_MDP 10
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#define MT8195_MASTER_VPUSYS 11
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#define MT8195_MASTER_VPU_0 12
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#define MT8195_MASTER_VPU_1 13
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#define MT8195_MASTER_MDLASYS 14
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#define MT8195_MASTER_MDLA_0 15
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#define MT8195_MASTER_UFS 16
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#define MT8195_MASTER_PCIE_0 17
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#define MT8195_MASTER_PCIE_1 18
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#define MT8195_MASTER_USB 19
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#define MT8195_MASTER_DBGIF 20
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#define MT8195_SLAVE_HRT_DDR_EMI 21
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#define MT8195_MASTER_HRT_MMSYS 22
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#define MT8195_MASTER_HRT_MM_DISP 23
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#define MT8195_MASTER_HRT_MM_VDEC 24
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#define MT8195_MASTER_HRT_MM_VENC 25
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#define MT8195_MASTER_HRT_MM_CAM 26
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#define MT8195_MASTER_HRT_MM_IMG 27
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#define MT8195_MASTER_HRT_MM_MDP 28
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#define MT8195_MASTER_HRT_DBGIF 29
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#define MT8195_MASTER_WIFI 30
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#define MT8195_MASTER_BT 31
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#define MT8195_MASTER_NETSYS 32
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#endif
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