528 lines
16 KiB
C
528 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chuan-Wen Chen <chuan-wen.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT6835_H
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#define _DT_BINDINGS_CLK_MT6835_H
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/* TOPCKGEN */
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#define CLK_TOP_AXI_SEL 0
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#define CLK_TOP_AXIP_SEL 1
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#define CLK_TOP_AXI_U_SEL 2
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#define CLK_TOP_BUS_AXIMEM_SEL 3
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#define CLK_TOP_DISP0_SEL 4
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#define CLK_TOP_MDP0_SEL 5
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#define CLK_TOP_MMINFRA_SEL 6
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#define CLK_TOP_MMUP_SEL 7
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#define CLK_TOP_CAMTG_SEL 8
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#define CLK_TOP_CAMTG2_SEL 9
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#define CLK_TOP_CAMTG3_SEL 10
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#define CLK_TOP_CAMTG4_SEL 11
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#define CLK_TOP_UART_SEL 12
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#define CLK_TOP_SPI_SEL 13
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#define CLK_TOP_MSDC_0P_MACRO_SEL 14
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#define CLK_TOP_MSDC50_0_HCLK_SEL 15
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#define CLK_TOP_MSDC50_0_SEL 16
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#define CLK_TOP_AES_MSDCFDE_SEL 17
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#define CLK_TOP_MSDC_MACRO_SEL 18
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#define CLK_TOP_MSDC30_1_SEL 19
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#define CLK_TOP_AUDIO_SEL 20
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#define CLK_TOP_AUD_INTBUS_SEL 21
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#define CLK_TOP_DISP_PWM_SEL 22
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#define CLK_TOP_USB_TOP_SEL 23
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#define CLK_TOP_USB_XHCI_SEL 24
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#define CLK_TOP_I2C_SEL 25
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#define CLK_TOP_SENINF_SEL 26
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#define CLK_TOP_SENINF1_SEL 27
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#define CLK_TOP_SENINF2_SEL 28
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#define CLK_TOP_DXCC_SEL 29
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#define CLK_TOP_AUD_ENGEN1_SEL 30
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#define CLK_TOP_AUD_ENGEN2_SEL 31
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#define CLK_TOP_AES_UFSFDE_SEL 32
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#define CLK_TOP_U_SEL 33
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#define CLK_TOP_AUD_1_SEL 34
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#define CLK_TOP_AUD_2_SEL 35
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#define CLK_TOP_DPMAIF_MAIN_SEL 36
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#define CLK_TOP_VENC_SEL 37
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#define CLK_TOP_VDEC_SEL 38
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#define CLK_TOP_PWM_SEL 39
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#define CLK_TOP_AUDIO_H_SEL 40
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#define CLK_TOP_MCUPM_SEL 41
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#define CLK_TOP_MEM_SUB_SEL 42
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#define CLK_TOP_MEM_SUBP_SEL 43
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#define CLK_TOP_MEM_SUB_U_SEL 44
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#define CLK_TOP_AP2CONN_HOST_SEL 45
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#define CLK_TOP_MCU_ACP_SEL 46
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#define CLK_TOP_IMG1_SEL 47
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#define CLK_TOP_IPE_SEL 48
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#define CLK_TOP_CAM_SEL 49
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#define CLK_TOP_CAMTM_SEL 50
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#define CLK_TOP_MSDC_1P_RX_SEL 51
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#define CLK_TOP_NFI1X_SEL 52
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#define CLK_TOP_DBI_SEL 53
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#define CLK_TOP_MFG_REF_SEL 54
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#define CLK_TOP_EMI_546_SEL 55
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#define CLK_TOP_EMI_624_SEL 56
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#define CLK_TOP_MFG_PLL_SEL 57
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#define CLK_TOP_APLL_I2S0_MCK_SEL 58
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#define CLK_TOP_APLL_I2S1_MCK_SEL 59
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#define CLK_TOP_APLL_I2S2_MCK_SEL 60
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#define CLK_TOP_APLL_I2S3_MCK_SEL 61
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#define CLK_TOP_APLL_I2S4_MCK_SEL 62
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#define CLK_TOP_APLL_I2S5_MCK_SEL 63
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#define CLK_TOP_APLL_I2S6_MCK_SEL 64
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#define CLK_TOP_APLL_I2S7_MCK_SEL 65
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#define CLK_TOP_APLL_I2S8_MCK_SEL 66
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#define CLK_TOP_APLL_I2S9_MCK_SEL 67
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#define CLK_TOP_APLL12_CK_DIV0 68
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#define CLK_TOP_APLL12_CK_DIV1 69
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#define CLK_TOP_APLL12_CK_DIV2 70
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#define CLK_TOP_APLL12_CK_DIV3 71
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#define CLK_TOP_APLL12_CK_DIV4 72
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#define CLK_TOP_APLL12_CK_DIVB 73
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#define CLK_TOP_APLL12_CK_DIV5 74
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#define CLK_TOP_APLL12_CK_DIV6 75
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#define CLK_TOP_APLL12_CK_DIV7 76
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#define CLK_TOP_APLL12_CK_DIV8 77
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#define CLK_TOP_APLL12_CK_DIV9 78
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#define CLK_TOP_MFGPLL 79
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#define CLK_TOP_MAINPLL_D3 80
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#define CLK_TOP_MAINPLL_D4 81
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#define CLK_TOP_MAINPLL_D4_D2 82
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#define CLK_TOP_MAINPLL_D4_D4 83
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#define CLK_TOP_MAINPLL_D4_D8 84
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#define CLK_TOP_MAINPLL_D4_D16 85
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#define CLK_TOP_MAINPLL_D5 86
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#define CLK_TOP_MAINPLL_D5_D2 87
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#define CLK_TOP_MAINPLL_D5_D4 88
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#define CLK_TOP_MAINPLL_D5_D8 89
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#define CLK_TOP_MAINPLL_D6 90
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#define CLK_TOP_MAINPLL_D6_D2 91
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#define CLK_TOP_MAINPLL_D6_D4 92
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#define CLK_TOP_MAINPLL_D7 93
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#define CLK_TOP_MAINPLL_D7_D2 94
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#define CLK_TOP_MAINPLL_D7_D4 95
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#define CLK_TOP_MAINPLL_D7_D8 96
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#define CLK_TOP_MAINPLL_D9 97
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#define CLK_TOP_UNIVPLL_D4 98
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#define CLK_TOP_UNIVPLL_D4_D2 99
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#define CLK_TOP_UNIVPLL_D4_D4 100
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#define CLK_TOP_UNIVPLL_D4_D8 101
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#define CLK_TOP_UNIVPLL_D5 102
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#define CLK_TOP_UNIVPLL_D5_D2 103
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#define CLK_TOP_UNIVPLL_D5_D4 104
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#define CLK_TOP_UNIVPLL_D6 105
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#define CLK_TOP_UNIVPLL_D6_D2 106
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#define CLK_TOP_UNIVPLL_D6_D4 107
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#define CLK_TOP_UNIVPLL_D6_D8 108
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#define CLK_TOP_UNIVPLL_D7 109
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#define CLK_TOP_UNIVPLL_D7_D2 110
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#define CLK_TOP_UNIVPLL_192M 111
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#define CLK_TOP_UNIVPLL_192M_D2 112
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#define CLK_TOP_UNIVPLL_192M_D4 113
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#define CLK_TOP_UNIVPLL_192M_D8 114
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#define CLK_TOP_UNIVPLL_192M_D10 115
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#define CLK_TOP_UNIVPLL_192M_D16 116
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#define CLK_TOP_UNIVPLL_192M_D32 117
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#define CLK_TOP_APLL1 118
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#define CLK_TOP_APLL1_D2 119
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#define CLK_TOP_APLL1_D4 120
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#define CLK_TOP_APLL1_D8 121
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#define CLK_TOP_APLL2 122
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#define CLK_TOP_APLL2_D2 123
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#define CLK_TOP_APLL2_D4 124
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#define CLK_TOP_APLL2_D8 125
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#define CLK_TOP_IMGPLL 126
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#define CLK_TOP_MMPLL_D4 127
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#define CLK_TOP_MMPLL_D4_D2 128
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#define CLK_TOP_MMPLL_D5 129
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#define CLK_TOP_MMPLL_D5_D2 130
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#define CLK_TOP_MMPLL_D6 131
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#define CLK_TOP_MMPLL_D6_D2 132
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#define CLK_TOP_MMPLL_D7 133
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#define CLK_TOP_MMPLL_D9 134
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#define CLK_TOP_TVDPLL 135
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#define CLK_TOP_MSDCPLL 136
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#define CLK_TOP_MSDCPLL_D2 137
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#define CLK_TOP_CLKRTC 138
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#define CLK_TOP_TCK_26M_MX9 139
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#define CLK_TOP_F26M_CK_D2 140
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#define CLK_TOP_OSC 141
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#define CLK_TOP_OSC_D2 142
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#define CLK_TOP_OSC_D4 143
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#define CLK_TOP_OSC_D7 144
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#define CLK_TOP_OSC_D8 145
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#define CLK_TOP_OSC_D16 146
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#define CLK_TOP_OSC_D10 147
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#define CLK_TOP_ULPOSC 148
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#define CLK_TOP_F26M 149
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#define CLK_TOP_AXI 150
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#define CLK_TOP_AXIP 151
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#define CLK_TOP_DISP0 152
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#define CLK_TOP_MDP0 153
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#define CLK_TOP_MMINFRA 154
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#define CLK_TOP_UART 155
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#define CLK_TOP_SPI 156
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#define CLK_TOP_MSDC50_0_HCLK 157
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#define CLK_TOP_MSDC50_0 158
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#define CLK_TOP_AES_MSDCFDE 159
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#define CLK_TOP_MSDC30_1 160
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#define CLK_TOP_AUDIO 161
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#define CLK_TOP_AUD_INTBUS 162
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#define CLK_TOP_DISP_PWM 163
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#define CLK_TOP_USB_TOP 164
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#define CLK_TOP_USB_XHCI 165
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#define CLK_TOP_USB_FMCNT 166
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#define CLK_TOP_I2C 167
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#define CLK_TOP_AUD_ENGEN1 168
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#define CLK_TOP_AUD_ENGEN2 169
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#define CLK_TOP_DPMAIF_MAIN 170
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#define CLK_TOP_VENC 171
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#define CLK_TOP_VDEC 172
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#define CLK_TOP_AUDIO_H 173
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#define CLK_TOP_MEM_SUB 174
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#define CLK_TOP_IMG1 175
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#define CLK_TOP_IPE 176
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#define CLK_TOP_CAM 177
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#define CLK_TOP_NFI1X 178
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#define CLK_TOP_DBI 179
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#define CLK_TOP_MFG_REF 180
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#define CLK_TOP_MFG_REF_SEL_CK 181
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#define CLK_TOP_I2C_PSEUDO0 182
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#define CLK_TOP_I2C_PSEUDO1 183
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#define CLK_TOP_I2C_PSEUDO2 184
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#define CLK_TOP_I2C_PSEUDO3 185
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#define CLK_TOP_I2C_PSEUDO4 186
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#define CLK_TOP_I2C_PSEUDO5 187
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#define CLK_TOP_I2C_PSEUDO6 188
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#define CLK_TOP_I2C_PSEUDO7 189
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#define CLK_TOP_I2C_PSEUDO8 190
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#define CLK_TOP_I2C_PSEUDO9 191
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#define CLK_TOP_I2C_PSEUDO10 192
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#define CLK_TOP_I2C_PSEUDO11 193
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#define CLK_TOP_NR_CLK 194
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/* INFRACFG_AO */
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#define CLK_IFRAO_THERM 0
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#define CLK_IFRAO_CPUM 1
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#define CLK_IFRAO_CCIF1_AP 2
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#define CLK_IFRAO_CCIF1_MD 3
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#define CLK_IFRAO_CCIF_AP 4
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#define CLK_IFRAO_CCIF_MD 5
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#define CLK_IFRAO_CLDMA_BCLK 6
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#define CLK_IFRAO_CQ_DMA 7
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#define CLK_IFRAO_CCIF5_MD 8
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#define CLK_IFRAO_CCIF2_AP 9
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#define CLK_IFRAO_CCIF2_MD 10
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#define CLK_IFRAO_DPMAIF_MAIN 11
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#define CLK_IFRAO_CCIF4_AP 12
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#define CLK_IFRAO_CCIF4_MD 13
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#define CLK_IFRAO_RG_MMW_DPMAIF26M_CK 14
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#define CLK_IFRAO_RG_MEM_SUB_CK 15
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#define CLK_IFRAO_AES_TOP0 16
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#define CLK_IFRAO_I2C_DUMMY_0 17
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#define CLK_IFRAO_I2C_DUMMY_1 18
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#define CLK_IFRAO_I2C_DUMMY_2 19
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#define CLK_IFRAO_I2C_DUMMY_3 20
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#define CLK_IFRAO_I2C_DUMMY_4 21
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#define CLK_IFRAO_I2C_DUMMY_5 22
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#define CLK_IFRAO_I2C_DUMMY_6 23
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#define CLK_IFRAO_I2C_DUMMY_7 24
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#define CLK_IFRAO_I2C_DUMMY_8 25
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#define CLK_IFRAO_I2C_DUMMY_9 26
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#define CLK_IFRAO_I2C_DUMMY_10 27
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#define CLK_IFRAO_I2C_DUMMY_11 28
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#define CLK_IFRAOP_DCM_RG_FORCE 29
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#define CLK_IFRAO_NR_CLK 30
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL_LL 0
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#define CLK_APMIXED_ARMPLL_BL 1
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#define CLK_APMIXED_CCIPLL 2
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#define CLK_APMIXED_MAINPLL 3
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#define CLK_APMIXED_UNIVPLL 4
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#define CLK_APMIXED_MSDCPLL 5
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#define CLK_APMIXED_MMPLL 6
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#define CLK_APMIXED_MFGPLL 7
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#define CLK_APMIXED_TVDPLL 8
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#define CLK_APMIXED_APLL1 9
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#define CLK_APMIXED_APLL2 10
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#define CLK_APMIXED_MPLL 11
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#define CLK_APMIXED_IMGPLL 12
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#define CLK_APMIXED_NR_CLK 13
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/* NEMI_REG */
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#define CLK_NEMI_REG_BUS_MON_MODE 0
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#define CLK_NEMI_REG_NR_CLK 1
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/* PERICFG_AO */
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#define CLK_PERAOP_UART0 0
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#define CLK_PERAOP_UART1 1
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#define CLK_PERAOP_PWM_HCLK 2
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#define CLK_PERAOP_PWM_BCLK 3
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#define CLK_PERAOP_PWM_FBCLK1 4
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#define CLK_PERAOP_PWM_FBCLK2 5
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#define CLK_PERAOP_PWM_FBCLK3 6
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#define CLK_PERAOP_PWM_FBCLK4 7
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#define CLK_PERAOP_BTIF_BCLK 8
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#define CLK_PERAOP_DISP_PWM0 9
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#define CLK_PERAOP_SPI0_BCLK 10
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#define CLK_PERAOP_SPI1_BCLK 11
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#define CLK_PERAOP_SPI2_BCLK 12
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#define CLK_PERAOP_SPI3_BCLK 13
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#define CLK_PERAOP_SPI4_BCLK 14
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#define CLK_PERAOP_SPI5_BCLK 15
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#define CLK_PERAOP_SPI6_BCLK 16
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#define CLK_PERAOP_SPI7_BCLK 17
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#define CLK_PERAOP_APDMA 18
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#define CLK_PERAOP_USB_FRMCNT 19
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#define CLK_PERAOP_USB_SYS 20
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#define CLK_PERAOP_USB_XHCI 21
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#define CLK_PERAOP_MSDC1_SRC 22
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#define CLK_PERAOP_MSDC1_HCLK 23
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#define CLK_PERAOP_MSDC0_SRC 24
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#define CLK_PERAOP_MSDC0_HCLK 25
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#define CLK_PERAOP_MSDC0_AES 26
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#define CLK_PERAOP_MSDC0_XCLK 27
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#define CLK_PERAOP_MSDC0_HCLK_WRAP 28
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#define CLK_PERAOP_NFIECC_BCLK 29
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#define CLK_PERAOP_NFI_BCLK 30
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#define CLK_PERAOP_NFI_HCLK 31
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#define CLK_AUXADC_BCLK_AP 32
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#define CLK_AUXADC_BCLK_MD 33
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#define CLK_PERAO_AUDIO_SLV_CKP 34
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#define CLK_PERAO_AUDIO_MST_CKP 35
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#define CLK_PERAO_INTBUS_CKP 36
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#define CLK_PERAO_NR_CLK 37
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/* AFE */
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#define CLK_AFE_AFE 0
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#define CLK_AFE_22M 1
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#define CLK_AFE_24M 2
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#define CLK_AFE_APLL2_TUNER 3
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#define CLK_AFE_APLL_TUNER 4
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#define CLK_AFE_ADC 5
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#define CLK_AFE_DAC 6
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#define CLK_AFE_DAC_PREDIS 7
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#define CLK_AFE_TML 8
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#define CLK_AFE_NLE 9
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#define CLK_AFE_GENERAL3_ASRC 10
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#define CLK_AFE_CONNSYS_I2S_ASRC 11
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#define CLK_AFE_GENERAL1_ASRC 12
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#define CLK_AFE_GENERAL2_ASRC 13
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#define CLK_AFE_DAC_HIRES 14
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#define CLK_AFE_ADC_HIRES 15
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#define CLK_AFE_ADC_HIRES_TML 16
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#define CLK_AFE_I2S5_BCLK 17
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#define CLK_AFE_I2S1_BCLK 18
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#define CLK_AFE_I2S2_BCLK 19
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#define CLK_AFE_I2S3_BCLK 20
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#define CLK_AFE_I2S4_BCLK 21
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#define CLK_AFE_NR_CLK 22
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/* IMP_IIC_WRAP_C */
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#define CLK_IMPC_AP_CLOCK_I2C10 0
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#define CLK_IMPC_AP_CLOCK_I2C11 1
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#define CLK_IMPC_NR_CLK 2
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/* IMP_IIC_WRAP_WS */
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#define CLK_IMPWS_AP_CLOCK_I2C3 0
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#define CLK_IMPWS_AP_CLOCK_I2C5 1
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#define CLK_IMPWS_NR_CLK 2
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/* IMP_IIC_WRAP_S */
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#define CLK_IMPS_AP_CLOCK_I2C1 0
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#define CLK_IMPS_AP_CLOCK_I2C6 1
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#define CLK_IMPS_AP_CLOCK_I2C7 2
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#define CLK_IMPS_AP_CLOCK_I2C8 3
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#define CLK_IMPS_NR_CLK 4
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/* IMP_IIC_WRAP_EN */
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#define CLK_IMPEN_AP_CLOCK_I2C0 0
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#define CLK_IMPEN_AP_CLOCK_I2C2 1
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#define CLK_IMPEN_AP_CLOCK_I2C4 2
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#define CLK_IMPEN_AP_CLOCK_I2C9 3
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#define CLK_IMPEN_NR_CLK 4
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/* MFG_TOP_CONFIG */
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#define CLK_MFGCFG_BG3D 0
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#define CLK_MFGCFG_NR_CLK 1
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/* DISPSYS_CONFIG */
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#define CLK_MM_DISP_MUTEX0 0
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#define CLK_MM_DISP_OVL0 1
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#define CLK_MM_DISP_FAKE_ENG0 2
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#define CLK_MM_INLINEROT0 3
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#define CLK_MM_DISP_WDMA0 4
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#define CLK_MM_DISP_FAKE_ENG1 5
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#define CLK_MM_DISP_DBI0 6
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#define CLK_MM_DISP_OVL0_2L_NW 7
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#define CLK_MM_DISP_RDMA0 8
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#define CLK_MM_DISP_RDMA1 9
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#define CLK_MM_DISP_DLI_ASYNC0 10
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#define CLK_MM_DISP_DLI_ASYNC1 11
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#define CLK_MM_DISP_DLI_ASYNC2 12
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#define CLK_MM_DISP_DLO_ASYNC0 13
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#define CLK_MM_DISP_DLO_ASYNC1 14
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#define CLK_MM_DISP_DLO_ASYNC2 15
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#define CLK_MM_DISP_RSZ0 16
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#define CLK_MM_DISP_COLOR0 17
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#define CLK_MM_DISP_CCORR0 18
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#define CLK_MM_DISP_AAL0 19
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#define CLK_MM_DISP_GAMMA0 20
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#define CLK_MM_DISP_POSTMASK0 21
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#define CLK_MM_DISP_DITHER0 22
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#define CLK_MM_DISP_DSC_WRAP0 23
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#define CLK_MM_DISP_DUMMY_MOD_B0 24
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#define CLK_MM_DISP_DSI0 25
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#define CLK_MM_DISP_DP_INTF0 26
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#define CLK_MM_APB_BUS 27
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#define CLK_MM_DISP_TDSHP0 28
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#define CLK_MM_DISP_C3D0 29
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#define CLK_MM_DISP_Y2R0 30
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#define CLK_MM_MDP_AAL0 31
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#define CLK_MM_DISP_CHIST0 32
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#define CLK_MM_DISP_CHIST1 33
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#define CLK_MM_DISP_OVL0_2L 34
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#define CLK_MM_DLI_ASYNC3 35
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#define CLK_MM_DLO_ASYNC3 36
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#define CLK_MM_DUMMY_MOD_B1 37
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#define CLK_MM_DISP_OVL1_2L 38
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#define CLK_MM_DUMMY_MOD_B2 39
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#define CLK_MM_DUMMY_MOD_B3 40
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#define CLK_MM_DUMMY_MOD_B4 41
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#define CLK_MM_DISP_OVL1_2L_NW 42
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#define CLK_MM_DUMMY_MOD_B5 43
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#define CLK_MM_DUMMY_MOD_B6 44
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#define CLK_MM_DUMMY_MOD_B7 45
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#define CLK_MM_SMI_IOMMU 46
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#define CLK_MM_DISP_DSI 47
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#define CLK_MM_DISP_DBPI 48
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#define CLK_MM_DISP_HRT_URGENT 49
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#define CLK_MM_NR_CLK 50
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/* IMGSYS1 */
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#define CLK_IMGSYS1_LARB9 0
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#define CLK_IMGSYS1_DIP 1
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#define CLK_IMGSYS1_GALS 2
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#define CLK_IMGSYS1_NR_CLK 3
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/* VDEC_GCON_BASE */
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#define CLK_VDE2_LARB1_CKEN 0
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#define CLK_VDE2_VDEC_CKEN 1
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#define CLK_VDE2_VDEC_ACTIVE 2
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#define CLK_VDE2_VDEC_CKEN_ENG 3
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#define CLK_VDE2_NR_CLK 4
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/* VENC_GCON */
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#define CLK_VEN1_CKE0_LARB 0
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#define CLK_VEN1_CKE1_VENC 1
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#define CLK_VEN1_CKE2_JPGENC 2
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#define CLK_VEN1_NR_CLK 3
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/* VLP_CKSYS */
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#define CLK_VLP_CK_SCP_SEL 0
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#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1
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#define CLK_VLP_CK_SPMI_P_MST_SEL 2
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#define CLK_VLP_CK_DVFSRC_SEL 3
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#define CLK_VLP_CK_PWM_VLP_SEL 4
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#define CLK_VLP_CK_AXI_VLP_SEL 5
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#define CLK_VLP_CK_DBGAO_26M_SEL 6
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#define CLK_VLP_CK_SYSTIMER_26M_SEL 7
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#define CLK_VLP_CK_SSPM_SEL 8
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#define CLK_VLP_CK_SSPM_F26M_SEL 9
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#define CLK_VLP_CK_SRCK_SEL 10
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#define CLK_VLP_CK_SRAMRC_SEL 11
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#define CLK_VLP_CK_SCP_SPI_SEL 12
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#define CLK_VLP_CK_SCP_IIC_SEL 13
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#define CLK_VLP_CK_NR_CLK 14
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/* SCP_IIC */
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#define CLK_SCP_IIC_AP_CLOCK_I2C0 0
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#define CLK_SCP_IIC_AP_CLOCK_I2C1 1
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#define CLK_SCP_IIC_AP_CLOCK_I2C2 2
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#define CLK_SCP_IIC_AP_CLOCK_I2C3 3
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#define CLK_SCP_IIC_AP_CLOCK_I2C4 4
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#define CLK_SCP_IIC_AP_CLOCK_I2C5 5
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#define CLK_SCP_IIC_AP_CLOCK_I2C6 6
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#define CLK_SCP_IIC_NR_CLK 7
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/* CAMSYS_MAIN */
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#define CLK_CAM_M_LARB13 0
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#define CLK_CAM_M_LARB14 1
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#define CLK_CAM_M_CAM 2
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#define CLK_CAM_M_CAMTG 3
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#define CLK_CAM_M_SENINF 4
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#define CLK_CAM_M_CAMSV1 5
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#define CLK_CAM_M_CAMSV2 6
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#define CLK_CAM_M_CAMSV3 7
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#define CLK_CAM_M_FAKE_ENG 8
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#define CLK_CAM_M_CAM2MM_GALS 9
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#define CLK_CAM_M_NR_CLK 10
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/* CAM_SUB1_BUS */
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#define CLK_CAM_SUB1_BUS_CAM_SUBA 0
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#define CLK_CAM_SUB1_BUS_NR_CLK 1
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/* CAM_SUB0_BUS */
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#define CLK_CAM_SUB0_BUS_CAM_SUBB 0
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#define CLK_CAM_SUB0_BUS_NR_CLK 1
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/* CAMSYS_RAWA */
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#define CLK_CAM_RA_LARBX 0
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#define CLK_CAM_RA_CAM 1
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#define CLK_CAM_RA_CAMTG 2
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#define CLK_CAM_RA_NR_CLK 3
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/* CAMSYS_RAWB */
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#define CLK_CAM_RB_LARBX 0
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#define CLK_CAM_RB_CAM 1
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#define CLK_CAM_RB_CAMTG 2
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#define CLK_CAM_RB_NR_CLK 3
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/* IPESYS */
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#define CLK_IPE_LARB19 0
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#define CLK_IPE_LARB20 1
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#define CLK_IPE_SMI_SUBCOM 2
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#define CLK_IPE_FD 3
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#define CLK_IPE_FE 4
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#define CLK_IPE_RSC 5
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#define CLK_IPE_GALS 6
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#define CLK_IPE_NR_CLK 7
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/* SRAMRC_APB */
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#define CLK_SRAMRC_APB_SRAMRC_EN 0
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#define CLK_SRAMRC_APB_NR_CLK 1
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/* MMINFRA_CONFIG */
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#define CLK_MMINFRA_GCE_D 0
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#define CLK_MMINFRA_GCE_M 1
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#define CLK_MMINFRA_GCE_26M 2
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#define CLK_MMINFRA_CONFIG_NR_CLK 3
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/* MDPSYS_CONFIG */
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#define CLK_MDP_MUTEX0 0
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#define CLK_MDP_APB_BUS 1
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#define CLK_MDP_SMI0 2
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#define CLK_MDP_RDMA0 3
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#define CLK_MDP_FG0 4
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#define CLK_MDP_HDR0 5
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#define CLK_MDP_AAL0 6
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#define CLK_MDP_RSZ0 7
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#define CLK_MDP_TDSHP0 8
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#define CLK_MDP_COLOR0 9
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#define CLK_MDP_WROT0 10
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#define CLK_MDP_FAKE_ENG0 11
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#define CLK_MDP_DLI_ASYNC0 12
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#define CLK_MDP_DLI_ASYNC1 13
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#define CLK_MDP_RSZ2 14
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#define CLK_MDP_WROT2 15
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#define CLK_MDP_FMM_IMG_DL_ASYNC0 16
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#define CLK_MDP_FMM_IMG_DL_ASYNC1 17
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#define CLK_MDP_FIMG_IMG_DL_ASYNC0 18
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#define CLK_MDP_FIMG_IMG_DL_ASYNC1 19
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#define CLK_MDP_NR_CLK 20
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#endif /* _DT_BINDINGS_CLK_MT6835_H */
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