156 lines
4 KiB
C
156 lines
4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __THERMAL_INTERFACE_H__
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#define __THERMAL_INTERFACE_H__
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#define CPU_TEMP_OFFSET (0)
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#define CPU_HEADROOM_OFFSET (0x20)
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#define CPU_HEADROOM_RATIO_OFFSET (0x40)
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#define CPU_PREDICT_TEMP_OFFSET (0x60)
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#define AP_NTC_HEADROOM_OFFSET (0x80)
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#define TPCB_OFFSET (0x84)
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#define TARGET_TPCB_OFFSET (0x88)
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#define SPORTS_MODE_ENABLE (0x90)
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#define VTSKIN (0x94)
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#define TTJ_OFFSET (0x100)
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#define POWER_BUDGET_OFFSET (0x110)
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#define CPU_MIN_OPP_HINT_OFFSET (0x120)
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#define CPU_ACTIVE_BITMASK_OFFSET (0x130)
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#define CPU_JATM_SUSPEND_OFFSET (0x140)
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#define GPU_JATM_SUSPEND_OFFSET (0x144)
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#define MIN_THROTTLE_FREQ_OFFSET (0x14C)
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#define GPU_TEMP_OFFSET (0x180)
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#define APU_TEMP_OFFSET (0x190)
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#define EMUL_TEMP_OFFSET (0x1B0)
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#define CPU_LIMIT_FREQ_OFFSET (0x200)
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#define CPU_CUR_FREQ_OFFSET (0x210)
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#define CPU_MAX_TEMP_OFFSET (0x220)
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#define CPU_LIMIT_OPP_OFFSET (0x260)
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#define CPU_ATC_OFFSET (0x280)
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#define CPU_ATC20_OFFSET (0x2E0)
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#define GPU_ATC_OFFSET (0x2C8)
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#define APU_ATC_OFFSET (0x2D4)
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#define CPU_ATC_NUM (17)
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#define CPU_ATC20_NUM (7)
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#define GPU_ATC_NUM (3)
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#define APU_ATC_NUM (1)
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#define UTC_COUNT_OFFSET (0x27C)
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#define INFOB_OFFSET (0x2C4)
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#define REBOOT_TEMPERATURE_ADDR_OFFSET (0x330)
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#define GPU_COOLER_BASE (0x3A0)
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#define CPU_COOLER_BASE (0x3D0)
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#define COLD_INTERRUPT_ENABLE_OFFSET (0x334)
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#define APU_MBOX_TTJ_OFFSET (0x700)
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#define APU_MBOX_PB_OFFSET (0x704)
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#define APU_MBOX_TEMP_OFFSET (0x708)
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#define APU_MBOX_LIMIT_OPP_OFFSET (0x70C)
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#define APU_MBOX_CUR_OPP_OFFSET (0x710)
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#define APU_MBOX_EMUL_TEMP_OFFSET (0x714)
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#define APU_MBOX_ATC_MAX_TTJ_ADDR (0x718)
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struct headroom_info {
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int temp;
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int predict_temp;
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int headroom;
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int ratio;
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};
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enum headroom_id {
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/* SoC Tj */
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SOC_CPU0,
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SOC_CPU1,
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SOC_CPU2,
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SOC_CPU3,
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SOC_CPU4,
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SOC_CPU5,
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SOC_CPU6,
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SOC_CPU7,
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/* PCB */
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PCB_AP,
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NR_HEADROOM_ID
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};
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enum ttj_user {
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JATM_OFF = -1,
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CATM,
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JATM_ON,
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NR_TTJ_USER
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};
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struct ttj_info {
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int jatm_on;
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unsigned int catm_cpu_ttj;
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unsigned int catm_gpu_ttj;
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unsigned int catm_apu_ttj;
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unsigned int cpu_max_ttj;
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unsigned int gpu_max_ttj;
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unsigned int apu_max_ttj;
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unsigned int min_ttj;
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};
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struct frs_info {
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int enable;
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int activated;
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int pid;
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int target_fps;
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int diff;
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int tpcb;
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int tpcb_slope;
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int ap_headroom;
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int n_sec_to_ttpcb;
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int frs_target_fps;
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int real_fps;
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int target_tpcb;
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int ptime;
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};
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#define MAX_MD_NAME_LENGTH (20)
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struct md_thermal_sensor_t {
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int id;
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char sensor_name[MAX_MD_NAME_LENGTH];
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int cur_temp;
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};
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struct md_thermal_actuator_t {
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int id;
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char actuator_name[MAX_MD_NAME_LENGTH];
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int cur_status;
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int max_status;
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};
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struct md_info {
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int sensor_num;
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struct md_thermal_sensor_t *sensor_info;
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int md_autonomous_ctrl;
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int actuator_num;
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struct md_thermal_actuator_t *actuator_info;
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};
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extern void update_ap_ntc_headroom(int temp, int polling_interval);
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extern int get_thermal_headroom(enum headroom_id id);
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extern int set_cpu_min_opp(int gear, int opp);
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extern int set_cpu_active_bitmask(int mask);
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extern int get_cpu_temp(int cpu_id);
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extern void set_ttj(int user);
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extern void write_jatm_suspend(int jatm_suspend);
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extern int get_jatm_suspend(void);
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extern int get_catm_ttj(void);
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extern int get_catm_min_ttj(void);
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extern int set_reboot_temperature(int temp);
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extern int set_cold_interrupt_enable_addr(int val);
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#if IS_ENABLED(CONFIG_MTK_THERMAL_INTERFACE)
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extern void __iomem *thermal_csram_base;
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extern void __iomem *thermal_apu_mbox_base;
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extern struct frs_info frs_data;
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#else
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void __iomem *thermal_csram_base;
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void __iomem *thermal_apu_mbox_base;
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struct frs_info frs_data;
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#endif
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#endif
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