490 lines
12 KiB
C
490 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef _UFS_MEDIATEK_H
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#define _UFS_MEDIATEK_H
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#include <linux/bitops.h>
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#include <linux/pm_qos.h>
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#include <linux/of_device.h>
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#include "ufs.h"
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#include "ufshci.h"
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#include "ufshcd.h"
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#ifdef CONFIG_UFSFEATURE
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#include "ufsfeature.h"
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#endif
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/*
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* Vendor specific UFSHCI Registers
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*/
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#define REG_UFS_XOUFS_CTRL 0x140
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#define REG_UFS_REFCLK_CTRL 0x144
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#define REG_UFS_EXTREG 0x2100
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#define REG_UFS_MPHYCTRL 0x2200
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#define REG_UFS_MTK_IP_VER 0x2240
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#define REG_UFS_REJECT_MON 0x22AC
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#define REG_UFS_AH8E_MON 0x22B0
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#define REG_UFS_AH8X_MON 0x22B4
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#define REG_UFS_DEBUG_SEL 0x22C0
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#define REG_UFS_PROBE 0x22C8
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#define REG_UFS_DEBUG_SEL_B0 0x22D0
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#define REG_UFS_DEBUG_SEL_B1 0x22D4
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#define REG_UFS_DEBUG_SEL_B2 0x22D8
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#define REG_UFS_DEBUG_SEL_B3 0x22DC
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/*
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* Should define in unipro.h
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*/
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#define PA_TXHSG1SYNCLENGTH 0x1552
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#define PA_TXHSG2SYNCLENGTH 0x1554
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#define PA_TXHSG3SYNCLENGTH 0x1556
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#define PA_TXHSG4SYNCLENGTH 0x15D0
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#define PA_TXHSG5SYNCLENGTH 0x15D6
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#define TX_HS_EQUALIZER_SETTING 0x0037
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/*
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* Details of UIC Errors
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*/
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static const u8 *ufs_uic_err_str[] = {
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"PHY Adapter Layer",
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"Data Link Layer",
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"Network Link Layer",
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"Transport Link Layer",
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"DME"
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};
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static const u8 *ufs_uic_pa_err_str[] = {
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"PHY error on Lane 0",
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"PHY error on Lane 1",
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"PHY error on Lane 2",
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"PHY error on Lane 3",
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"Generic PHY Adapter Error. This should be the LINERESET indication"
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};
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static const u8 *ufs_uic_dl_err_str[] = {
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"NAC_RECEIVED",
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"TCx_REPLAY_TIMER_EXPIRED",
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"AFCx_REQUEST_TIMER_EXPIRED",
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"FCx_PROTECTION_TIMER_EXPIRED",
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"CRC_ERROR",
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"RX_BUFFER_OVERFLOW",
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"MAX_FRAME_LENGTH_EXCEEDED",
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"WRONG_SEQUENCE_NUMBER",
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"AFC_FRAME_SYNTAX_ERROR",
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"NAC_FRAME_SYNTAX_ERROR",
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"EOF_SYNTAX_ERROR",
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"FRAME_SYNTAX_ERROR",
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"BAD_CTRL_SYMBOL_TYPE",
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"PA_INIT_ERROR (FATAL ERROR)",
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"PA_ERROR_IND_RECEIVED",
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"PA_INIT (3.0 FATAL ERROR)"
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};
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/*
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* Ref-clk control
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*
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* Values for register REG_UFS_REFCLK_CTRL
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*/
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#define REFCLK_RELEASE 0x0
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#define REFCLK_REQUEST BIT(0)
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#define REFCLK_ACK BIT(1)
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#define REFCLK_REQ_TIMEOUT_US 3000
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/*
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* Other attributes
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*/
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#define VS_DEBUGCLOCKENABLE 0xD0A1
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#define VS_SAVEPOWERCONTROL 0xD0A6
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#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
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/*
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* Vendor specific link state
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*/
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enum {
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VS_LINK_DISABLED = 0,
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VS_LINK_DOWN = 1,
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VS_LINK_UP = 2,
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VS_LINK_HIBERN8 = 3,
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VS_LINK_LOST = 4,
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VS_LINK_CFG = 5,
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};
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/*
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* Vendor specific host controller state
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*/
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enum {
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VS_HCE_RESET = 0,
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VS_HCE_BASE = 1,
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VS_HCE_OOCPR_WAIT = 2,
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VS_HCE_DME_RESET = 3,
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VS_HCE_MIDDLE = 4,
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VS_HCE_DME_ENABLE = 5,
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VS_HCE_DEFAULTS = 6,
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VS_HIB_IDLEEN = 7,
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VS_HIB_ENTER = 8,
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VS_HIB_ENTER_CONF = 9,
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VS_HIB_MIDDLE = 10,
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VS_HIB_WAITTIMER = 11,
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VS_HIB_EXIT_CONF = 12,
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VS_HIB_EXIT = 13,
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};
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/*
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* VS_DEBUGCLOCKENABLE
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*/
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enum {
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TX_SYMBOL_CLK_REQ_FORCE = 5,
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};
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/*
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* VS_SAVEPOWERCONTROL
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*/
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enum {
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RX_SYMBOL_CLK_GATE_EN = 0,
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SYS_CLK_GATE_EN = 2,
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TX_CLK_GATE_EN = 3,
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};
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/*
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* Host capability
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*/
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enum ufs_mtk_host_caps {
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UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
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UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
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UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
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UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
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/* Override UFS_MTK_CAP_BROKEN_VCC's behavior to
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* allow vccqx upstream to enter LPM
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*/
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UFS_MTK_CAP_FORCE_VSx_LPM = 1 << 5,
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UFS_MTK_CAP_PMC_VIA_FASTAUTO = 1 << 6,
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UFS_MTK_CAP_TX_SKEW_FIX = 1 << 7,
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};
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struct ufs_mtk_crypt_cfg {
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struct regulator *reg_vcore;
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struct clk *clk_crypt_perf;
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struct clk *clk_crypt_mux;
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struct clk *clk_crypt_lp;
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int vcore_volt;
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};
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struct ufs_mtk_clk {
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struct ufs_clk_info *ufs_sel_clki; // mux
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struct ufs_clk_info *ufs_sel_max_clki; // max src
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struct ufs_clk_info *ufs_sel_min_clki; // min src
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};
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struct ufs_mtk_hw_ver {
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u8 step;
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u8 minor;
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u8 major;
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};
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#if IS_ENABLED(CONFIG_UFS_MEDIATEK_INTERNAL)
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struct tag_chipid {
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u32 size;
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u32 hw_code;
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u32 hw_subcode;
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u32 hw_ver;
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u32 sw_ver;
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};
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#endif
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struct ufs_mtk_host {
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struct phy *mphy;
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void __iomem *mphy_base;
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struct regulator *reg_va09;
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struct reset_control *hci_reset;
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struct reset_control *unipro_reset;
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struct reset_control *crypto_reset;
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struct reset_control *mphy_reset;
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struct ufs_hba *hba;
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struct ufs_mtk_crypt_cfg *crypt;
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struct ufs_mtk_hw_ver hw_ver;
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enum ufs_mtk_host_caps caps;
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bool mphy_powered_on;
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bool unipro_lpm;
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bool ref_clk_enabled;
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bool clk_scale_up;
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atomic_t clkscale_control;
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atomic_t clkscale_control_powerhal;
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u16 ref_clk_ungating_wait_us;
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u16 ref_clk_gating_wait_us;
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u32 ip_ver;
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u32 desired_ahit;
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struct ufs_mtk_clk mclk;
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bool pm_qos_init;
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struct pm_qos_request pm_qos_req;
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bool qos_allowed;
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bool qos_enabled;
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bool boot_device;
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bool skip_blocktag;
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struct completion luns_added;
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struct semaphore rpmb_sem;
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struct device *phy_dev;
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#if defined(CONFIG_UFSFEATURE)
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struct ufsf_feature ufsf;
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#endif
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};
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#define UFSHCD_MAX_TAG 256
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enum {
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REG_UFS_MCQCAP = 0x0c,
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REG_UFS_MCQCFG = 0x28,
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REG_UFS_MMIO_OPT_CTRL_0 = 0x160,
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REG_UFS_MMIO_SQ_IS = 0x190,
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REG_UFS_MMIO_SQ_IE = 0x194,
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REG_UFS_MMIO_CQ_IS = 0x1A0,
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REG_UFS_MMIO_CQ_IE = 0x1A4,
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REG_UFS_MMIO_VER_ID = 0x1B0,
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REG_UFS_MCQ_BASE = 0x320,
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REG_UFS_SQ_ATTR = (REG_UFS_MCQ_BASE + 0x0),
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REG_UFS_SQ_LBA = (REG_UFS_MCQ_BASE + 0x4),
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REG_UFS_SQ_UBA = (REG_UFS_MCQ_BASE + 0x8),
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REG_UFS_SQ_HEAD = (REG_UFS_MCQ_BASE + 0xc),
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REG_UFS_SQ_TAIL = (REG_UFS_MCQ_BASE + 0x10),
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REG_UFS_CQ_ATTR = (REG_UFS_MCQ_BASE + 0x18),
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REG_UFS_CQ_LBA = (REG_UFS_MCQ_BASE + 0x1c),
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REG_UFS_CQ_UBA = (REG_UFS_MCQ_BASE + 0x20),
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REG_UFS_CQ_HEAD = (REG_UFS_MCQ_BASE + 0x24),
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REG_UFS_CQ_TAIL = (REG_UFS_MCQ_BASE + 0x28),
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};
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/* MCQCAP 08h */
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#define MAX_Q GENMASK(4, 0)
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/* REG_UFS_MMIO_OPT_CTRL_0 160h */
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#define EHS_EN 0x1
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#define PFM_IMPV 0x2
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#define MCQ_MULTI_INTR_EN 0x4
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#define MCQ_CMB_INTR_EN 0x8
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#define MCQ_AH8 0x10
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#define SQ_INT 0x80000
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#define CQ_INT 0x100000
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#define UFSHCD_ENABLE_INTRS_MCQ (SQ_INT |\
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CQ_INT |\
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UTP_TASK_REQ_COMPL |\
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UFSHCD_ERROR_MASK)
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#define UFSHCD_ENABLE_INTRS_MCQ_SEPARATE \
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(UTP_TASK_REQ_COMPL | UFSHCD_ERROR_MASK)
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#define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN)
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struct utp_cq_entry {
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__le64 UCD_base;
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__le32 dword_2;
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__le32 dword_3;
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__le32 dword_4;
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__le32 dword_5; //reserved
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__le32 dword_6; //reserved
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__le32 dword_7; //reserved
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};
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#define UCD_BASE_ADD_MASK UFS_MASK(0x1ffffffffffffff,7) //bit7~63
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#define UCD_BASE_SQID_MASK UFS_MASK(0x1f, 0) //[4:0]
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#define UTRD_OCS_MASK UFS_MASK(0xff, 0)
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union utp_q_entry {
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struct utp_transfer_req_desc sq;
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struct utp_cq_entry cq;
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};
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#define SQE_SIZE sizeof(struct utp_transfer_req_desc)
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#define CQE_SIZE sizeof(struct utp_cq_entry)
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#define SQE_NUM_1K (1024 / SQE_SIZE)
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#define CQE_NUM_1K (1024 / CQE_SIZE)
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/* MCQCFG */
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#define MCQCFG_ARB_SCHEME (0x3<<1)
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#define MCQCFG_ARB_SP (0x0<<1)
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#define MCQCFG_ARB_RRP (0x1<<1)
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#define MCQCFG_TYPE (0x1<<0)
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#define Q_SPACING (0x30)
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#define MCQ_ADDR(base, index) ((base) + (Q_SPACING * (index)))
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#define Q_ENABLE (0x1<<31)
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#define UFSHCD_MAX_Q_NR 8
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#define UFSHCD_MCQ_PRI_THRESHOD 5
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enum {
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MCQ_Q_TYPE_SQ = 0,
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MCQ_Q_TYPE_CQ = 1,
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};
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struct ufs_queue {
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u8 q_enable; //0: disable, 1: enable
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u8 qid; //0... N-1
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u8 q_type; //SQ/CQ
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u16 q_depth;
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u8 priority;
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union utp_q_entry *q_base_addr; //content list
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union utp_q_entry *head; //u16 head;
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union utp_q_entry *tail; //u16 tail; //SW
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union utp_q_entry *tail_written; //u16 tail_written; //SW
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spinlock_t q_lock;
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dma_addr_t q_dma_addr;
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};
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struct ufs_sw_queue {
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u16 depth;
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u16 head;
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u16 tail;
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int tag_data[UFSHCD_MAX_TAG];
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};
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struct ufs_queue_config {
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struct ufs_queue *sq;
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struct ufs_queue *cq;
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u8 sq_nr;
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u8 cq_nr;
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u8 sq_cq_map[UFSHCD_MAX_Q_NR]; //sq to cq mapping, ex. sq_cq_mapping[3] = 2 means sq[3] mapping to cq[2]
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u32 sent_cmd_count[UFSHCD_MAX_Q_NR];
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};
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struct ufs_mcq_intr_info {
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struct ufs_hba *hba;
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u32 intr;
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u8 qid;
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};
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#define BITMAP_TAGS_LEN BITS_TO_LONGS(UFSHCD_MAX_TAG)
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struct ufs_hba_private {
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//struct ufs_hba *hba;
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u32 max_q;
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u32 mcq_cap;
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u32 mcq_nr_hw_queue;
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u32 mcq_nr_q_depth;
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u32 mcq_nr_intr;
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struct ufs_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
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struct utp_transfer_req_desc *usel_base_addr;
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struct utp_cq_entry *ucel_base_addr;
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dma_addr_t usel_dma_addr;
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dma_addr_t ucel_dma_addr;
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dma_addr_t sq_dma_addr;
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dma_addr_t cq_dma_addr;
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struct ufs_queue_config mcq_q_cfg;
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unsigned long outstanding_mcq_reqs[BITMAP_TAGS_LEN];
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bool is_mcq_enabled;
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bool is_mcq_intr_enabled;
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};
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int ufs_mtk_mcq_alloc_priv(struct ufs_hba *hba);
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void ufs_mtk_mcq_host_dts(struct ufs_hba *hba);
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void ufs_mtk_mcq_get_irq(struct platform_device *pdev);
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void ufs_mtk_mcq_request_irq(struct ufs_hba *hba);
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void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba);
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void ufs_mtk_mcq_disable_irq(struct ufs_hba *hba);
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void ufs_mtk_mcq_enable_irq(struct ufs_hba *hba);
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int ufs_mtk_mcq_memory_alloc(struct ufs_hba *hba);
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int ufs_mtk_mcq_install_tracepoints(void);
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/*
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* IOCTL opcode for ufs queries has the following opcode after
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* SCSI_IOCTL_GET_PCI
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*/
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#define UFS_IOCTL_QUERY 0x5388
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/**
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* struct ufs_ioctl_query_data - used to transfer data to and from user via
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* ioctl
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* @opcode: type of data to query (descriptor/attribute/flag)
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* @idn: id of the data structure
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* @buf_size: number of allocated bytes/data size on return
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* @buffer: data location
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*
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* Received: buffer and buf_size (available space for transferred data)
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* Submitted: opcode, idn, length, buf_size
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*/
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struct ufs_ioctl_query_data {
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/*
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* User should select one of the opcode defined in "enum query_opcode".
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* Please check include/uapi/scsi/ufs/ufs.h for the definition of it.
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* Note that only UPIU_QUERY_OPCODE_READ_DESC,
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* UPIU_QUERY_OPCODE_READ_ATTR & UPIU_QUERY_OPCODE_READ_FLAG are
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* supported as of now. All other query_opcode would be considered
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* invalid.
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* As of now only read query operations are supported.
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*/
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__u32 opcode;
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/*
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* User should select one of the idn from "enum flag_idn" or "enum
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* attr_idn" or "enum desc_idn" based on whether opcode above is
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* attribute, flag or descriptor.
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* Please check include/uapi/scsi/ufs/ufs.h for the definition of it.
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*/
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__u8 idn;
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/*
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* User should specify the size of the buffer (buffer[0] below) where
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* it wants to read the query data (attribute/flag/descriptor).
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* As we might end up reading less data then what is specified in
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* buf_size. So we are updating buf_size to what exactly we have read.
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*/
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__u16 buf_size;
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/*
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* placeholder for the start of the data buffer where kernel will copy
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* the query data (attribute/flag/descriptor) read from the UFS device
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* Note:
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* For Read/Write Attribute you will have to allocate 4 bytes
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* For Read/Write Flag you will have to allocate 1 byte
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*/
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__u8 buffer[0];
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};
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enum {
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BOOTDEV_SDMMC = 1,
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BOOTDEV_UFS = 2
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};
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struct tag_bootmode {
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u32 size;
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u32 tag;
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u32 bootmode;
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u32 boottype;
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};
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#if IS_ENABLED(CONFIG_RPMB)
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struct rpmb_dev *ufs_mtk_rpmb_get_raw_dev(void);
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#endif
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#if defined(CONFIG_UFSFEATURE)
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static inline struct ufsf_feature *ufs_mtk_get_ufsf(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return &host->ufsf;
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}
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#endif
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static inline const void *ufs_mtk_get_boot_property(struct device_node *np,
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const char *name, int *lenp)
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{
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struct device_node *boot_node = NULL;
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boot_node = of_parse_phandle(np, "bootmode", 0);
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if (!boot_node)
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return NULL;
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return of_get_property(boot_node, name, lenp);
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}
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#endif /* !_UFS_MEDIATEK_H */
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