329 lines
8.8 KiB
C
Executable file
329 lines
8.8 KiB
C
Executable file
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#ifndef __UPM6910_HEADER__
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#define __UPM6910_HEADER__
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/* Register 00h */
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#define UPM6910_REG_00 0x00
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#define REG00_ENHIZ_MASK 0x80
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#define REG00_ENHIZ_SHIFT 7
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#define REG00_HIZ_ENABLE 1
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#define REG00_HIZ_DISABLE 0
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#define REG00_STAT_CTRL_MASK 0x60
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#define REG00_STAT_CTRL_SHIFT 5
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#define REG00_STAT_CTRL_STAT 0
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#define REG00_STAT_CTRL_ICHG 1
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#define REG00_STAT_CTRL_IINDPM 2
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#define REG00_STAT_CTRL_DISABLE 3
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#define REG00_IINLIM_MASK 0x1F
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#define REG00_IINLIM_SHIFT 0
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#define REG00_IINLIM_LSB 100
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#define REG00_IINLIM_BASE 100
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/* Register 01h */
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#define UPM6910_REG_01 0x01
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#define REG01_PFM_DIS_MASK 0x80
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#define REG01_PFM_DIS_SHIFT 7
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#define REG01_PFM_ENABLE 0
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#define REG01_PFM_DISABLE 1
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#define REG01_WDT_RESET_MASK 0x40
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#define REG01_WDT_RESET_SHIFT 6
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#define REG01_WDT_RESET 1
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#define REG01_OTG_CONFIG_MASK 0x20
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#define REG01_OTG_CONFIG_SHIFT 5
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#define REG01_OTG_ENABLE 1
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#define REG01_OTG_DISABLE 0
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#define REG01_CHG_CONFIG_MASK 0x10
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#define REG01_CHG_CONFIG_SHIFT 4
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#define REG01_CHG_DISABLE 0
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#define REG01_CHG_ENABLE 1
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#define REG01_SYS_MINV_MASK 0x0E
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#define REG01_SYS_MINV_SHIFT 1
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#define REG01_MIN_VBAT_SEL_MASK 0x01
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#define REG01_MIN_VBAT_SEL_SHIFT 0
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#define REG01_MIN_VBAT_2P8V 0
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#define REG01_MIN_VBAT_2P5V 1
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/* Register 0x02*/
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#define UPM6910_REG_02 0x02
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#define REG02_BOOST_LIM_MASK 0x80
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#define REG02_BOOST_LIM_SHIFT 7
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#define REG02_BOOST_LIM_0P5A 0
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#define REG02_BOOST_LIM_1P2A 1
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#define REG02_Q1_FULLON_MASK 0x40
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#define REG02_Q1_FULLON_SHIFT 6
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#define REG02_Q1_FULLON_ENABLE 1
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#define REG02_Q1_FULLON_DISABLE 0
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#define REG02_ICHG_MASK 0x3F
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#define REG02_ICHG_SHIFT 0
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#define REG02_ICHG_BASE 0
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#define REG02_ICHG_LSB 60
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#define REG02_ICHG_MIN 840
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/* Register 0x03*/
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#define UPM6910_REG_03 0x03
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#define REG03_IPRECHG_MASK 0xF0
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#define REG03_IPRECHG_SHIFT 4
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#define REG03_IPRECHG_BASE 60
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#define REG03_IPRECHG_LSB 60
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#define REG03_ITERM_MASK 0x0F
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#define REG03_ITERM_SHIFT 0
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#define REG03_ITERM_BASE 60
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#define REG03_ITERM_LSB 60
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/* Register 0x04*/
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#define UPM6910_REG_04 0x04
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#define REG04_VREG_MASK 0xF8
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#define REG04_VREG_SHIFT 3
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#define REG04_VREG_BASE 3856
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#define REG04_VREG_LSB 32
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#define REG04_TOPOFF_TIMER_MASK 0x06
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#define REG04_TOPOFF_TIMER_SHIFT 1
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#define REG04_TOPOFF_TIMER_DISABLE 0
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#define REG04_TOPOFF_TIMER_15M 1
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#define REG04_TOPOFF_TIMER_30M 2
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#define REG04_TOPOFF_TIMER_45M 3
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#define REG04_VRECHG_MASK 0x01
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#define REG04_VRECHG_SHIFT 0
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#define REG04_VRECHG_100MV 0
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#define REG04_VRECHG_200MV 1
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/* Register 0x05*/
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#define UPM6910_REG_05 0x05
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#define REG05_EN_TERM_MASK 0x80
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#define REG05_EN_TERM_SHIFT 7
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#define REG05_TERM_ENABLE 1
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#define REG05_TERM_DISABLE 0
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#define REG05_WDT_MASK 0x30
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#define REG05_WDT_SHIFT 4
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#define REG05_WDT_DISABLE 0
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#define REG05_WDT_40S 1
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#define REG05_WDT_80S 2
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#define REG05_WDT_160S 3
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#define REG05_WDT_BASE 0
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#define REG05_WDT_LSB 40
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#define REG05_EN_TIMER_MASK 0x08
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#define REG05_EN_TIMER_SHIFT 3
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#define REG05_CHG_TIMER_ENABLE 1
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#define REG05_CHG_TIMER_DISABLE 0
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#define REG05_CHG_TIMER_MASK 0x04
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#define REG05_CHG_TIMER_SHIFT 2
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#define REG05_CHG_TIMER_5HOURS 0
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#define REG05_CHG_TIMER_10HOURS 1
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#define REG05_TREG_MASK 0x02
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#define REG05_TREG_SHIFT 1
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#define REG05_TREG_90C 0
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#define REG05_TREG_110C 1
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#define REG05_JEITA_ISET_MASK 0x01
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#define REG05_JEITA_ISET_SHIFT 0
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#define REG05_JEITA_ISET_50PCT 0
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#define REG05_JEITA_ISET_20PCT 1
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/* Register 0x06*/
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#define UPM6910_REG_06 0x06
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#define REG06_OVP_MASK 0xC0
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#define REG06_OVP_SHIFT 0x6
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#define REG06_OVP_5P5V 0
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#define REG06_OVP_6P5V 1
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#define REG06_OVP_10P5V 2
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#define REG06_OVP_14P0V 3
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#define REG06_BOOSTV_MASK 0x30
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#define REG06_BOOSTV_SHIFT 4
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#define REG06_BOOSTV_4P85V 0
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#define REG06_BOOSTV_5V 1
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#define REG06_BOOSTV_5P15V 2
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#define REG06_BOOSTV_5P3V 3
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#define REG06_VINDPM_MASK 0x0F
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#define REG06_VINDPM_SHIFT 0
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#define REG06_VINDPM_BASE 3900
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#define REG06_VINDPM_LSB 100
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/* Register 0x07*/
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#define UPM6910_REG_07 0x07
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#define REG07_FORCE_DPDM_MASK 0x80
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#define REG07_FORCE_DPDM_SHIFT 7
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#define REG07_FORCE_DPDM 1
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#define REG07_TMR2X_EN_MASK 0x40
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#define REG07_TMR2X_EN_SHIFT 6
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#define REG07_TMR2X_ENABLE 1
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#define REG07_TMR2X_DISABLE 0
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#define REG07_BATFET_DIS_MASK 0x20
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#define REG07_BATFET_DIS_SHIFT 5
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#define REG07_BATFET_OFF 1
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#define REG07_BATFET_ON 0
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#define REG07_JEITA_VSET_MASK 0x10
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#define REG07_JEITA_VSET_SHIFT 4
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#define REG07_JEITA_VSET_4100 0
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#define REG07_JEITA_VSET_VREG 1
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#define REG07_BATFET_DLY_MASK 0x08
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#define REG07_BATFET_DLY_SHIFT 3
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#define REG07_BATFET_DLY_0S 0
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#define REG07_BATFET_DLY_10S 1
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#define REG07_BATFET_RST_EN_MASK 0x04
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#define REG07_BATFET_RST_EN_SHIFT 2
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#define REG07_BATFET_RST_DISABLE 0
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#define REG07_BATFET_RST_ENABLE 1
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#define REG07_VDPM_BAT_TRACK_MASK 0x03
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#define REG07_VDPM_BAT_TRACK_SHIFT 0
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#define REG07_VDPM_BAT_TRACK_DISABLE 0
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#define REG07_VDPM_BAT_TRACK_200MV 1
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#define REG07_VDPM_BAT_TRACK_250MV 2
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#define REG07_VDPM_BAT_TRACK_300MV 3
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/* Register 0x08*/
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#define UPM6910_REG_08 0x08
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#define REG08_VBUS_STAT_MASK 0xE0
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#define REG08_VBUS_STAT_SHIFT 5
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#define REG08_VBUS_TYPE_NONE 0
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#define REG08_VBUS_TYPE_SDP 1
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#define REG08_VBUS_TYPE_CDP 2
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#define REG08_VBUS_TYPE_DCP 3
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#define REG08__VBUS_TYPE_HVDCP 4
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#define REG08_VBUS_TYPE_UNKNOWN 5
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#define REG08_VBUS_TYPE_NON_STD 6
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#define REG08_VBUS_TYPE_OTG 7
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#define REG08_CHRG_STAT_MASK 0x18
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#define REG08_CHRG_STAT_SHIFT 3
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#define REG08_CHRG_STAT_IDLE 0
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#define REG08_CHRG_STAT_PRECHG 1
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#define REG08_CHRG_STAT_FASTCHG 2
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#define REG08_CHRG_STAT_CHGDONE 3
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#define REG08_PG_STAT_MASK 0x04
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#define REG08_PG_STAT_SHIFT 2
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#define REG08_POWER_GOOD 1
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#define REG08_THERM_STAT_MASK 0x02
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#define REG08_THERM_STAT_SHIFT 1
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#define REG08_VSYS_STAT_MASK 0x01
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#define REG08_VSYS_STAT_SHIFT 0
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#define REG08_IN_VSYS_STAT 1
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/* Register 0x09*/
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#define UPM6910_REG_09 0x09
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#define REG09_FAULT_WDT_MASK 0x80
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#define REG09_FAULT_WDT_SHIFT 7
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#define REG09_FAULT_WDT 1
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#define REG09_FAULT_BOOST_MASK 0x40
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#define REG09_FAULT_BOOST_SHIFT 6
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#define REG09_FAULT_CHRG_MASK 0x30
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#define REG09_FAULT_CHRG_SHIFT 4
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#define REG09_FAULT_CHRG_NORMAL 0
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#define REG09_FAULT_CHRG_INPUT 1
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#define REG09_FAULT_CHRG_THERMAL 2
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#define REG09_FAULT_CHRG_TIMER 3
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#define REG09_FAULT_BAT_MASK 0x08
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#define REG09_FAULT_BAT_SHIFT 3
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#define REG09_FAULT_BAT_OVP 1
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#define REG09_FAULT_NTC_MASK 0x07
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#define REG09_FAULT_NTC_SHIFT 0
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#define REG09_FAULT_NTC_NORMAL 0
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#define REG09_FAULT_NTC_WARM 2
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#define REG09_FAULT_NTC_COOL 3
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#define REG09_FAULT_NTC_COLD 5
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#define REG09_FAULT_NTC_HOT 6
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/* Register 0x0A */
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#define UPM6910_REG_0A 0x0A
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#define REG0A_VBUS_GD_MASK 0x80
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#define REG0A_VBUS_GD_SHIFT 7
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#define REG0A_VBUS_GD 1
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#define REG0A_VINDPM_STAT_MASK 0x40
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#define REG0A_VINDPM_STAT_SHIFT 6
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#define REG0A_VINDPM_ACTIVE 1
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#define REG0A_IINDPM_STAT_MASK 0x20
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#define REG0A_IINDPM_STAT_SHIFT 5
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#define REG0A_IINDPM_ACTIVE 1
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#define REG0A_TOPOFF_ACTIVE_MASK 0x08
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#define REG0A_TOPOFF_ACTIVE_SHIFT 3
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#define REG0A_TOPOFF_ACTIVE 1
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#define REG0A_ACOV_STAT_MASK 0x04
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#define REG0A_ACOV_STAT_SHIFT 2
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#define REG0A_ACOV_ACTIVE 1
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#define REG0A_VINDPM_INT_MASK 0x02
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#define REG0A_VINDPM_INT_SHIFT 1
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#define REG0A_VINDPM_INT_ENABLE 0
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#define REG0A_VINDPM_INT_DISABLE 1
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#define REG0A_IINDPM_INT_MASK 0x01
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#define REG0A_IINDPM_INT_SHIFT 0
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#define REG0A_IINDPM_INT_ENABLE 0
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#define REG0A_IINDPM_INT_DISABLE 1
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#define REG0A_INT_MASK_MASK 0x03
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#define REG0A_INT_MASK_SHIFT 0
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/* Register 0x0B */
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#define UPM6910_REG_0B 0x0B
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#define REG0B_REG_RESET_MASK 0x80
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#define REG0B_REG_RESET_SHIFT 7
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#define REG0B_REG_RESET 1
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#define REG0B_PN_MASK 0x78
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#define REG0B_PN_SHIFT 3
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#define REG0B_DEV_REV_MASK 0x03
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#define REG0B_DEV_REV_SHIFT 0
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/* Register 0x0C */
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#define UPM6910_REG_0C 0x0C
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#define REG0C_EN_HVDCP_MASK 0x80
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#define REG0C_EN_HVDCP_SHIFT 7
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#define REG0C_EN_HVDCP_ENABLE 1
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#define REG0C_EN_HVDCP_DISABLE 0
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#define REG0C_DP_MUX_MASK 0x18
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#define REG0C_DP_MUX_SHIFT 4
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#define REG0C_DM_MUX_MASK 0x0C
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#define REG0C_DM_MUX_SHIFT 2
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#define REG0C_DPDM_OUT_HIZ 0
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#define REG0C_DPDM_OUT_0P6V 1
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#define REG0C_DPDM_OUT_0V 2
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#define REG0C_DPDM_OUT_3P3V 3
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#endif
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