334 lines
9.9 KiB
C
334 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __MTK_PE5P_H
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#define __MTK_PE5P_H
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#include "mtk_charger_algorithm_class.h"
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#define PE5P_ERR_LEVEL 1
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#define PE5P_INFO_LEVEL 2
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#define PE5P_DBG_LEVEL 3
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#define PE5P_ITA_GAP_WINDOW_SIZE 50
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#define PRECISION_ENHANCE 5
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#define DISABLE_VBAT_THRESHOLD -1
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extern int pe5p_get_log_level(void);
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#define PE5P_DBG(fmt, ...) \
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do { \
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if (pe5p_get_log_level() >= PE5P_DBG_LEVEL) \
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pr_info("[PE5P]%s " fmt, __func__, ##__VA_ARGS__); \
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} while (0)
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#define PE5P_INFO(fmt, ...) \
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do { \
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if (pe5p_get_log_level() >= PE5P_INFO_LEVEL) \
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pr_info("[PE5P]%s " fmt, __func__, ##__VA_ARGS__); \
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} while (0)
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#define PE5P_ERR(fmt, ...) \
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do { \
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if (pe5p_get_log_level() >= PE5P_ERR_LEVEL) \
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pr_info("[PE5P]%s " fmt, __func__, ##__VA_ARGS__); \
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} while (0)
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enum pe5p_adc_channel {
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PE5P_ADCCHAN_VBUS = 0,
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PE5P_ADCCHAN_IBUS,
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PE5P_ADCCHAN_VBAT,
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PE5P_ADCCHAN_IBAT,
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PE5P_ADCCHAN_TBAT,
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PE5P_ADCCHAN_TCHG,
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PE5P_ADCCHAN_VOUT,
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PE5P_ADCCHAN_VSYS,
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PE5P_ADCCHAN_MAX,
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};
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enum pe5p_algo_state {
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PE5P_ALGO_INIT = 0,
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PE5P_ALGO_MEASURE_R,
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PE5P_ALGO_SS_SWCHG,
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PE5P_ALGO_SS_DVCHG,
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PE5P_ALGO_CC_CV,
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PE5P_ALGO_STOP,
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PE5P_ALGO_STATE_MAX,
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};
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enum pe5p_thermal_level {
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PE5P_THERMAL_VERY_COLD = 0,
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PE5P_THERMAL_COLD,
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PE5P_THERMAL_VERY_COOL,
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PE5P_THERMAL_COOL,
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PE5P_THERMAL_NORMAL,
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PE5P_THERMAL_WARM,
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PE5P_THERMAL_VERY_WARM,
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PE5P_THERMAL_HOT,
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PE5P_THERMAL_VERY_HOT,
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PE5P_THERMAL_MAX,
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};
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enum pe5p_rcable_level {
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PE5P_RCABLE_NORMAL = 0,
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PE5P_RCABLE_BAD1,
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PE5P_RCABLE_BAD2,
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PE5P_RCABLE_BAD3,
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PE5P_RCABLE_MAX,
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};
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enum pe5p_dvchg_role {
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PE5P_DVCHG_MASTER = 0,
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PE5P_DVCHG_SLAVE,
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PE5P_HVDVCHG_MASTER,
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PE5P_HVDVCHG_SLAVE,
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PE5P_BUCK_BSTCHG,
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PE5P_DVCHG_MAX,
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};
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struct pe5p_ta_status {
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int temperature;
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bool ocp;
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bool otp;
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bool ovp;
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};
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struct pe5p_ta_auth_data {
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int vcap_min;
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int vcap_max;
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int icap_min;
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int vta_min;
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int vta_max;
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int ita_max;
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int ita_min;
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bool pwr_lmt;
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u8 pdp;
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bool support_meas_cap;
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bool support_status;
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bool support_cc;
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u32 vta_step;
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u32 ita_step;
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u32 ita_gap_per_vstep;
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};
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struct pe5p_algo_data {
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bool is_dvchg_exist[PE5P_DVCHG_MAX];
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/* Thread & Timer */
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struct alarm timer;
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struct task_struct *task;
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struct mutex lock;
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struct mutex ext_lock;
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wait_queue_head_t wq;
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atomic_t wakeup_thread;
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atomic_t stop_thread;
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atomic_t stop_algo;
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/* Notify */
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struct mutex notify_lock;
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u32 notify;
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/* Algorithm */
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bool inited;
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bool ta_ready;
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bool run_once;
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bool is_swchg_en;
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bool is_dvchg_en[PE5P_DVCHG_MAX];
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bool ignore_ibusucpf;
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bool force_ta_cv;
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bool tried_dual_dvchg;
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bool suspect_ta_cc;
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struct pe5p_ta_auth_data ta_auth_data;
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u32 vta_setting;
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u32 ita_setting;
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u32 vta_measure;
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u32 ita_measure;
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u32 ita_gap_per_vstep;
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u32 ita_gap_window_idx;
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u32 ita_gaps[PE5P_ITA_GAP_WINDOW_SIZE];
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u32 ichg_setting;
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u32 aicr_setting;
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u32 aicr_lmt;
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u32 aicr_init_lmt;
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u32 idvchg_cc;
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u32 idvchg_ss_init;
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u32 idvchg_term;
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int vbus_cali;
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u32 r_sw;
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u32 r_cable;
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u32 r_cable_by_swchg;
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u32 r_bat;
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u32 r_total;
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u32 ita_lmt;
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u32 ita_pwr_lmt;
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u32 cv_lower_bound;
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u32 err_retry_cnt;
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u32 vbusovp;
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u32 zcv;
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u32 vbat_cv_no_ircmp;
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u32 vbat_cv;
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u32 vbat_ircmp;
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int vta_comp;
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int vbat_threshold; /* For checking Ready */
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int ref_vbat; /* Vbat with cable in */
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bool is_vbat_over_cv;
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ktime_t stime;
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enum pe5p_algo_state state;
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enum pe5p_thermal_level tbat_level;
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enum pe5p_thermal_level tta_level;
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enum pe5p_thermal_level tdvchg_level;
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enum pe5p_thermal_level tswchg_level;
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int input_current_limit;
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int cv_limit;
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};
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/* Setting from dtsi */
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struct pe5p_algo_desc {
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u32 polling_interval; /* polling interval */
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u32 ta_cv_ss_repeat_tmin; /* min repeat time of ss for TA CV */
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u32 vbat_cv; /* vbat constant voltage */
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u32 start_soc_min; /* algo start bat low bound */
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u32 start_soc_max; /* algo start bat upper bound */
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u32 start_vbat_min; /* algo start bat low bound */
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u32 start_vbat_max; /* algo start bat upper bound */
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u32 idvchg_term; /* terminated current */
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u32 idvchg_step; /* input current step */
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u32 ita_level[PE5P_RCABLE_MAX]; /* input current */
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u32 rcable_level[PE5P_RCABLE_MAX]; /* cable impedance level */
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u32 ita_level_dual[PE5P_RCABLE_MAX]; /* input current */
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u32 rcable_level_dual[PE5P_RCABLE_MAX]; /* cable impedance level */
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u32 idvchg_ss_init; /* SS state init input current */
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u32 idvchg_ss_step; /* SS state input current step */
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u32 idvchg_ss_step1; /* SS state input current step2 */
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u32 idvchg_ss_step2; /* SS state input current step3 */
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u32 idvchg_ss_step1_vbat; /* vbat threshold for ic_ss_step2 */
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u32 idvchg_ss_step2_vbat; /* vbat threshold for ic_ss_step3 */
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u32 ta_blanking; /* wait TA stable */
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u32 swchg_aicr; /* CC state swchg input current */
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u32 swchg_ichg; /* CC state swchg charging current */
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u32 swchg_aicr_ss_init; /* SWCHG_SS state init input current */
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u32 swchg_aicr_ss_step; /* SWCHG_SS state input current step */
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u32 swchg_off_vbat; /* VBAT to turn off SWCHG */
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u32 force_ta_cv_vbat; /* Force TA using CV mode */
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u32 chg_time_max; /* max charging time */
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int tta_level_def[PE5P_THERMAL_MAX]; /* TA temp level */
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int tta_curlmt[PE5P_THERMAL_MAX]; /* TA temp current limit */
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int tbat_level_def[PE5P_THERMAL_MAX]; /* BAT temp level */
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int tbat_curlmt[PE5P_THERMAL_MAX]; /* BAT temp current limit */
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int tdvchg_level_def[PE5P_THERMAL_MAX]; /* DVCHG temp level */
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int tdvchg_curlmt[PE5P_THERMAL_MAX]; /* DVCHG temp current limit */
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int tswchg_level_def[PE5P_THERMAL_MAX]; /* SWCHG temp level */
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int tswchg_curlmt[PE5P_THERMAL_MAX]; /* SWCHG temp current limit */
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u32 tta_recovery_area;
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u32 tbat_recovery_area;
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u32 tdvchg_recovery_area;
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u32 tswchg_recovery_area;
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u32 ifod_threshold; /* FOD current threshold */
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u32 rsw_min; /* min rsw */
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u32 ircmp_rbat; /* IR compensation's rbat */
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u32 ircmp_vclamp; /* IR compensation's vclamp */
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u32 vta_cap_min; /* min ta voltage capability */
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u32 vta_cap_max; /* max ta voltage capability */
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u32 ita_cap_min; /* min ta current capability */
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const char **support_ta; /* supported ta name */
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u32 support_ta_cnt; /* supported ta count */
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bool allow_not_check_ta_status; /* allow not to check ta status */
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};
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struct pe5p_algo_info {
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struct device *dev;
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struct chg_alg_device *alg;
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struct pe5p_algo_desc *desc;
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struct pe5p_algo_data *data;
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};
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static inline u32 precise_div(u64 dividend, u64 divisor)
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{
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u64 _val = div64_u64(dividend << PRECISION_ENHANCE, divisor);
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return (u32)((_val + (1 << (PRECISION_ENHANCE - 1))) >>
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PRECISION_ENHANCE);
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}
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static inline u32 percent(u32 val, u32 percent)
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{
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return precise_div((u64)val * percent, 100);
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}
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static inline u32 div1000(u32 val)
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{
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return precise_div(val, 1000);
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}
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static inline u32 milli_to_micro(u32 val)
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{
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return val * 1000;
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}
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static inline int micro_to_milli(int val)
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{
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return (val < 0) ? -1 : div1000(val);
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}
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extern int pe5p_hal_get_ta_output(struct chg_alg_device *alg, int *mV, int *mA);
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extern int pe5p_hal_get_ta_status(struct chg_alg_device *alg,
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struct pe5p_ta_status *status);
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extern int pe5p_hal_set_ta_cap(struct chg_alg_device *alg, int mV, int mA);
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extern int pe5p_hal_is_ta_cc(struct chg_alg_device *alg, bool *is_cc);
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extern int pe5p_hal_set_ta_wdt(struct chg_alg_device *alg, u32 ms);
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extern int pe5p_hal_enable_ta_wdt(struct chg_alg_device *alg, bool en);
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extern int pe5p_hal_enable_ta_charging(struct chg_alg_device *alg, bool en,
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int mV, int mA);
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extern int pe5p_hal_sync_ta_volt(struct chg_alg_device *alg, u32 mV);
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extern int pe5p_hal_authenticate_ta(struct chg_alg_device *alg,
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struct pe5p_ta_auth_data *data);
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extern int pe5p_hal_send_ta_hardreset(struct chg_alg_device *alg);
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extern int pe5p_hal_init_hardware(struct chg_alg_device *alg,
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const char **support_ta, int support_ta_cnt);
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extern int pe5p_hal_enable_sw_vbusovp(struct chg_alg_device *alg, bool en);
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extern int pe5p_set_operating_mode(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool en);
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extern int pe5p_hal_enable_charging(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool en);
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extern int pe5p_hal_dump_registers(struct chg_alg_device *alg,
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enum chg_idx chgidx);
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extern int pe5p_hal_enable_hz(struct chg_alg_device *alg, enum chg_idx chgidx,
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bool en);
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extern int pe5p_hal_set_vacovp(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 mV);
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extern int pe5p_hal_set_vbusovp(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 mV);
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extern int pe5p_hal_set_ibusocp(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 mA);
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extern int pe5p_hal_set_vbatovp(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 mV);
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extern int pe5p_hal_set_ibatocp(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 mA);
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extern int pe5p_hal_set_vbatovp_alarm(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 mV);
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extern int pe5p_hal_reset_vbatovp_alarm(struct chg_alg_device *alg,
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enum chg_idx chgidx);
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extern int pe5p_hal_set_vbusovp_alarm(struct chg_alg_device *alg,
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enum chg_idx chgidx, u32 mV);
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extern int pe5p_hal_reset_vbusovp_alarm(struct chg_alg_device *alg,
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enum chg_idx chgidx);
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extern int pe5p_hal_get_adc(struct chg_alg_device *alg, enum chg_idx chgidx,
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enum pe5p_adc_channel chan, int *val);
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extern int pe5p_hal_get_soc(struct chg_alg_device *alg, u32 *soc);
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extern int pe5p_hal_is_pd_adapter_ready(struct chg_alg_device *alg);
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extern int pe5p_hal_set_ichg(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 mA);
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extern int pe5p_hal_set_aicr(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 mA);
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extern int pe5p_hal_get_ichg(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 *mA);
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extern int pe5p_hal_get_aicr(struct chg_alg_device *alg, enum chg_idx chgidx,
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u32 *mA);
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extern int pe5p_hal_is_vbuslowerr(struct chg_alg_device *alg,
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enum chg_idx chgidx, bool *err);
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extern int pe5p_hal_get_adc_accuracy(struct chg_alg_device *alg,
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enum chg_idx chgidx,
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enum pe5p_adc_channel chan, int *val);
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extern int pe5p_hal_init_chip(struct chg_alg_device *alg, enum chg_idx chgidx);
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#endif /* __MTK_PE5P_H */
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