986 lines
52 KiB
C
986 lines
52 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Ming-Fan Chen <ming-fan.chen@mediatek.com>
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*/
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#include <dt-bindings/interconnect/mtk,mmqos.h>
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#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
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#include <dt-bindings/memory/mt6985-larb-port.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include "mmqos-mtk.h"
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static const struct mtk_node_desc node_descs_mt6985[] = {
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DEFINE_MNODE(common0,
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SLAVE_COMMON(0), 0, false, 0x0, MMQOS_NO_LINK), //DISP
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DEFINE_MNODE(mdp_common0,
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SLAVE_COMMON(1), 0, false, 0x0, MMQOS_NO_LINK), //MDP
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DEFINE_MNODE(common0_port0,
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MASTER_COMMON_PORT(0, 0), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port1,
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MASTER_COMMON_PORT(0, 1), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port2,
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MASTER_COMMON_PORT(0, 2), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port3,
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MASTER_COMMON_PORT(0, 3), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port4,
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MASTER_COMMON_PORT(0, 4), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port5,
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MASTER_COMMON_PORT(0, 5), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port6,
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MASTER_COMMON_PORT(0, 6), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port7,
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MASTER_COMMON_PORT(0, 7), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port8,
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MASTER_COMMON_PORT(0, 8), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(mdp_common0_port0,
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MASTER_COMMON_PORT(1, 0), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port1,
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MASTER_COMMON_PORT(1, 1), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port2,
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MASTER_COMMON_PORT(1, 2), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port3,
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MASTER_COMMON_PORT(1, 3), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port4,
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MASTER_COMMON_PORT(1, 4), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port5,
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MASTER_COMMON_PORT(1, 5), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port6,
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MASTER_COMMON_PORT(1, 6), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port7,
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MASTER_COMMON_PORT(1, 7), 0, false, 0x0, SLAVE_COMMON(1)),
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DEFINE_MNODE(mdp_common0_port8,
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MASTER_COMMON_PORT(1, 8), 0, false, 0x0, SLAVE_COMMON(1)),
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/* SMI COMMON */
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DEFINE_MNODE(larb0, SLAVE_LARB(0), 0, false, 0x0, MASTER_COMMON_PORT(0, 0)),
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DEFINE_MNODE(larb21, SLAVE_LARB(21), 0, false, 0x0, MASTER_COMMON_PORT(0, 1)),
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DEFINE_MNODE(larb33, SLAVE_LARB(33), 0, false, 0x0, MASTER_COMMON_PORT(0, 1)),
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DEFINE_MNODE(larb2, SLAVE_LARB(2), 0, false, 0x0, MASTER_COMMON_PORT(0, 2)),
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DEFINE_MNODE(larb5, SLAVE_LARB(5), 0, false, 0x2, MASTER_COMMON_PORT(0, 3)),
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DEFINE_MNODE(larb7, SLAVE_LARB(7), 0, false, 0x1, MASTER_COMMON_PORT(0, 4)),
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DEFINE_MNODE(larb10, SLAVE_LARB(10), 0, false, 0x2, MASTER_COMMON_PORT(0, 5)),
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DEFINE_MNODE(larb22, SLAVE_LARB(22), 0, true, 0x2, MASTER_COMMON_PORT(0, 5)), //LARB11_u1
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DEFINE_MNODE(larb23, SLAVE_LARB(23), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)), //LARB11_u2
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DEFINE_MNODE(larb28, SLAVE_LARB(28), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)),
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DEFINE_MNODE(larb16, SLAVE_LARB(16), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB16_u0
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DEFINE_MNODE(larb31, SLAVE_LARB(31), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB16_u2
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DEFINE_MNODE(larb34, SLAVE_LARB(34), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB17_u1
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DEFINE_MNODE(larb25, SLAVE_LARB(25), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
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DEFINE_MNODE(larb19, SLAVE_LARB(19), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
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//DEFINE_MNODE(larb17, SLAVE_LARB(17), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB17_u0
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//DEFINE_MNODE(larb35, SLAVE_LARB(35), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB17_u2
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DEFINE_MNODE(larb29, SLAVE_LARB(29), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
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DEFINE_MNODE(larb6, SLAVE_LARB(6), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)),
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/* MDP COMMON */
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DEFINE_MNODE(larb1, SLAVE_LARB(1), 0, false, 0x0, MASTER_COMMON_PORT(1, 0)),
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DEFINE_MNODE(larb32, SLAVE_LARB(32), 0, false, 0x0, MASTER_COMMON_PORT(1, 0)),
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DEFINE_MNODE(larb20, SLAVE_LARB(20), 0, false, 0x0, MASTER_COMMON_PORT(1, 1)),
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DEFINE_MNODE(larb3, SLAVE_LARB(3), 0, false, 0x0, MASTER_COMMON_PORT(1, 2)),
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DEFINE_MNODE(larb4, SLAVE_LARB(4), 0, false, 0x11, MASTER_COMMON_PORT(1, 3)),
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DEFINE_MNODE(larb8, SLAVE_LARB(8), 0, true, 0x12, MASTER_COMMON_PORT(1, 4)),
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DEFINE_MNODE(larb37, SLAVE_LARB(37), 0, false, 0x12, MASTER_COMMON_PORT(1, 4)), //LARB8_u1
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DEFINE_MNODE(larb9, SLAVE_LARB(9), 0, false, 0x11, MASTER_COMMON_PORT(1, 5)),
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DEFINE_MNODE(larb11, SLAVE_LARB(11), 0, false, 0x0, MASTER_COMMON_PORT(1, 5)),
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DEFINE_MNODE(larb12, SLAVE_LARB(12), 0, false, 0x0, MASTER_COMMON_PORT(1, 5)),
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DEFINE_MNODE(larb15, SLAVE_LARB(15), 0, true, 0x11, MASTER_COMMON_PORT(1, 5)),
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DEFINE_MNODE(larb18, SLAVE_LARB(18), 0, false, 0x0, MASTER_COMMON_PORT(1, 5)),
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DEFINE_MNODE(larb13, SLAVE_LARB(13), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)),
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DEFINE_MNODE(larb30, SLAVE_LARB(30), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), //LARB16_u1
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DEFINE_MNODE(larb17, SLAVE_LARB(17), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), //LARB17_u0
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DEFINE_MNODE(larb35, SLAVE_LARB(35), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), //LARB17_u2
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DEFINE_MNODE(larb26, SLAVE_LARB(26), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)),
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DEFINE_MNODE(larb27, SLAVE_LARB(27), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)),
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DEFINE_MNODE(larb14, SLAVE_LARB(14), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)),
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DEFINE_MNODE(larb38, SLAVE_LARB(38), 0, false, 0x1, MASTER_COMMON_PORT(0, 8)), //virt DISP
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DEFINE_MNODE(larb39, SLAVE_LARB(39), 0, true, 0x1, MASTER_COMMON_PORT(0, 6)), //virt CCU
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DEFINE_MNODE(larb40, SLAVE_LARB(40), 0, true, 0x12, MASTER_COMMON_PORT(1, 6)), //virt CCU0
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/* LARB0 */
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DEFINE_MNODE(larb0_disp_ovl0_2L_hdr_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_HDR), 7, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_ovl0_2L_rdma0_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_RDMA0), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_ovl1_2L_rdma1_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_RDMA1), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_ovl2_2L_hdr_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL2_2L_HDR), 7, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_ovl2_2L_rdma0_w,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL2_2L_RDMA0), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_ovl3_2L_rdma1_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL3_2L_RDMA1), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_wdma0_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_WDMA0), 9, true, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_ufbc_wdma0_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_UFBC_WDMA0), 9, true, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(larb0_disp_fake0_r,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_FAKE0), 8, false, 0x1, SLAVE_LARB(0)),
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/* LARB21 */
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DEFINE_MNODE(larb21_disp_ovl0_2L_rdma1_r,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL0_2L_RDMA1), 8, false, 0x2, SLAVE_LARB(21)),
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DEFINE_MNODE(larb21_disp_ovl1_2L_hdr_r,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL1_2L_HDR), 7, false, 0x2, SLAVE_LARB(21)),
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DEFINE_MNODE(larb21_disp_ovl1_2L_rdma0_r,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL1_2L_RDMA0), 8, false, 0x2, SLAVE_LARB(21)),
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DEFINE_MNODE(larb21_disp_ovl2_2L_rdma1_r,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL2_2L_RDMA1), 8, false, 0x2, SLAVE_LARB(21)),
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DEFINE_MNODE(larb21_disp_ovl3_2L_hdr_w,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL3_2L_HDR), 7, false, 0x2, SLAVE_LARB(21)),
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DEFINE_MNODE(larb21_disp_ovl3_2L_rdma0_r,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL3_2L_RDMA0), 8, false, 0x2, SLAVE_LARB(21)),
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DEFINE_MNODE(larb21_disp_wdma2_w,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_WDMA2), 9, true, 0x2, SLAVE_LARB(21)),
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DEFINE_MNODE(larb21_disp_fake1_r,
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MASTER_LARB_PORT(M4U_PORT_L21_DISP_FAKE1), 8, false, 0x2, SLAVE_LARB(21)),
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/* LARB33 */
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DEFINE_MNODE(larb33_disp_postmask0_r,
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MASTER_LARB_PORT(M4U_PORT_L33_DISP_POSTMASK0), 7, false, 0x2, SLAVE_LARB(33)),
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DEFINE_MNODE(larb33_disp_mdp_rdma0_r,
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MASTER_LARB_PORT(M4U_PORT_L33_DISP_MDP_RDMA0), 8, false, 0x2, SLAVE_LARB(33)),
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DEFINE_MNODE(larb33_disp_oddmr0_dmrr_w,
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MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_DMRR), 8, false, 0x2, SLAVE_LARB(33)),
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DEFINE_MNODE(larb33_disp_oddmr0_odr_w,
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MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_ODR), 8, false, 0x2, SLAVE_LARB(33)),
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DEFINE_MNODE(larb33_disp_oddmr0_odw_r,
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MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_ODW), 9, true, 0x2, SLAVE_LARB(33)),
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DEFINE_MNODE(larb33_disp_wdma1_r,
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MASTER_LARB_PORT(M4U_PORT_L33_DISP_WDMA1), 9, true, 0x2, SLAVE_LARB(33)),
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DEFINE_MNODE(larb33_disp_ufbc_wdma1_w,
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MASTER_LARB_PORT(M4U_PORT_L33_DISP_UFBC_WDMA1), 9, true, 0x2, SLAVE_LARB(33)),
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/* LARB2 */
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DEFINE_MNODE(larb2_mdp_rdma0_r,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0), 8, false, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_mdp_wrot0_w,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0), 7, true, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_disp_fake0_r,
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MASTER_LARB_PORT(M4U_PORT_L2_DISP_FAKE0), 8, false, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_mdp_rdma1_r,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA1), 8, false, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_mdp_wrot1_w,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT1), 7, true, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_mdp_rdma2_r,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA2), 8, false, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_mdp_rdma3_r,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA3), 8, false, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_mdp_wdma2_w,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_WDMA2), 8, true, 0x1, SLAVE_LARB(2)),
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DEFINE_MNODE(larb2_mdp_wdma3_w,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_WDMA3), 8, true, 0x1, SLAVE_LARB(2)),
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/* LARB5 */
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DEFINE_MNODE(larb5_hw_vdec_lat0_vld_ext_r,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_LAT0_VLD_EXT), 7, false, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_lat0_vld2_ext_r,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_LAT0_VLD2_EXT), 7, false, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_lat0_avc_mv_ext_r,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_LAT0_AVC_MV_EXT), 6, false, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_lat0_pred_rd_ext_r,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_LAT0_PRED_RD_EXT), 7, false, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_lat0_tile_ext_r,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_LAT0_TILE_EXT), 7, false, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_lat0_wdma_ext_w,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_LAT0_WDMA_EXT), 8, true, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_ufo_enc_ext_w,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_UFO_ENC_EXT), 7, true, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_ufo_enc_ext_c_w,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_UFO_ENC_EXT_C), 7, true, 0x2, SLAVE_LARB(5)),
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DEFINE_MNODE(larb5_hw_vdec_mc_ext_r,
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MASTER_LARB_PORT(M4U_PORT_L5_HW_VDEC_MC_EXT), 6, false, 0x2, SLAVE_LARB(5)),
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/* LARB7 */
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DEFINE_MNODE(l7_venc_rcpu_r,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_RCPU), 7, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_rec_w,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_REC), 8, true, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_bsdma_w,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_BSDMA), 8, true, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_sv_comv_w,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_SV_COMV), 8, true, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_rd_comv_r,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_RD_COMV), 7, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_nbm_rdma_r,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_nbm_rdma_lite_r,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA_LITE), 5, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_jpgenc_y_rdma_r,
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MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_jpgenc_c_rdma_r,
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MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_jpgenc_q_table_r,
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MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_TABLE), 7, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_sub_w_luma_w,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_W_LUMA), 8, true, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_fcs_nbm_rdma_r,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_ec_wpp_bsdma_w,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_EC_WPP_BSDMA), 8, true, 0x1, SLAVE_LARB(7)),
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DEFINE_MNODE(l7_venc_ec_wpp_rdma_r,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_EC_WPP_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_db_sysram_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_DB_SYSRAM_WDMA), 8, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_db_sysram_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_DB_SYSRAM_RDMA), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_jpgenc_bsdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA), 8, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_jpgdec_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_WDMA_0), 8, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_jpgdec_bsdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_BSDMA_0), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_nbm_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA), 8, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_nbm_wdma_lite_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA_LITE), 6, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_cur_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_LUMA), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_cur_chroma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_CHROMA), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_ref_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_LUMA), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_ref_chroma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_CHROMA), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_sub_r_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_R_LUMA), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_venc_fcs_nbm_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_WDMA), 8, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_jpgdec_wdma_1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_WDMA_1), 8, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_jpgdec_bsdma_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_BSDMA_1), 7, false, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_jpgdec_huff_offset_1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_HUFF_OFFSET_1), 8, true, 0x1, SLAVE_LARB(7)),
|
|
DEFINE_MNODE(l7_jpgdec_huff_offset_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_HUFF_OFFSET_0), 8, true, 0x1, SLAVE_LARB(7)),
|
|
/* LARB10 */
|
|
DEFINE_MNODE(larb10_imgi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMGI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_imgci_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMGCI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_imgci_d1_n_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMGCI_D1_N), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_dmgi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_DMGI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_reci_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_RECI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_tnraimi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRAIMI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_reci_d3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_RECI_D3), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_recbi_d2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_RECBI_D2), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_tnrwi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRWI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_tnrci_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRCI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_smti_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_smtci_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTCI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_img4o_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMG4O_D1), 8, true, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_img4co_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMG4CO_D1), 8, true, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_tnrmo_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRMO_D1), 8, true, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_smto_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTO_D1), 8, true, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_smtco_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTCO_D1), 8, true, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_tnrsi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRSI_D1), 7, false, 0x2, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(larb10_tnrso_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRSO_D1), 8, true, 0x2, SLAVE_LARB(10)),
|
|
/* LARB22 */
|
|
DEFINE_MNODE(larb22_wpe_rdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_0), 8, false, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_wpe_rdma_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_1), 6, false, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_wpe_rdma_4p_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_4P_0), 8, false, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_wpe_rdma_4p_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_4P_1), 6, false, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_pimgi_p1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_PIMGI_P1), 7, false, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_pimgbi_p1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_PIMGBI_P1), 7, false, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_wpe_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_WDMA_0), 8, true, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_wpe_wdma_4p_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_WDMA_4P_0), 8, true, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_wrot_p1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WROT_P1), 8, true, 0x2, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(larb22_tccso_p1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_TCCSO_P1), 8, true, 0x2, SLAVE_LARB(22)),
|
|
/* LARB23 */
|
|
DEFINE_MNODE(larb23_wpe_rdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_0), 8, false, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_wpe_rdma_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_1), 6, false, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_wpe_rdma_4p_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_4P_0), 8, false, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_wpe_rdma_4p_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_4P_1), 6, false, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_pimgi_p1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_PIMGI_P1), 7, false, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_pimgbi_p1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_PIMGBI_P1), 7, false, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_wpe_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_WDMA_0), 8, true, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_wpe_wdma_4p_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_WDMA_4P_0), 8, true, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_wrot_p1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WROT_P1), 8, true, 0x2, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(larb23_tccso_p1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_TCCSO_P1), 8, true, 0x2, SLAVE_LARB(23)),
|
|
/* LARB28 */
|
|
DEFINE_MNODE(larb28_imgi_t1_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGI_T1_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_imgi_t1_n_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGI_T1_N_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_imgci_t1_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGCI_T1_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_imgci_t1_n_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGCI_T1_N_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_smti_t1_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTI_T1_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_smti_t4_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTI_T4_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_tncsti_t1_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TNCSTI_T1_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_tncsti_t4_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TNCSTI_T4_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_ltmsti_t1_a_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_LTMSTI_T1_A), 7, false, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_yuvo_t1_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVO_T1_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_yuvo_t1_n_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVO_T1_N_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_yuvco_t1_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVCO_T1_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_yuvo_t2_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVO_T2_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_yuvo_t4_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVO_T4_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_tncsto_t1_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TNCSTO_T1_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_tncso_t1_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TNCSO_T1_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_smto_t1_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTO_T1_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_smto_t4_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTO_T4_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(larb28_ltmso_t1_a_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_LTMSO_T1_A), 8, true, 0x2, SLAVE_LARB(28)),
|
|
/* LARB16 */
|
|
DEFINE_MNODE(larb16_cqi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_CQI_R1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_rawi_r2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R2), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_rawi_r3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R3), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_rawi_r5_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R5), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_imgo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_IMGO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_bpci_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_BPCI_R1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_lcsi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_LCSI_R1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_ufeo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_UFEO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_ltmso_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_LTMSO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_drzb2no_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_DRZB2NO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_aao_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_AAO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(larb16_afo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_AFO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
/* LARB31 */
|
|
DEFINE_MNODE(larb31_cqi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_CQI_R1), 8, false, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_rawi_r2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_RAWI_R2), 8, false, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_rawi_r3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_RAWI_R3), 8, false, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_rawi_r5_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_RAWI_R5), 8, false, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_imgo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_IMGO_R1), 9, true, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_bpci_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_BPCI_R1), 8, false, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_lcsi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_LCSI_R1), 8, false, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_ufeo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_UFEO_R1), 9, true, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_ltmso_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_LTMSO_R1), 9, true, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_drzb2no_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_DRZB2NO_R1), 9, true, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_aao_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_AAO_R1), 9, true, 0x1, SLAVE_LARB(31)),
|
|
DEFINE_MNODE(larb31_afo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L31_AFO_R1), 9, true, 0x1, SLAVE_LARB(31)),
|
|
/* LARB34 */
|
|
DEFINE_MNODE(larb34_yuvo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R1), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(larb34_yuvo_r3_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R3), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(larb34_yuvo_r2_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R2), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(larb34_yuvo_r5_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R5), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(larb34_rgbwi_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_RGBWI_R1), 8, false, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(larb34_tcyso_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_TCYSO_R1), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(larb34_drz4no_r3_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_DRZ4NO_R3), 9, true, 0x1, SLAVE_LARB(34)),
|
|
/* LARB25 */
|
|
DEFINE_MNODE(larb25_mraw0_cqi_m1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_CQI_M1), 8, false, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_mraw0_imgbo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGBO_M1), 9, true, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_mraw2_cqi_m1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_CQI_M1), 8, false, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_mraw2_imgbo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGBO_M1), 9, true, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_pdai_a_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_0), 8, false, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_pdai_a_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_1), 8, false, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_pdai_a_2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_2), 8, false, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_pdai_a_3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_3), 8, false, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_pdai_a_4_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_4), 8, false, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_pdao_a_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAO_A_0), 9, true, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_mraw0_imgo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGO_M1), 9, true, 0x1, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(larb25_mraw2_imgo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGO_M1), 9, true, 0x1, SLAVE_LARB(25)),
|
|
/* LARB19 */
|
|
DEFINE_MNODE(larb19_ccui_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUI), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(larb19_ccuo_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUO), 9, true, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(larb19_ccui2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUI2), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(larb19_ccuo2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUO2), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(larb19_dvs_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVS_RDMA), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(larb19_dvs_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVS_WDMA), 9, true, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(larb19_dvp_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVP_RDMA), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(larb19_dvp_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVP_WDMA), 9, true, 0x1, SLAVE_LARB(19)),
|
|
/* LARB17 */
|
|
DEFINE_MNODE(larb17_yuvo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R1), 9, true, 0x12, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(larb17_yuvo_r3_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R3), 9, true, 0x12, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(larb17_yuvo_r2_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R2), 9, true, 0x12, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(larb17_yuvo_r5_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R5), 9, true, 0x12, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(larb17_rgbwi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_RGBWI_R1), 8, false, 0x12, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(larb17_tcyso_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_TCYSO_R1), 9, true, 0x12, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(larb17_drz4no_r3_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_DRZ4NO_R3), 9, true, 0x12, SLAVE_LARB(17)),
|
|
/* LARB35 */
|
|
DEFINE_MNODE(larb35_yuvo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R1), 9, true, 0x12, SLAVE_LARB(35)),
|
|
DEFINE_MNODE(larb35_yuvo_r3_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R3), 9, true, 0x12, SLAVE_LARB(35)),
|
|
DEFINE_MNODE(larb35_yuvo_r2_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R2), 9, true, 0x12, SLAVE_LARB(35)),
|
|
DEFINE_MNODE(larb35_yuvo_r5_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R5), 9, true, 0x12, SLAVE_LARB(35)),
|
|
DEFINE_MNODE(larb35_rgbwi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L35_RGBWI_R1), 8, false, 0x12, SLAVE_LARB(35)),
|
|
DEFINE_MNODE(larb35_tcyso_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L35_TCYSO_R1), 9, true, 0x12, SLAVE_LARB(35)),
|
|
DEFINE_MNODE(larb35_drz4no_r3_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L35_DRZ4NO_R3), 9, true, 0x12, SLAVE_LARB(35)),
|
|
/* LARB29 */
|
|
DEFINE_MNODE(larb29_cqi_2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CQI_2), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(larb29_cqi_3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CQI_3), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(larb29_cqi_4_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CQI_4), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(larb29_cqi_5_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CQI_5), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(larb29_camsv_2_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_2_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(larb29_camsv_3_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_3_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(larb29_camsv_4_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_4_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(larb29_camsv_5_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_5_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
/* LARB6 */
|
|
DEFINE_MNODE(larb6_hw_mini_mdp_r0_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_R0_EXT), 7, false, 0x2, SLAVE_LARB(6)),
|
|
DEFINE_MNODE(larb6_hw_mini_mdp_w0_ext_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_W0_EXT), 8, true, 0x2, SLAVE_LARB(6)),
|
|
DEFINE_MNODE(larb6_hw_mini_mdp_r1_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_R1_EXT), 7, false, 0x2, SLAVE_LARB(6)),
|
|
DEFINE_MNODE(larb6_hw_mini_mdp_w1_ext_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_W1_EXT), 8, true, 0x2, SLAVE_LARB(6)),
|
|
/* LARB1 */
|
|
DEFINE_MNODE(larb1_disp_ovl0_2L_rdma1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_2L_RDMA1), 8, false, 0x11, SLAVE_LARB(1)),
|
|
DEFINE_MNODE(larb1_disp_ovl1_2L_hdr_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_HDR), 7, false, 0x11, SLAVE_LARB(1)),
|
|
DEFINE_MNODE(larb1_disp_ovl1_2L_rdma0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_RDMA0), 8, false, 0x11, SLAVE_LARB(1)),
|
|
DEFINE_MNODE(larb1_disp_ovl2_2L_rdma1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL2_2L_RDMA1), 8, false, 0x11, SLAVE_LARB(1)),
|
|
DEFINE_MNODE(larb1_disp_ovl3_2L_hdr_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL3_2L_HDR), 7, false, 0x11, SLAVE_LARB(1)),
|
|
DEFINE_MNODE(larb1_disp_ovl3_2L_rdma0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL3_2L_RDMA0), 8, false, 0x11, SLAVE_LARB(1)),
|
|
DEFINE_MNODE(larb1_disp_wdma2_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_WDMA2), 9, true, 0x11, SLAVE_LARB(1)),
|
|
DEFINE_MNODE(larb1_disp_fake1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L1_DISP_FAKE1), 8, false, 0x11, SLAVE_LARB(1)),
|
|
/* LARB32 */
|
|
DEFINE_MNODE(larb32_disp_postmask0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L32_DISP_POSTMASK0), 7, false, 0x11, SLAVE_LARB(32)),
|
|
DEFINE_MNODE(larb32_disp_mdp_rdma0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L32_DISP_MDP_RDMA0), 8, false, 0x11, SLAVE_LARB(32)),
|
|
DEFINE_MNODE(larb32_disp_oddmr0_dmrr_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_DMRR), 8, false, 0x11, SLAVE_LARB(32)),
|
|
DEFINE_MNODE(larb32_disp_oddmr0_odr_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_ODR), 8, false, 0x11, SLAVE_LARB(32)),
|
|
DEFINE_MNODE(larb32_disp_oddmr0_odw_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_ODW), 9, true, 0x11, SLAVE_LARB(32)),
|
|
DEFINE_MNODE(larb32_disp_wdma1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L32_DISP_WDMA1), 9, true, 0x11, SLAVE_LARB(32)),
|
|
DEFINE_MNODE(larb32_disp_ufbc_wdma1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L32_DISP_UFBC_WDMA1), 9, true, 0x11, SLAVE_LARB(32)),
|
|
/* LARB20 */
|
|
DEFINE_MNODE(larb20_disp_ovl0_2L_hdr_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_HDR), 7, false, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_ovl0_2L_rdma0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_RDMA0), 8, false, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_ovl1_2L_rdma1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL1_2L_RDMA1), 8, false, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_ovl2_2L_hdr_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL2_2L_HDR), 7, false, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_ovl2_2L_rdma0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL2_2L_RDMA0), 8, false, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_ovl3_2L_rdma1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL3_2L_RDMA1), 8, false, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_wdma0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_WDMA0), 9, true, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_ufbc_wdma0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_UFBC_WDMA0), 9, true, 0x12, SLAVE_LARB(20)),
|
|
DEFINE_MNODE(larb20_disp_fake0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L20_DISP_FAKE0), 8, false, 0x12, SLAVE_LARB(20)),
|
|
/* LARB3 */
|
|
DEFINE_MNODE(larb3_mdp_rdma0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA0), 6, false, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_mdp_wrot0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_WROT0), 7, true, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_disp_fake0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_DISP_FAKE0), 8, false, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_mdp_rdma1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA1), 6, false, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_mdp_wrot1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_WROT1), 7, true, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_mdp_rdma2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA2), 6, false, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_mdp_rdma3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA3), 6, false, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_mdp_wdma2_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_WDMA2), 8, true, 0x11, SLAVE_LARB(3)),
|
|
DEFINE_MNODE(larb3_mdp_wdma3_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L3_MDP_WDMA3), 8, true, 0x11, SLAVE_LARB(3)),
|
|
/* LARB4 */
|
|
DEFINE_MNODE(larb4_hw_vdec_mc_c_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_MC_C_EXT), 6, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_ufo_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_UFO_EXT), 7, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_pp_ext_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PP_EXT), 8, true, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_pred_rd_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_RD_EXT), 7, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_pred_wr_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_WR_EXT), 7, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_ppwrap_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PPWRAP_EXT), 7, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_tile_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_TILE_EXT), 7, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_vld_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD_EXT), 7, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_vld2_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD2_EXT), 7, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_avc_mv_ext_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_AVC_MV_EXT), 6, false, 0x11, SLAVE_LARB(4)),
|
|
DEFINE_MNODE(larb4_hw_vdec_ufo_ext_c_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_UFO_EXT_C), 7, false, 0x11, SLAVE_LARB(4)),
|
|
/* LARB8 */
|
|
DEFINE_MNODE(l8_venc_rcpu_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_RCPU), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_rec_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_REC), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_bsdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_BSDMA), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_sv_comv_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_SV_COMV), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_rd_comv_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_RD_COMV), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_nbm_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_RDMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_nbm_rdma_lite_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_RDMA_LITE), 5, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgenc_y_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_Y_RDMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgenc_c_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_C_RDMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgenc_q_table_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_Q_TABLE), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_sub_w_luma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_SUB_W_LUMA), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_fcs_nbm_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_FCS_NBM_RDMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_ec_wpp_bsdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_EC_WPP_BSDMA), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_ec_wpp_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_EC_WPP_RDMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_db_sysram_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_DB_SYSRAM_WDMA), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_db_sysram_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_DB_SYSRAM_RDMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgenc_bsdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_BSDMA), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgdec_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_WDMA_0), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgdec_bsdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_BSDMA_0), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_nbm_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_WDMA), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_nbm_wdma_lite_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_WDMA_LITE), 6, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_cur_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_CUR_LUMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_cur_chroma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_CUR_CHROMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_ref_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_REF_LUMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_ref_chroma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_REF_CHROMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_sub_r_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_SUB_R_LUMA), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_venc_fcs_nbm_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_VENC_FCS_NBM_WDMA), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgdec_wdma_1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_WDMA_1), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgdec_bsdma_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_BSDMA_1), 7, false, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgdec_huff_offset_1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_HUFF_OFFSET_1), 8, true, 0x12, SLAVE_LARB(8)),
|
|
DEFINE_MNODE(l8_jpgdec_huff_offset_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_HUFF_OFFSET_0), 8, true, 0x12, SLAVE_LARB(8)),
|
|
/* LARB37 */
|
|
DEFINE_MNODE(larb37_venc_rcpu_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_RCPU), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_rec_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_REC), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_bsdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_BSDMA), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_sv_comv_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_SV_COMV), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_rd_comv_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_RD_COMV), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_nbm_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_NBM_RDMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_nbm_rdma_lite_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_NBM_RDMA_LITE), 5, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgenc_y_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGENC_Y_RDMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgenc_c_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGENC_C_RDMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgenc_q_table_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGENC_Q_TABLE), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_sub_w_luma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_SUB_W_LUMA), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_fcs_nbm_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_FCS_NBM_RDMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_ec_wpp_bsdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_EC_WPP_BSDMA), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_ec_wpp_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_EC_WPP_RDMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_db_sysram_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_DB_SYSRAM_WDMA), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_db_sysram_rdma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_DB_SYSRAM_RDMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgenc_bsdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGENC_BSDMA), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgdec_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGDEC_WDMA_0), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgdec_bsdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGDEC_BSDMA_0), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_nbm_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_NBM_WDMA), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_nbm_wdma_lite_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_NBM_WDMA_LITE), 6, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_cur_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_CUR_LUMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_cur_chroma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_CUR_CHROMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_ref_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_REF_LUMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_ref_chroma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_REF_CHROMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_sub_r_luma_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_SUB_R_LUMA), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_venc_fcs_nbm_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_VENC_FCS_NBM_WDMA), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgdec_wdma_1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGDEC_WDMA_1), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgdec_bsdma_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGDEC_BSDMA_1), 7, false, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgdec_huff_offset_1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGDEC_HUFF_OFFSET_1), 8, true, 0x12, SLAVE_LARB(37)),
|
|
DEFINE_MNODE(larb37_jpgdec_huff_offset_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L37_JPGDEC_HUFF_OFFSET_0), 8, true, 0x12, SLAVE_LARB(37)),
|
|
/* LARB9 */
|
|
DEFINE_MNODE(larb9_imgi_t1_b_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_IMGI_T1_B), 7, false, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_imgi_t1_n_b_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_IMGI_T1_N_B), 7, false, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_imgci_t1_b_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_IMGCI_T1_B), 7, false, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_imgci_t1_n_b_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_IMGCI_T1_N_B), 7, false, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_smti_t1_b_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_SMTI_T1_B), 7, false, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_yuvo_t1_b_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T1_B), 8, true, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_yuvo_t1_n_b_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T1_N_B), 8, true, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_yuvco_t1_b_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVCO_T1_B), 8, true, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_yuvo_t2_b_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T2_B), 8, true, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_yuvo_t4_b_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T4_B), 8, true, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_tncsto_t1_b_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_TNCSTO_T1_B), 8, true, 0x11, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(larb9_smto_t1_b_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_SMTO_T1_B), 8, true, 0x11, SLAVE_LARB(9)),
|
|
/* LARB11 */
|
|
DEFINE_MNODE(larb11_wpe_rdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_0), 8, false, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_wpe_rdma_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_1), 6, false, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_wpe_rdma_4p_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_4P_0), 8, false, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_wpe_rdma_4p_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_4P_1), 6, false, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_pimgi_p1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_PIMGI_P1), 7, false, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_pimgbi_p1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_PIMGBI_P1), 7, false, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_wpe_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_WDMA_0), 8, true, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_wpe_wdma_4p_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_WDMA_4P_0), 8, true, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_wrot_p1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WROT_P1), 8, true, 0x11, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(larb11_tccso_p1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_TCCSO_P1), 8, true, 0x11, SLAVE_LARB(11)),
|
|
/* LARB12 */
|
|
DEFINE_MNODE(larb12_fdvt_rda_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_FDVT_RDA_0), 6, false, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_fdvt_wra_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_FDVT_WRA_0), 8, true, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_me_rdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_RDMA_0), 7, false, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_me_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_WDMA_0), 8, true, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_memmg_rdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_RDMA_0), 6, false, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_memmg_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_WDMA_0), 7, true, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_me_2nd_rdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_2ND_RDMA_0), 7, false, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_me_2nd_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_2ND_WDMA_0), 8, true, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_memmg_2nd_rdma_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_2ND_RDMA_0), 6, false, 0x11, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(larb12_memmg_2nd_wdma_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_2ND_WDMA_0), 7, true, 0x11, SLAVE_LARB(12)),
|
|
/* LARB15 */
|
|
DEFINE_MNODE(larb15_vipi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_VIPI_D1), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_vipi_d1_n_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_VIPI_D1_N), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_tncsti_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSTI_D1), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_tncsti_d4_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSTI_D4), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_eecsi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_EECSI_D1), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_snrcsi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SNRCSI_D1), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_csmcsi_d1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_CSMCSI_D1), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_smti_d4_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMTI_D4), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_smti_d6_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMTI_D6), 7, false, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_img3o_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_IMG3O_D1), 8, true, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_img3co_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_IMG3CO_D1), 8, true, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_img2o_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_IMG2O_D1), 8, true, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_tnco_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCO_D1), 8, true, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_tncso_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSO_D1), 8, true, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_tncsto_d1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSTO_D1), 8, true, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_smto_d4_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMTO_D4), 8, true, 0x11, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(larb15_smto_d6_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMTO_D6), 8, true, 0x11, SLAVE_LARB(15)),
|
|
/* LARB18 */
|
|
DEFINE_MNODE(larb18_imgadl_0_ipui_e1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L18_IMGADL_0_IPUI_E1), 7, false, 0x11, SLAVE_LARB(18)),
|
|
DEFINE_MNODE(larb18_imgadl_0_ipui_e2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L18_IMGADL_0_IPUI_E2), 7, false, 0x11, SLAVE_LARB(18)),
|
|
/* LARB13 */
|
|
DEFINE_MNODE(larb13_cqi_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_CQI_1), 8, false, 0x12, SLAVE_LARB(13)),
|
|
DEFINE_MNODE(larb13_camsv_1_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_1_WDMA), 9, true, 0x12, SLAVE_LARB(13)),
|
|
DEFINE_MNODE(larb13_fake_eng_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_FAKE_ENG), 8, false, 0x12, SLAVE_LARB(13)),
|
|
/* LARB30 */
|
|
DEFINE_MNODE(larb30_cqi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_CQI_R1), 8, false, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_rawi_r2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R2), 8, false, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_rawi_r3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R3), 8, false, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_rawi_r5_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R5), 8, false, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_imgo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_IMGO_R1), 9, true, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_bpci_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_BPCI_R1), 8, false, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_lcsi_r1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_LCSI_R1), 8, false, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_ufeo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_UFEO_R1), 9, true, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_ltmso_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_LTMSO_R1), 9, true, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_drzb2no_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_DRZB2NO_R1), 9, true, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_aao_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_AAO_R1), 9, true, 0x12, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(larb30_afo_r1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_AFO_R1), 9, true, 0x12, SLAVE_LARB(30)),
|
|
/* LARB26 */
|
|
DEFINE_MNODE(larb26_mraw1_cqi_m1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_CQI_M1), 8, false, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_mraw1_imgbo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGBO_M1), 9, true, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_mraw3_cqi_m1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_CQI_M1), 8, false, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_mraw3_imgbo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGBO_M1), 9, true, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_pdai_b_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_0), 8, false, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_pdai_b_1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_1), 8, false, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_pdai_b_2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_2), 8, false, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_pdai_b_3_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_3), 8, false, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_pdai_b_4_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_4), 8, false, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_pdao_b_0_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_PDAO_B_0), 9, true, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_mraw1_imgo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGO_M1), 9, true, 0x12, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(larb26_mraw3_imgo_m1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGO_M1), 9, true, 0x12, SLAVE_LARB(26)),
|
|
/* LARB27 */
|
|
DEFINE_MNODE(larb27_ipui_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_IPUI), 8, false, 0x12, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(larb27_ipui_2_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_IPUI_2), 8, false, 0x12, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(larb27_ipu3o_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_IPU3O), 9, true, 0x12, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(larb27_cqi_u1_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_CQI_U1), 8, false, 0x12, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(larb27_imgo_u1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_IMGO_U1), 9, true, 0x12, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(larb27_yuvo_u1_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_YUVO_U1), 9, true, 0x12, SLAVE_LARB(27)),
|
|
/* LARB14 */
|
|
DEFINE_MNODE(larb14_cqi_0_r,
|
|
MASTER_LARB_PORT(M4U_PORT_L14_CQI_0), 8, true, 0x12, SLAVE_LARB(14)),
|
|
DEFINE_MNODE(larb14_camsv_0_wdma_w,
|
|
MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_0_WDMA), 9, true, 0x12, SLAVE_LARB(14)),
|
|
};
|
|
static const char * const comm_muxes_mt6985[] = { "mm", "mdp" };
|
|
static const char * const comm_icc_path_names_mt6985[] = { "icc-bw", "icc-bw" };
|
|
static const char * const comm_icc_hrt_path_names_mt6985[] = { "icc-hrt-bw", "icc-hrt-bw" };
|
|
static const struct mtk_mmqos_desc mmqos_desc_mt6985 = {
|
|
.nodes = node_descs_mt6985,
|
|
.num_nodes = ARRAY_SIZE(node_descs_mt6985),
|
|
.comm_muxes = comm_muxes_mt6985,
|
|
.comm_icc_path_names = comm_icc_path_names_mt6985,
|
|
.comm_icc_hrt_path_names = comm_icc_hrt_path_names_mt6985,
|
|
.max_ratio = 64,
|
|
.hrt = {
|
|
.hrt_bw = {12183, 0, 0},
|
|
.hrt_total_bw = 68264, /* Todo: Use DRAMC API 8533*4(channel)*2(io width)*/
|
|
.md_speech_bw = { 12808, 12183},
|
|
.hrt_ratio = {1000, 880, 900, 900}, /* MD, CAM, DISP, MML */
|
|
.blocking = true,
|
|
.emi_ratio = 630,
|
|
},
|
|
.comm_port_channels = {
|
|
{ 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x3 },
|
|
{ 0x1, 0x2, 0x1, 0x1, 0x2, 0x1, 0x2, 0x2, 0x3 }
|
|
},
|
|
.comm_port_hrt_types = {
|
|
{ HRT_MAX_BWL, HRT_MAX_BWL, HRT_NONE, HRT_NONE, HRT_NONE,
|
|
HRT_NONE, HRT_CAM, HRT_NONE, HRT_DISP },
|
|
{ HRT_MAX_BWL, HRT_MAX_BWL, HRT_NONE, HRT_NONE, HRT_NONE,
|
|
HRT_NONE, HRT_CAM, HRT_NONE, HRT_NONE },
|
|
},
|
|
//.dual_pipe_larbs = { SLAVE_LARB(1), SLAVE_LARB(20) },
|
|
.mmqos_state = MMQOS_ENABLE | COMM_OSTDL_ENABLE,
|
|
.report_bw_larbs = { SLAVE_LARB(9), SLAVE_LARB(10),
|
|
SLAVE_LARB(15), SLAVE_LARB(22),
|
|
SLAVE_LARB(4), SLAVE_LARB(5),
|
|
SLAVE_LARB(7), SLAVE_LARB(8),
|
|
SLAVE_LARB(37),},
|
|
};
|
|
static const struct of_device_id mtk_mmqos_mt6985_of_ids[] = {
|
|
{
|
|
.compatible = "mediatek,mt6985-mmqos",
|
|
.data = &mmqos_desc_mt6985,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_mmqos_mt6985_of_ids);
|
|
static struct platform_driver mtk_mmqos_mt6985_driver = {
|
|
.probe = mtk_mmqos_probe,
|
|
.remove = mtk_mmqos_remove,
|
|
.driver = {
|
|
.name = "mtk-mt6985-mmqos",
|
|
.of_match_table = mtk_mmqos_mt6985_of_ids,
|
|
},
|
|
};
|
|
module_platform_driver(mtk_mmqos_mt6985_driver);
|
|
MODULE_LICENSE("GPL v2");
|