730 lines
38 KiB
C
730 lines
38 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Ming-Fan Chen <ming-fan.chen@mediatek.com>
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*/
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#include <dt-bindings/interconnect/mtk,mmqos.h>
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#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
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#include <dt-bindings/memory/mt6886-larb-port.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include "mmqos-mtk.h"
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static const struct mtk_node_desc node_descs_mt6886[] = {
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DEFINE_MNODE(common0,
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SLAVE_COMMON(0), 0, false, 0x0, MMQOS_NO_LINK), //DISP
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DEFINE_MNODE(common0_port0,
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MASTER_COMMON_PORT(0, 0), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port1,
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MASTER_COMMON_PORT(0, 1), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port2,
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MASTER_COMMON_PORT(0, 2), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port3,
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MASTER_COMMON_PORT(0, 3), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port4,
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MASTER_COMMON_PORT(0, 4), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port5,
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MASTER_COMMON_PORT(0, 5), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port6,
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MASTER_COMMON_PORT(0, 6), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port7,
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MASTER_COMMON_PORT(0, 7), 0, false, 0x0, SLAVE_COMMON(0)),
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DEFINE_MNODE(common0_port8,
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MASTER_COMMON_PORT(0, 8), 0, false, 0x0, SLAVE_COMMON(0)),
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/* SMI COMMON */
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DEFINE_MNODE(larb0, SLAVE_LARB(0), 0, false, 0x0, MASTER_COMMON_PORT(0, 0)),
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DEFINE_MNODE(larb1, SLAVE_LARB(1), 0, false, 0x0, MASTER_COMMON_PORT(0, 1)),
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DEFINE_MNODE(larb2, SLAVE_LARB(2), 0, false, 0x0, MASTER_COMMON_PORT(0, 2)),
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DEFINE_MNODE(larb7, SLAVE_LARB(7), 0, false, 0x0, MASTER_COMMON_PORT(0, 2)),
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DEFINE_MNODE(larb4, SLAVE_LARB(4), 0, false, 0x0, MASTER_COMMON_PORT(0, 3)),
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DEFINE_MNODE(larb28, SLAVE_LARB(28), 0, false, 0x0, MASTER_COMMON_PORT(0, 4)),
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DEFINE_MNODE(larb10, SLAVE_LARB(10), 0, false, 0x1, MASTER_COMMON_PORT(0, 4)),
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DEFINE_MNODE(larb22, SLAVE_LARB(22), 0, true, 0x1, MASTER_COMMON_PORT(0, 4)), //larb11B
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DEFINE_MNODE(larb23, SLAVE_LARB(23), 0, false, 0x0, MASTER_COMMON_PORT(0, 4)), //larb11C
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DEFINE_MNODE(larb12, SLAVE_LARB(12), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)),
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DEFINE_MNODE(larb15, SLAVE_LARB(15), 0, true, 0x2, MASTER_COMMON_PORT(0, 5)),
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DEFINE_MNODE(larb11, SLAVE_LARB(11), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)), //larb11A
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DEFINE_MNODE(larb9, SLAVE_LARB(9), 0, false, 0x2, MASTER_COMMON_PORT(0, 5)),
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DEFINE_MNODE(larb14, SLAVE_LARB(14), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
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DEFINE_MNODE(larb29, SLAVE_LARB(29), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
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DEFINE_MNODE(larb16, SLAVE_LARB(16), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //larb16A
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DEFINE_MNODE(larb34, SLAVE_LARB(34), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //larb17B
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DEFINE_MNODE(larb26, SLAVE_LARB(26), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
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DEFINE_MNODE(larb19, SLAVE_LARB(19), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)),
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DEFINE_MNODE(larb27, SLAVE_LARB(27), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)),
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DEFINE_MNODE(larb13, SLAVE_LARB(13), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)),
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DEFINE_MNODE(larb17, SLAVE_LARB(17), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)), //larb17A
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DEFINE_MNODE(larb30, SLAVE_LARB(30), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)), //larb16B
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DEFINE_MNODE(larb25, SLAVE_LARB(25), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)),
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DEFINE_MNODE(larb35, SLAVE_LARB(35), 0, false, 0x1, MASTER_COMMON_PORT(0, 8)), //virt disp
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DEFINE_MNODE(larb36, SLAVE_LARB(36), 0, true, 0x1, MASTER_COMMON_PORT(0, 6)), //virt ccu0
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DEFINE_MNODE(larb37, SLAVE_LARB(37), 0, true, 0x2, MASTER_COMMON_PORT(0, 7)), //virt ccu1
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/* LARB0 */
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DEFINE_MNODE(disp_postmask_larb0_0,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_POSTMASK), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_ovl0_hdr_larb0_1,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_HDR), 7, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_ovl0_2L_hdr_larb0_2,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_HDR), 7, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_ovl1_2L_hdr_larb0_3,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_HDR), 7, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_ovl0_0_larb0_4,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_0), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_ovl0_2L_0_larb0_5,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_0), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_ovl1_2L_0_larb0_6,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_0), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_rdma0_larb0_7,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0), 8, false, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_wdma0_larb0_8,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_WDMA0), 9, true, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_ufbc_wdma0_larb0_9,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_UFBC_WDMA0), 9, true, 0x1, SLAVE_LARB(0)),
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DEFINE_MNODE(disp_fake0_larb0_10,
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MASTER_LARB_PORT(M4U_PORT_L0_DISP_FAKE0), 9, true, 0x1, SLAVE_LARB(0)),
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/* LARB1 */
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DEFINE_MNODE(disp_ovl0_1_larb1_0,
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MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_1), 8, false, 0x2, SLAVE_LARB(1)),
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DEFINE_MNODE(disp_ovl0_2L_1_larb1_1,
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MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_2L_1), 8, false, 0x2, SLAVE_LARB(1)),
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DEFINE_MNODE(disp_ovl1_2L_1_larb1_2,
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MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_1), 8, false, 0x2, SLAVE_LARB(1)),
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DEFINE_MNODE(disp_rdma1_larb1_3,
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MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA1), 8, false, 0x2, SLAVE_LARB(1)),
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DEFINE_MNODE(disp_wdma1_larb1_4,
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MASTER_LARB_PORT(M4U_PORT_L1_DISP_WDMA1), 9, true, 0x2, SLAVE_LARB(1)),
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DEFINE_MNODE(disp_fake1_larb1_5,
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MASTER_LARB_PORT(M4U_PORT_L1_DISP_FAKE1), 9, true, 0x2, SLAVE_LARB(1)),
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/* LARB2 */
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DEFINE_MNODE(mdp_rdma0_larb2_0,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0), 8, false, 0x2, SLAVE_LARB(2)),
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DEFINE_MNODE(mdp_rdma1_larb2_1,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA1), 8, false, 0x2, SLAVE_LARB(2)),
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DEFINE_MNODE(mdp_wrot0_larb2_2,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0), 8, true, 0x2, SLAVE_LARB(2)),
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DEFINE_MNODE(mdp_wrot1_larb2_3,
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MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT1), 8, true, 0x2, SLAVE_LARB(2)),
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DEFINE_MNODE(disp_fake0_larb2_4,
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MASTER_LARB_PORT(M4U_PORT_L2_DISP_FAKE0), 1, true, 0x2, SLAVE_LARB(2)),
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/* LARB4 */
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DEFINE_MNODE(hw_vdec_mc_ext_larb4_0,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_MC_EXT), 6, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_ufo_ext_larb4_1,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_UFO_EXT), 7, false, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_pp_ext_larb4_2,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PP_EXT), 8, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_pred_rd_ext_larb4_3,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_RD_EXT), 7, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_pred_wr_ext_larb4_4,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_WR_EXT), 7, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_ppwrap_ext_larb4_5,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PPWRAP_EXT), 7, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_tile_ext_larb4_6,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_TILE_EXT), 7, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_vld_ext_larb4_7,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD_EXT), 7, false, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_vld2_ext_larb4_8,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD2_EXT), 7, false, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_avc_mv_ext_larb4_9,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_AVC_MV_EXT), 6, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_rg_ctrl_dma_ext_larb4_10,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT),
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7, false, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_vdec_ufo_enc_ext_larb4_11,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_UFO_ENC_EXT), 7, true, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_mini_mdp_r0_ext_larb4_12,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_MINI_MDP_R0_EXT), 8, false, 0x1, SLAVE_LARB(4)),
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DEFINE_MNODE(hw_mini_mdp_w0_ext_larb4_13,
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MASTER_LARB_PORT(M4U_PORT_L4_HW_MINI_MDP_W0_EXT), 9, true, 0x1, SLAVE_LARB(4)),
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/* LARB7 */
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DEFINE_MNODE(venc_rcpu_larb7_0,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_RCPU), 7, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_rec_larb7_1,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_REC), 8, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_bsdna_larb7_2,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_BSDNA), 8, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_sv_comv_larb7_3,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_SV_COMV), 8, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_rd_comv_larb7_4,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_RD_COMV), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_nbm_rdma_larb7_5,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_nbm_rdma_lite_larb7_6,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA_LITE), 5, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(jpgenc_y_rdma_larb7_7,
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MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(jpgenc_c_rdma_larb7_8,
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MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_RDMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(jpgenc_q_table_larb7_9,
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MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_TABLE), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_sub_w_luma_larb7_10,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_W_LUMA), 8, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_fcs_nbm_rdma_larb7_11,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_RDMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(jpgenc_bsdma_larb7_12,
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MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA), 8, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_nbm_wdma_larb7_13,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA), 8, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_nbm_wdma_lite_larb7_14,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA_LITE), 6, true, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_cur_luma_larb7_15,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_LUMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_cur_chroma_larb7_16,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_CHROMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_ref_luma_larb7_17,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_LUMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_ref_chroma_larb7_18,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_CHROMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_sub_r_luma_larb7_19,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_R_LUMA), 7, false, 0x2, SLAVE_LARB(7)),
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DEFINE_MNODE(venc_fcs_nbm_wdma_larb7_20,
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MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_WDMA), 8, true, 0x2, SLAVE_LARB(7)),
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/* LARB9 */
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DEFINE_MNODE(imgi_t1_c_larb9_0,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGI_T1_C), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(imgi_t1_n_c_larb9_1,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGI_T1_N_C), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(imgci_t1_c_larb9_2,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGCI_T1_C), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(imgci_t1_n_c_larb9_3,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGCI_T1_N_C), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(smti_t1_c_larb9_4,
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MASTER_LARB_PORT(M4U_PORT_L9_SMTI_T1_C), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(smti_t4_c_larb9_5,
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MASTER_LARB_PORT(M4U_PORT_L9_SMTI_T4_C), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(yuvo_t1_c_larb9_6,
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MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T1_C), 8, true, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(yuvbo_t1_c_larb9_7,
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MASTER_LARB_PORT(M4U_PORT_L9_YUVBO_T1_C), 8, true, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(yuvco_t1_c_larb9_9,
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MASTER_LARB_PORT(M4U_PORT_L9_YUVCO_T1_C), 8, true, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(yuvo_t2_c_larb9_9,
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MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T2_C), 8, true, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(yuvo_t4_c_larb9_10,
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MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T4_C), 8, true, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(imgi_t1_b_larb9_11,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGI_T1_B), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(imgi_t1_n_b_larb9_12,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGI_T1_N_B), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(imgci_t1_b_larb9_13,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGCI_T1_B), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(imgci_t1_n_b_larb9_14,
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MASTER_LARB_PORT(M4U_PORT_L9_IMGCI_T1_N_B), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(smti_t1_b_larb9_15,
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MASTER_LARB_PORT(M4U_PORT_L9_SMTI_T1_B), 7, false, 0x2, SLAVE_LARB(9)),
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DEFINE_MNODE(yuvo_t1_b_larb9_16,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T1_B), 8, true, 0x2, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(yuvo_t1_n_b_larb9_17,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T1_N_B), 8, true, 0x2, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(yuvco_t1_b_larb9_18,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVCO_T1_B), 8, true, 0x2, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(yuvo_t2_b_larb9_19,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T2_B), 8, true, 0x2, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(yuvo_t4_b_larb9_20,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_YUVO_T4_B), 8, true, 0x2, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(tncsto_t1_b_larb9_21,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_TNCSTO_T1_B), 8, true, 0x2, SLAVE_LARB(9)),
|
|
DEFINE_MNODE(smto_t1_b_larb9_25,
|
|
MASTER_LARB_PORT(M4U_PORT_L9_SMTO_T1_B), 8, false, 0x2, SLAVE_LARB(9)),
|
|
/* LARB10 */
|
|
DEFINE_MNODE(img_d1_larb10_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMG_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(imgci_d1_larb10_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMGCI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(imgci_d1_n_larb10_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMGCI_D1_N), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(dmgi_d1_larb10_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_DMGI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(reci_d1_larb10_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_RECI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(tnraimi_d1_larb10_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRAIMI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(reci_d3_larb10_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_RECI_D3), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(recbi_d2_larb10_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_RECBI_D2), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(tnrwi_d1_larb10_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRWI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(tnrci_d1_larb10_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRCI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(smti_d1_larb10_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(smtci_d1_larb10_11,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTCI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(img4o_d1_larb10_12,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMG4O_D1), 8, true, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(img4co_d1_larb10_13,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_IMG4CO_D1), 8, true, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(tnrmo_d1_larb10_14,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRMO_D1), 8, true, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(smto_d1_larb10_15,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTO_D1), 8, true, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(smtco_d1_larb10_16,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_SMTCO_D1), 8, true, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(tnrsi_d1_larb10_17,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRSI_D1), 7, false, 0x1, SLAVE_LARB(10)),
|
|
DEFINE_MNODE(tnrso_d1_larb10_18,
|
|
MASTER_LARB_PORT(M4U_PORT_L10_TNRSO_D1), 8, true, 0x1, SLAVE_LARB(10)),
|
|
/* LARB11 */
|
|
DEFINE_MNODE(wpe_rdma_0_larb11_u0_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_0), 6, false, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(wpe_rdma_1_larb11_u0_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_1), 6, false, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(wpe_rdma_4p_0_larb11_u0_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_4P_0), 6, false, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(wpe_rdma_4p_1_larb11_u0_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_RDMA_4P_1), 6, false, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(pimgi_p1_larb11_u0_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_PIMGI_P1), 7, false, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(pimgbi_p1_larb11_u0_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_PIMGBI_P1), 7, false, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(wpe_wdma_0_larb11_u0_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_WDMA_0), 7, true, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(wpe_wdma_4p_0_larb11_u0_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WPE_WDMA_4P_0), 7, true, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(wrot_p1_larb11_u0_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_WROT_P1), 8, true, 0x2, SLAVE_LARB(11)),
|
|
DEFINE_MNODE(tesco_p1_larb11_u0_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L11_TESCO_P1), 8, true, 0x2, SLAVE_LARB(11)),
|
|
/* LARB12 */
|
|
DEFINE_MNODE(fdvt_rda_0_larb12_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_FDVT_RDA_0), 7, false, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(fdvt_wra_0_larb12_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_FDVT_WRA_0), 8, true, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(me_rdma_0_larb12_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_RDMA_0), 7, false, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(me_wdma_0_larb12_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_WDMA_0), 8, true, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(memmg_rdma_0_larb12_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_RDMA_0), 7, false, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(memmg_wdma_0_larb12_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_WDMA_0), 8, true, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(me_2nd_rdma_0_larb12_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_2ND_RDMA_0), 7, false, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(me_2nd_wdma_0_larb12_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_ME_2ND_WDMA_0), 7, false, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(memmg_2nd_rdma_0_larb12_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_2ND_RDMA_0), 7, false, 0x2, SLAVE_LARB(12)),
|
|
DEFINE_MNODE(memmg_2nd_wdma_0_larb12_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L12_MEMMG_2ND_WDMA_0), 7, false, 0x2, SLAVE_LARB(12)),
|
|
/* LARB13 */
|
|
DEFINE_MNODE(camsv_cqi_e1_larb13_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_CQI_E1), 8, false, 0x2, SLAVE_LARB(13)),
|
|
DEFINE_MNODE(camsv_e1_wdma_larb13_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_E1_WDMA), 9, true, 0x2, SLAVE_LARB(13)),
|
|
DEFINE_MNODE(fake_eng_larb13_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_FAKE_ENG), 8, false, 0x2, SLAVE_LARB(13)),
|
|
DEFINE_MNODE(camsv_r_0_larb13_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_R_0), 8, false, 0x2, SLAVE_LARB(13)),
|
|
DEFINE_MNODE(camsv_r_1_larb13_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_R_1), 8, false, 0x2, SLAVE_LARB(13)),
|
|
/* LARB14 */
|
|
DEFINE_MNODE(camsv_cqi_e0_larb14_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_CQI_E0), 8, false, 0x1, SLAVE_LARB(14)),
|
|
DEFINE_MNODE(camsv_e0_wdma_larb14_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_E0_WDMA), 9, true, 0x1, SLAVE_LARB(14)),
|
|
DEFINE_MNODE(camsv_r_0_wdma_larb14_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_R_0_WDMA), 8, false, 0x1, SLAVE_LARB(14)),
|
|
DEFINE_MNODE(camsv_r_1_wdma_larb14_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_R_1_WDMA), 8, false, 0x1, SLAVE_LARB(14)),
|
|
/* LARB15 */
|
|
DEFINE_MNODE(vipi_d1_larb15_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_VIPI_D1), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(vipi_d1_n_larb15_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_VIPI_D1_N), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(tncsti_d1_larb15_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSTI_D1), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(tncsi_d4_larb15_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSI_D4), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(eecsi_d1_larb15_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_EECSI_D1), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(snrcsi_d1_larb15_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SNRCSI_D1), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(csmcsi_d1_larb15_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_CSMCSI_D1), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(smiti_d4_larb15_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMITI_D4), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(smti_d6_larb15_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMTI_D6), 7, false, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(img3o_d1_larb15_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_IMG3O_D1), 8, true, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(img3co__d1_larb15_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_IMG3CO_D1), 8, true, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(img2o_d1_larb15_11,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_IMG2O_D1), 8, true, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(tnco_d1_larb15_12,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCO_D1), 8, true, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(tncso_d1_larb15_13,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSO_D1), 8, true, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(tncsto_d1_larb15_14,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_TNCSTO_D1), 8, true, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(smto_d4_larb15_15,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMTO_D4), 8, true, 0x2, SLAVE_LARB(15)),
|
|
DEFINE_MNODE(smto_d6_larb15_16,
|
|
MASTER_LARB_PORT(M4U_PORT_L15_SMTO_D6), 8, true, 0x2, SLAVE_LARB(15)),
|
|
/* LARB16 */
|
|
DEFINE_MNODE(cqi_r1_larb16_u0_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_CQI_R1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(rawi_r2_larb16_u0_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R2), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(rawi_r3_larb16_u0_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R3), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(rawi_r5_larb16_u0_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R5), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(imgo_r1_larb16_u0_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_IMGO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(bpci_r1_larb16_u0_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_BPCI_R1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(lsci_r1_larb16_u0_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_LSCI_R1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(ufeo_r1_larb16_u0_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_UFEO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(ltmso_r1_larb16_u0_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_LTMSO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(drzb2no_r1_larb16_u0_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_DRZB2NO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(aao_r1_larb16_u0_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_AAO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(afo_r1_larb16_u0_11,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_AFO_R1), 9, true, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(rgbwi_r1_larb16_u0_12,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RGBWI_R1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(raw_r_0_larb16_u0_13,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAW_R_0), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(raw_r_1_larb16_u0_14,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAW_R_1), 8, false, 0x1, SLAVE_LARB(16)),
|
|
DEFINE_MNODE(raw_r_2_larb16_u0_15,
|
|
MASTER_LARB_PORT(M4U_PORT_L16_RAW_R_2), 8, false, 0x1, SLAVE_LARB(16)),
|
|
/* LARB17 */
|
|
DEFINE_MNODE(yuvo_r1_larb17_u0_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R1), 9, true, 0x2, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(yuvo_r3_larb17_u0_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R3), 9, true, 0x2, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(yuvo_r2_larb17_u0_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R2), 9, true, 0x2, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(yuvo_r5_larb17_u0_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R5), 9, true, 0x2, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(yuv_r_0_larb17_u0_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUV_R_0), 8, false, 0x2, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(tcyso_r1_larb17_u0_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_TCYSO_R1), 9, true, 0x2, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(drzhno_r9_larb17_u0_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_DRZHNO_R9), 9, true, 0x2, SLAVE_LARB(17)),
|
|
DEFINE_MNODE(yuv_r_1_larb17_u0_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L17_YUV_R_1), 8, false, 0x2, SLAVE_LARB(17)),
|
|
/* LARB19 */
|
|
DEFINE_MNODE(ccui_larb19_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUI), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(ccuo_larb19_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUO), 9, true, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(ccui2_larb19_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUI2), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(ccuo2_larb19_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCUO2), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(dvs_rdma_larb19_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVS_RDMA), 7, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(dvs_wdma_larb19_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVS_WDMA), 8, true, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(dvp_rdma_larb19_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVP_RDMA), 7, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(dvp_wdma_larb19_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DVP_WDMA), 8, true, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(dhze_rdma_larb19_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DHZE_RDMA), 7, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(dhze_wdma_larb19_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_DHZE_WDMA), 8, true, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(ccu_r_0_larb19_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCU_R_0), 8, false, 0x1, SLAVE_LARB(19)),
|
|
DEFINE_MNODE(ccu_r_1_larb19_11,
|
|
MASTER_LARB_PORT(M4U_PORT_L19_CCU_R_1), 8, false, 0x1, SLAVE_LARB(19)),
|
|
/* LARB22 */
|
|
DEFINE_MNODE(wpe_rdma_0_larb11_u1_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_0), 6, false, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(wpe_rdma_1_larb11_u1_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_1), 6, false, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(wpe_rdma_4p_0_larb11_u1_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_4P_0), 6, false, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(wpe_rdma_4p_1_larb11_u1_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_RDMA_4P_1), 6, false, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(pimgi_p1_larb11_u1_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_PIMGI_P1), 7, false, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(pimgbi_p1_larb11_u1_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_PIMGBI_P1), 7, false, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(wpe_wdma_0_larb11_u1_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_WDMA_0), 7, true, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(wpe_wdma_4p_0_larb11_u1_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WPE_WDMA_4P_0), 7, true, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(wrot_p1_larb11_u1_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_WROT_P1), 8, true, 0x1, SLAVE_LARB(22)),
|
|
DEFINE_MNODE(tesco_p1_larb11_u1_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L22_TESCO_P1), 8, true, 0x1, SLAVE_LARB(22)),
|
|
/* LARB23 */
|
|
DEFINE_MNODE(wpe_rdma_0_larb11_u2_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_0), 6, false, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(wpe_rdma_1_larb11_u2_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_1), 6, false, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(wpe_rdma_4p_0_larb11_u2_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_4P_0), 6, false, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(wpe_rdma_4p_1_larb11_u2_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_RDMA_4P_1), 6, false, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(pimgi_p1_larb11_u2_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_PIMGI_P1), 7, false, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(pimgbi_p1_larb11_u2_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_PIMGBI_P1), 7, false, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(wpe_wdma_0_larb11_u2_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_WDMA_0), 7, true, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(wpe_wdma_4p_0_larb11_u2_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WPE_WDMA_4P_0), 7, true, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(wrot_p1_larb11_u2_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_WROT_P1), 8, true, 0x1, SLAVE_LARB(23)),
|
|
DEFINE_MNODE(tesco_p1_larb11_u2_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L23_TESCO_P1), 8, true, 0x1, SLAVE_LARB(23)),
|
|
/* LARB25 */
|
|
DEFINE_MNODE(mraw0_cqi_m1_larb25_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_CQI_M1), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(mraw0_imgo_m1_larb25_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGO_M1), 9, true, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(mraw2_cqi_m1_larb25_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_CQI_M1), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(mraw2_imgo_m1_larb25_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGO_M1), 9, true, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_a_0_larb25_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_0), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_a_1_larb25_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_1), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_a_2_larb25_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_2), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_a_3_larb25_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_3), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_a_4_larb25_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_4), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdao_a_0_larb25_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAO_A_0), 9, true, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_b_0_larb25_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_B_0), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_b_1_larb25_11,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_B_1), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_b_2_larb25_12,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_B_2), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_b_3_larb25_13,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_B_3), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdai_b_4_larb25_14,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAI_B_4), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(pdao_b_0_larb25_15,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_PDAO_B_0), 9, true, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(mraw0_imgbo_m1_larb25_16,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGBO_M1), 9, true, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(mraw2_imgbo_m1_larb25_17,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGBO_M1), 9, true, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(mraw_r_0_larb25_18,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW_R_0), 8, false, 0x2, SLAVE_LARB(25)),
|
|
DEFINE_MNODE(mraw_r_1_larb25_19,
|
|
MASTER_LARB_PORT(M4U_PORT_L25_MRAW_R_1), 8, false, 0x2, SLAVE_LARB(25)),
|
|
/* LARB26 */
|
|
DEFINE_MNODE(mraw1_cqi_m1_larb26_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_CQI_M1), 8, false, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw1_imgo_m1_larb26_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGO_M1), 9, true, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw3_cqi_m1_larb26_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_CQI_M1), 8, false, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw3_imgo_m1_larb26_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGO_M1), 9, true, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw4_cqi_m1_larb26_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW4_CQI_M1), 8, false, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw4_imgo_m1_larb26_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW4_IMGO_M1), 9, true, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw1_imgbo_m1_larb26_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGBO_M1), 9, true, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw3_imgbo_m1_larb26_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGBO_M1), 9, true, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw4_imgbo_m1_larb26_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW4_IMGBO_M1), 9, true, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw_r_0_larb26_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW_R_0), 8, false, 0x1, SLAVE_LARB(26)),
|
|
DEFINE_MNODE(mraw_r_1_larb26_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L26_MRAW_R_1), 8, false, 0x1, SLAVE_LARB(26)),
|
|
/* LARB27 */
|
|
DEFINE_MNODE(adl_ipui_larb27_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_ADL_IPUI), 8, false, 0x2, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(adl_ipuo_larb27_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_ADL_IPUO), 9, true, 0x2, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(adl_ipu3o_larb27_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_ADL_IPU3O), 9, true, 0x2, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(uisp_cqi_u1_larb27_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_UISP_CQI_U1), 8, false, 0x2, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(uisp_imgo_u1_larb27_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_UISP_IMGO_U1), 9, true, 0x2, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(uisp_yuvo_u1_larb27_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_UISP_YUVO_U1), 9, true, 0x2, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(uisp_r_0_larb27_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_UISP_R_0), 8, false, 0x2, SLAVE_LARB(27)),
|
|
DEFINE_MNODE(uisp_r_1_larb27_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L27_UISP_R_1), 8, false, 0x2, SLAVE_LARB(27)),
|
|
/* LARB28 */
|
|
DEFINE_MNODE(imgi_ti_a_larb28_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGI_TI_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(imgi_ti_n_a_larb28_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGI_TI_N_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(imgci_t1_a_larb28_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGCI_T1_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(imgci_t1_n_a_larb28_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_IMGCI_T1_N_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(smti_t1_a_larb28_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTI_T1_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(smti_t4_a_larb28_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTI_T4_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(tncsti_t1_a_larb28_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TNCSTI_T1_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(tncsti_t4_a_larb28_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TNCSTI_T4_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(ltmsti_t1_a_larb28_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_LTMSTI_T1_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(yuvo_t1_a_larb28_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVO_T1_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(yuvbo_t1_a_larb28_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVBO_T1_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(yuvco_t1_a_larb28_11,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVCO_T1_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(yuvo_t2_a_larb28_12,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVO_T2_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(yuvo_t4_a_larb28_13,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_YUVO_T4_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(tncso_t1_a_larb28_14,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TNCSO_T1_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(tmcsto_t1_a_larb28_15,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_TMCSTO_T1_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(smto_t1_a_larb28_16,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTO_T1_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(smto_t4_a_larb28_17,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_SMTO_T4_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(ltmso_t1_a_larb28_18,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_LTMSO_T1_A), 8, true, 0x1, SLAVE_LARB(28)),
|
|
DEFINE_MNODE(dbgo_t1_n_a_larb28_19,
|
|
MASTER_LARB_PORT(M4U_PORT_L28_DBGO_T1_N_A), 7, false, 0x1, SLAVE_LARB(28)),
|
|
/* LARB29 */
|
|
DEFINE_MNODE(camsv_cqi_e2_larb29_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E2), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_cqi_e3_larb29_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E3), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_cqi_e4_larb29_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E4), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_cqi_e5_larb29_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_CQI_E5), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_e2_wdma_larb29_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E2_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_e3_wdma_larb29_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E3_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_e4_wdma_larb29_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E4_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_e5_wdma_larb29_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_E5_WDMA), 9, true, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_r_0_larb29_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_R_0), 8, false, 0x1, SLAVE_LARB(29)),
|
|
DEFINE_MNODE(camsv_r_1_larb29_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_R_1), 8, false, 0x1, SLAVE_LARB(29)),
|
|
/* LARB30 */
|
|
DEFINE_MNODE(cqi_r1_larb16_u1_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_CQI_R1), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(rawi_r2_larb16_u1_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R2), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(rawi_r3_larb16_u1_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R3), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(rawi_r5_larb16_u1_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R5), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(imgo_r1_larb16_u1_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_IMGO_R1), 9, true, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(bpci_r1_larb16_u1_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_BPCI_R1), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(lsci_r1_larb16_u1_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_LSCI_R1), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(ufeo_r1_larb16_u1_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_UFEO_R1), 9, true, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(ltmso_r1_larb16_u1_8,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_LTMSO_R1), 9, true, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(drzb2no_r1_larb16_u1_9,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_DRZB2NO_R1), 9, true, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(aao_r1_larb16_u1_10,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_AAO_R1), 9, true, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(afo_r1_larb16_u1_11,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_AFO_R1), 9, true, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(rgbwi_r1_larb16_u1_12,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RGBWI_R1), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(raw_r_0_larb16_u1_13,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAW_R_0), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(raw_r_1_larb16_u1_14,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAW_R_1), 8, false, 0x2, SLAVE_LARB(30)),
|
|
DEFINE_MNODE(raw_r_2_larb16_u1_15,
|
|
MASTER_LARB_PORT(M4U_PORT_L30_RAW_R_2), 8, false, 0x2, SLAVE_LARB(30)),
|
|
/* LARB34 */
|
|
DEFINE_MNODE(yuvo_r1_larb17_u1_0,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R1), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(yuvo_r3_larb17_u1_1,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R3), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(yuvo_r2_larb17_u1_2,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R2), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(yuvo_r5_larb17_u1_3,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R5), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(yuv_r_0_larb17_u1_4,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUV_R_0), 8, false, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(tcyso_r1_larb17_u1_5,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_TCYSO_R1), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(drzhno_r9_larb17_u1_6,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_DRZHNO_R9), 9, true, 0x1, SLAVE_LARB(34)),
|
|
DEFINE_MNODE(yuv_r_1_larb17_u1_7,
|
|
MASTER_LARB_PORT(M4U_PORT_L34_YUV_R_1), 8, false, 0x1, SLAVE_LARB(34)),
|
|
};
|
|
static const char * const comm_muxes_mt6886[] = { "mm" };
|
|
static const char * const comm_icc_path_names_mt6886[] = { "icc-bw" };
|
|
static const char * const comm_icc_hrt_path_names_mt6886[] = { "icc-hrt-bw" };
|
|
static const struct mtk_mmqos_desc mmqos_desc_mt6886 = {
|
|
.nodes = node_descs_mt6886,
|
|
.num_nodes = ARRAY_SIZE(node_descs_mt6886),
|
|
.comm_muxes = comm_muxes_mt6886,
|
|
.comm_icc_path_names = comm_icc_path_names_mt6886,
|
|
.comm_icc_hrt_path_names = comm_icc_hrt_path_names_mt6886,
|
|
.max_ratio = 64,
|
|
.hrt = {
|
|
.hrt_bw = {6105, 0, 0},
|
|
.hrt_total_bw = 25600, /* Todo: Use DRAMC API 6400*2(channel)*2(io width)*/
|
|
.md_speech_bw = { 6105, 5480},
|
|
.hrt_ratio = {1000, 880, 880, 880}, /* MD, CAM, DISP, MML */
|
|
.blocking = true,
|
|
.emi_ratio = 730,
|
|
},
|
|
.hrt_LPDDR4 = {
|
|
.hrt_bw = {6105, 0, 0},
|
|
.hrt_total_bw = 17064, /* Todo: Use DRAMC API 4266*2(channel)*2(io width)*/
|
|
.md_speech_bw = { 6105, 5480},
|
|
.hrt_ratio = {1000, 880, 880, 880}, /* MD, CAM, DISP, MML */
|
|
.blocking = true,
|
|
.emi_ratio = 800,
|
|
},
|
|
.comm_port_channels = {
|
|
{ 0x1, 0x2, 0x2, 0x1, 0x1, 0x2, 0x1, 0x2, 0x3 },
|
|
},
|
|
.comm_port_hrt_types = {
|
|
{ HRT_MAX_BWL, HRT_MAX_BWL, HRT_NONE, HRT_NONE, HRT_NONE,
|
|
HRT_NONE, HRT_CAM, HRT_CAM, HRT_DISP },
|
|
},
|
|
//.dual_pipe_larbs = { SLAVE_LARB(1), SLAVE_LARB(20) },
|
|
.mmqos_state = MMQOS_ENABLE | COMM_OSTDL_ENABLE | BWL_MIN_ENABLE,
|
|
.report_bw_larbs = { SLAVE_LARB(9), SLAVE_LARB(10),
|
|
SLAVE_LARB(15), SLAVE_LARB(22) },
|
|
};
|
|
static const struct of_device_id mtk_mmqos_mt6886_of_ids[] = {
|
|
{
|
|
.compatible = "mediatek,mt6886-mmqos",
|
|
.data = &mmqos_desc_mt6886,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_mmqos_mt6886_of_ids);
|
|
static struct platform_driver mtk_mmqos_mt6886_driver = {
|
|
.probe = mtk_mmqos_probe,
|
|
.remove = mtk_mmqos_remove,
|
|
.driver = {
|
|
.name = "mtk-mt6886-mmqos",
|
|
.of_match_table = mtk_mmqos_mt6886_of_ids,
|
|
},
|
|
};
|
|
module_platform_driver(mtk_mmqos_mt6886_driver);
|
|
MODULE_LICENSE("GPL v2");
|