474 lines
15 KiB
C
474 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#ifndef __GPUFREQ_V2_H__
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#define __GPUFREQ_V2_H__
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#include <linux/bits.h>
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#include <uapi/asm-generic/errno-base.h>
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/**************************************************
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* Definition
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**************************************************/
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#define GPUFREQ_UNREFERENCED(param) ((void)(param))
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#define GPUFREQ_DEBUG_ENABLE (0)
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#define GPUFREQ_TRACE_ENABLE (0)
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#define GPUFREQ_FORCE_WDT_ENABLE (0)
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#define GPUFERQ_TAG "[GPU/FREQ]"
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#define GPUFREQ_TRACE_TAG "[GPU/TRACE]"
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#define GPUFREQ_MEM_TABLE_IDX (1)
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#define GPUFREQ_MAGIC_NUMBER (0xBABADADA)
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#define GPUFREQ_MAX_OPP_NUM (70)
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#define GPUFREQ_MAX_ADJ_NUM (10)
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#define GPUFREQ_MAX_REG_NUM (70)
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#define GPUFREQ_MAX_GPM3_NUM (20)
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/**************************************************
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* GPUFREQ Log Setting
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**************************************************/
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#define GPUFREQ_LOGE(fmt, args...) \
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pr_err(GPUFERQ_TAG"[ERROR]@%s: "fmt"\n", __func__, ##args)
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#define GPUFREQ_LOGW(fmt, args...) \
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pr_debug(GPUFERQ_TAG"[WARN]@%s: "fmt"\n", __func__, ##args)
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#define GPUFREQ_LOGI(fmt, args...) \
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pr_info(GPUFERQ_TAG"[INFO]@%s: "fmt"\n", __func__, ##args)
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#if GPUFREQ_DEBUG_ENABLE
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#define GPUFREQ_LOGD(fmt, args...) \
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pr_info(GPUFERQ_TAG"[DEBUG]@%s: "fmt"\n", __func__, ##args)
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#else
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#define GPUFREQ_LOGD(fmt, args...) {}
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#endif /* GPUFREQ_DEBUG_ENABLE */
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#if GPUFREQ_TRACE_ENABLE
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#define GPUFREQ_TRACE_START(fmt, args...) \
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pr_info(GPUFREQ_TRACE_TAG" + %s("fmt")\n", __func__, ##args)
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#define GPUFREQ_TRACE_END(fmt, args...) \
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pr_info(GPUFREQ_TRACE_TAG" - %s("fmt")\n", __func__, ##args)
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#else
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#define GPUFREQ_TRACE_START(fmt, args...) {}
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#define GPUFREQ_TRACE_END(fmt, args...) {}
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#endif /* GPUFREQ_TRACE_ENABLE */
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/**************************************************
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* Enumeration
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**************************************************/
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enum gpufreq_return {
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GPUFREQ_HW_LIMIT = 1,
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GPUFREQ_SUCCESS = 0,
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GPUFREQ_EINVAL = -EINVAL, /* -22 */
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GPUFREQ_ENOMEM = -ENOMEM, /* -12 */
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GPUFREQ_ENOENT = -ENOENT, /* -2 */
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GPUFREQ_ENODEV = -ENODEV, /* -19 */
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};
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enum gpufreq_posdiv {
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POSDIV_POWER_1 = 0,
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POSDIV_POWER_2 = 1,
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POSDIV_POWER_4,
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POSDIV_POWER_8,
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POSDIV_POWER_16,
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};
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enum gpufreq_dvfs_state {
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DVFS_FREE = 0, /* 0000 0000 */
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DVFS_DISABLE = BIT(0), /* 0000 0001 */
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DVFS_POWEROFF = BIT(1), /* 0000 0010 */
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DVFS_FIX_OPP = BIT(2), /* 0000 0100 */
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DVFS_FIX_FREQ_VOLT = BIT(3), /* 0000 1000 */
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DVFS_AGING_KEEP = BIT(4), /* 0001 0000 */
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DVFS_SLEEP = BIT(5), /* 0010 0000 */
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DVFS_MSSV_TEST = BIT(6), /* 0100 0000 */
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};
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enum gpufreq_target {
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TARGET_DEFAULT = 0,
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TARGET_GPU = 1,
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TARGET_STACK,
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TARGET_INVALID,
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};
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enum gpufreq_power_state {
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POWER_OFF = 0,
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POWER_ON,
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};
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enum gpufreq_config_target {
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CONFIG_TARGET_INVALID = -1,
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CONFIG_TEST_MODE = 0,
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CONFIG_STRESS_TEST = 1,
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CONFIG_MARGIN = 2,
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CONFIG_GPM1 = 3,
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CONFIG_GPM3 = 4,
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CONFIG_DFD = 5,
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CONFIG_IMAX_STACK = 6,
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CONFIG_IMAX_SRAM = 7,
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CONFIG_PMAX_STACK = 8,
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CONFIG_DYN_STACK = 9,
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CONFIG_DYN_SRAM_GPU = 10,
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CONFIG_DYN_SRAM_STACK = 11,
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CONFIG_IPS = 12,
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CONFIG_OCL_TIMESTAMP = 13,
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CONFIG_FAKE_MTCMOS_CTRL = 14,
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CONFIG_MCUETM_CLK = 15,
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CONFIG_PTP3 = 16,
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};
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enum gpufreq_config_value {
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CONFIG_VAL_INVALID = -1,
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FEAT_DISABLE = 0,
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FEAT_ENABLE = 1,
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DFD_FORCE_DUMP = 2,
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IPS_VMIN_GET = 3,
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};
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enum gpuppm_reserved_idx {
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GPUPPM_DEFAULT_IDX = -1,
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GPUPPM_RESET_IDX = -2,
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GPUPPM_KEEP_IDX = -3,
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};
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enum gpuppm_limiter {
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LIMIT_SEGMENT = 0,
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LIMIT_DEBUG = 1,
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LIMIT_GPM3 = 2,
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LIMIT_TEMPER_COMP = 3,
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LIMIT_PEAK_POWER_AP = 4,
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LIMIT_PEAK_POWER_EB = 5,
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LIMIT_THERMAL_AP = 6,
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LIMIT_THERMAL_EB = 7,
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LIMIT_SRAMRC = 8,
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LIMIT_BATT_OC = 9,
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LIMIT_BATT_PERCENT = 10,
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LIMIT_LOW_BATT = 11,
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LIMIT_PBM = 12,
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LIMIT_APIBOOST = 13,
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LIMIT_FPSGO = 14,
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LIMIT_NUM = 15,
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};
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enum gpuppm_limit_type {
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GPUPPM_CEILING = 0,
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GPUPPM_FLOOR = 1,
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GPUPPM_INVALID,
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};
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/**************************************************
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* Structure
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**************************************************/
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struct gpufreq_opp_info {
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unsigned int freq; /* KHz */
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unsigned int volt; /* mV x 100 */
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unsigned int vsram; /* mV x 100 */
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enum gpufreq_posdiv posdiv;
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unsigned int margin; /* mV x 100 */
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unsigned int power; /* mW */
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};
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struct gpufreq_adj_info {
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int oppidx;
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unsigned int freq;
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unsigned int volt;
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unsigned int vsram;
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};
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struct gpufreq_core_mask_info {
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unsigned int num;
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unsigned int mask;
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};
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struct gpuppm_limit_info {
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unsigned int limiter;
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char name[20];
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unsigned int priority;
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int ceiling;
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unsigned int c_enable;
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int floor;
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unsigned int f_enable;
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};
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struct gpufreq_asensor_info {
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unsigned int efuse1;
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unsigned int efuse2;
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unsigned int efuse3;
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unsigned int efuse4;
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unsigned int efuse1_addr;
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unsigned int efuse2_addr;
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unsigned int efuse3_addr;
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unsigned int efuse4_addr;
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unsigned int a_t0_efuse1;
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unsigned int a_t0_efuse2;
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unsigned int a_t0_efuse3;
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unsigned int a_t0_efuse4;
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unsigned int a_tn_sensor1;
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unsigned int a_tn_sensor2;
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unsigned int a_tn_sensor3;
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unsigned int a_tn_sensor4;
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int a_diff1;
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int a_diff2;
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int a_diff3;
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int a_diff4;
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int tj_max;
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unsigned int aging_table_idx;
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unsigned int aging_table_idx_agrresive;
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unsigned int leakage_power;
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unsigned int lvts5_0_y_temperature;
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};
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struct gpufreq_ips_info {
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unsigned int vmin_reg_val;
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unsigned int vmin_val;
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unsigned int autok_result;
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unsigned int autok_trim0;
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unsigned int autok_trim1;
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unsigned int autok_trim2;
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};
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struct gpufreq_gpm3_info {
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int temper;
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int ceiling;
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unsigned int i_stack;
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unsigned int i_sram;
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unsigned int p_stack;
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};
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struct gpufreq_reg_info {
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unsigned int addr;
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unsigned int val;
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};
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/**************************************************
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* Shared Status
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**************************************************/
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#define GPUFREQ_SHARED_STATUS_SIZE (sizeof(struct gpufreq_shared_status))
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struct gpufreq_shared_status {
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int magic;
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int cur_oppidx_gpu;
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int cur_oppidx_stack;
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int opp_num_gpu;
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int opp_num_stack;
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int signed_opp_num_gpu;
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int signed_opp_num_stack;
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int power_count;
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int buck_count;
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int mtcmos_count;
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int cg_count;
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int active_count;
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int temperature;
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int temper_comp_norm_gpu;
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int temper_comp_high_gpu;
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int temper_comp_norm_stack;
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int temper_comp_high_stack;
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unsigned int cur_fgpu;
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unsigned int cur_fstack;
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unsigned int cur_con1_fgpu;
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unsigned int cur_con1_fstack;
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unsigned int cur_fmeter_fgpu;
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unsigned int cur_fmeter_fstack;
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unsigned int cur_vgpu;
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unsigned int cur_vstack;
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unsigned int cur_vsram_gpu;
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unsigned int cur_vsram_stack;
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unsigned int cur_regulator_vgpu;
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unsigned int cur_regulator_vstack;
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unsigned int cur_regulator_vsram_gpu;
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unsigned int cur_regulator_vsram_stack;
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unsigned int cur_power_gpu;
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unsigned int cur_power_stack;
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unsigned int max_power_gpu;
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unsigned int max_power_stack;
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unsigned int min_power_gpu;
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unsigned int min_power_stack;
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unsigned int lkg_rt_info_gpu;
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unsigned int lkg_rt_info_stack;
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unsigned int lkg_rt_info_sram;
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unsigned int lkg_ht_info_gpu;
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unsigned int lkg_ht_info_stack;
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unsigned int lkg_ht_info_sram;
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unsigned int cur_ceiling;
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unsigned int cur_floor;
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unsigned int cur_c_limiter;
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unsigned int cur_f_limiter;
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unsigned int cur_c_priority;
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unsigned int cur_f_priority;
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unsigned int power_control;
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unsigned int active_idle_control;
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unsigned int dvfs_state;
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unsigned int shader_present;
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unsigned int asensor_enable;
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unsigned int aging_load;
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unsigned int aging_margin;
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unsigned int avs_enable;
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unsigned int avs_margin;
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unsigned int sb_version;
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unsigned int ptp_version;
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unsigned int dbg_version;
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unsigned int gpm1_mode;
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unsigned int gpm3_mode;
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unsigned int dual_buck;
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unsigned int segment_id;
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unsigned int power_time_h;
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unsigned int power_time_l;
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unsigned int mfg_pwr_status;
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unsigned int stress_test;
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unsigned int test_mode;
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unsigned int ips_mode;
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unsigned int ptp3_mode;
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unsigned int temper_comp_mode;
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unsigned int ht_temper_comp_mode;
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struct gpufreq_reg_info reg_mfgsys[GPUFREQ_MAX_REG_NUM];
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struct gpufreq_reg_info reg_stack_sel;
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struct gpufreq_reg_info reg_del_sel;
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struct gpufreq_asensor_info asensor_info;
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struct gpufreq_ips_info ips_info;
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struct gpufreq_opp_info working_table_gpu[GPUFREQ_MAX_OPP_NUM];
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struct gpufreq_opp_info working_table_stack[GPUFREQ_MAX_OPP_NUM];
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struct gpufreq_opp_info signed_table_gpu[GPUFREQ_MAX_OPP_NUM];
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struct gpufreq_opp_info signed_table_stack[GPUFREQ_MAX_OPP_NUM];
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struct gpuppm_limit_info limit_table[LIMIT_NUM];
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struct gpufreq_adj_info aging_table_gpu[GPUFREQ_MAX_ADJ_NUM];
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struct gpufreq_adj_info aging_table_stack[GPUFREQ_MAX_ADJ_NUM];
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struct gpufreq_adj_info avs_table_gpu[GPUFREQ_MAX_ADJ_NUM];
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struct gpufreq_adj_info avs_table_stack[GPUFREQ_MAX_ADJ_NUM];
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struct gpufreq_gpm3_info gpm3_table[GPUFREQ_MAX_GPM3_NUM];
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};
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/**************************************************
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* Platform Implementation
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**************************************************/
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struct gpufreq_platform_fp {
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/* Common */
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unsigned int (*power_ctrl_enable)(void);
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unsigned int (*active_idle_ctrl_enable)(void);
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unsigned int (*get_power_state)(void);
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unsigned int (*get_dvfs_state)(void);
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unsigned int (*get_shader_present)(void);
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unsigned int (*get_segment_id)(void);
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int (*power_control)(enum gpufreq_power_state power);
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int (*active_idle_control)(enum gpufreq_power_state power);
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void (*dump_infra_status)(void);
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void (*update_debug_opp_info)(void);
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void (*set_mfgsys_config)(enum gpufreq_config_target target, enum gpufreq_config_value val);
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struct gpufreq_core_mask_info *(*get_core_mask_table)(void);
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unsigned int (*get_core_num)(void);
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void (*pdca_config)(enum gpufreq_power_state power);
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void (*set_shared_status)(struct gpufreq_shared_status *shared_status);
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int (*mssv_commit)(unsigned int target, unsigned int val);
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void (*update_temperature)(unsigned int instant_dvfs);
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/* GPU */
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unsigned int (*get_cur_fgpu)(void);
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unsigned int (*get_cur_vgpu)(void);
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unsigned int (*get_cur_pgpu)(void);
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unsigned int (*get_max_pgpu)(void);
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unsigned int (*get_min_pgpu)(void);
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int (*get_cur_idx_gpu)(void);
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int (*get_opp_num_gpu)(void);
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int (*get_signed_opp_num_gpu)(void);
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unsigned int (*get_fgpu_by_idx)(int oppidx);
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unsigned int (*get_pgpu_by_idx)(int oppidx);
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int (*get_idx_by_fgpu)(unsigned int freq);
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unsigned int (*get_lkg_pgpu)(unsigned int volt);
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unsigned int (*get_dyn_pgpu)(unsigned int freq, unsigned int volt);
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int (*generic_commit_gpu)(int target_oppidx, enum gpufreq_dvfs_state key);
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int (*fix_target_oppidx_gpu)(int oppidx);
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int (*fix_custom_freq_volt_gpu)(unsigned int freq, unsigned int volt);
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/* SRAM */
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unsigned int (*get_cur_vsram_gpu)(void);
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unsigned int (*get_cur_vsram_stack)(void);
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/* STACK */
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unsigned int (*get_cur_fstack)(void);
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unsigned int (*get_cur_vstack)(void);
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unsigned int (*get_cur_pstack)(void);
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unsigned int (*get_max_pstack)(void);
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unsigned int (*get_min_pstack)(void);
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int (*get_cur_idx_stack)(void);
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int (*get_opp_num_stack)(void);
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int (*get_signed_opp_num_stack)(void);
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unsigned int (*get_fstack_by_idx)(int oppidx);
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unsigned int (*get_pstack_by_idx)(int oppidx);
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int (*get_idx_by_fstack)(unsigned int freq);
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unsigned int (*get_lkg_pstack)(unsigned int volt);
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unsigned int (*get_dyn_pstack)(unsigned int freq, unsigned int volt);
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int (*generic_commit_stack)(int target_oppidx, enum gpufreq_dvfs_state key);
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int (*fix_target_oppidx_stack)(int oppidx);
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int (*fix_custom_freq_volt_stack)(unsigned int freq, unsigned int volt);
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};
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struct gpuppm_platform_fp {
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int (*limited_commit)(enum gpufreq_target target, int oppidx);
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int (*set_limit)(enum gpufreq_target target, enum gpuppm_limiter limiter,
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int ceiling_info, int floor_info);
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int (*switch_limit)(enum gpufreq_target target, enum gpuppm_limiter limiter,
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int c_enable, int f_enable);
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int (*get_ceiling)(void);
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int (*get_floor)(void);
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unsigned int (*get_c_limiter)(void);
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unsigned int (*get_f_limiter)(void);
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void (*set_shared_status)(struct gpufreq_shared_status *shared_status);
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};
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/**************************************************
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* GPU HAL Interface
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**************************************************/
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extern int (*mtk_get_gpu_limit_index_fp)(enum gpufreq_target target,
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enum gpuppm_limit_type limit);
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extern unsigned int (*mtk_get_gpu_limiter_fp)(enum gpufreq_target target,
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enum gpuppm_limit_type limit);
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extern unsigned int (*mtk_get_gpu_cur_freq_fp)(enum gpufreq_target target);
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extern int (*mtk_get_gpu_cur_oppidx_fp)(enum gpufreq_target target);
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/**************************************************
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* External Function
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**************************************************/
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/* Common */
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unsigned int gpufreq_bringup(void);
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unsigned int gpufreq_power_ctrl_enable(void);
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unsigned int gpufreq_active_idle_ctrl_enable(void);
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unsigned int gpufreq_get_power_state(void);
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unsigned int gpufreq_get_dvfs_state(void);
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unsigned int gpufreq_get_shader_present(void);
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unsigned int gpufreq_get_segment_id(void);
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void gpufreq_set_ocl_timestamp(void);
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void gpufreq_dump_infra_status(void);
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unsigned int gpufreq_get_cur_freq(enum gpufreq_target target);
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unsigned int gpufreq_get_cur_volt(enum gpufreq_target target);
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unsigned int gpufreq_get_cur_vsram(enum gpufreq_target target);
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unsigned int gpufreq_get_cur_power(enum gpufreq_target target);
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unsigned int gpufreq_get_max_power(enum gpufreq_target target);
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unsigned int gpufreq_get_min_power(enum gpufreq_target target);
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int gpufreq_get_cur_oppidx(enum gpufreq_target target);
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int gpufreq_get_opp_num(enum gpufreq_target target);
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unsigned int gpufreq_get_freq_by_idx(enum gpufreq_target target, int oppidx);
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unsigned int gpufreq_get_power_by_idx(enum gpufreq_target target, int oppidx);
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int gpufreq_get_oppidx_by_freq(enum gpufreq_target target, unsigned int freq);
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unsigned int gpufreq_get_leakage_power(enum gpufreq_target target, unsigned int volt);
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unsigned int gpufreq_get_dynamic_power(enum gpufreq_target target,
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unsigned int freq, unsigned int volt);
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int gpufreq_set_limit(enum gpufreq_target target,
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enum gpuppm_limiter limiter, int ceiling_info, int floor_info);
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int gpufreq_get_cur_limit_idx(enum gpufreq_target target,enum gpuppm_limit_type limit);
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unsigned int gpufreq_get_cur_limiter(enum gpufreq_target target, enum gpuppm_limit_type limit);
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int gpufreq_power_control(enum gpufreq_power_state power, int oppidx);
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int gpufreq_active_idle_control(enum gpufreq_power_state power);
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int gpufreq_commit(enum gpufreq_target target, int oppidx);
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struct gpufreq_core_mask_info *gpufreq_get_core_mask_table(void);
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unsigned int gpufreq_get_core_num(void);
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void gpufreq_pdca_config(enum gpufreq_power_state power);
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void gpufreq_fake_mtcmos_control(enum gpufreq_power_state power);
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void gpufreq_register_gpufreq_fp(struct gpufreq_platform_fp *platform_fp);
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void gpufreq_register_gpuppm_fp(struct gpuppm_platform_fp *platform_fp);
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/* Debug */
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int gpufreq_update_debug_opp_info(void);
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const struct gpufreq_opp_info *gpufreq_get_working_table(enum gpufreq_target target);
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int gpufreq_switch_limit(enum gpufreq_target target,
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enum gpuppm_limiter limiter, int c_enable, int f_enable);
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int gpufreq_fix_target_oppidx(enum gpufreq_target target, int oppidx);
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int gpufreq_fix_custom_freq_volt(enum gpufreq_target target,
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unsigned int freq, unsigned int volt);
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int gpufreq_set_mfgsys_config(enum gpufreq_config_target target, enum gpufreq_config_value val);
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int gpufreq_mssv_commit(unsigned int target, unsigned int val);
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#endif /* __GPUFREQ_V2_H__ */
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