532 lines
22 KiB
C
532 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#ifndef __GPUFREQ_MT6985_H__
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#define __GPUFREQ_MT6985_H__
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/**************************************************
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* GPUFREQ Config
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**************************************************/
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/* 0 -> power on once then never off and disable DDK power on/off callback */
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#define GPUFREQ_POWER_CTRL_ENABLE (1)
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/* 0 -> disable DDK runtime active-idle callback */
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#define GPUFREQ_ACTIVE_IDLE_CTRL_ENABLE (0)
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/*
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* (DVFS_ENABLE, CUST_INIT)
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* (1, 1) -> DVFS enable and init to CUST_INIT_OPPIDX
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* (1, 0) -> DVFS enable
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* (0, 1) -> DVFS disable but init to CUST_INIT_OPPIDX (do DVFS only onces)
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* (0, 0) -> DVFS disable
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*/
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#define GPUFREQ_DVFS_ENABLE (1)
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#define GPUFREQ_CUST_INIT_ENABLE (0)
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#define GPUFREQ_CUST_INIT_OPPIDX (0)
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/* MFGSYS Feature */
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#define GPUFREQ_HWDCM_ENABLE (1)
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#define GPUFREQ_ACP_ENABLE (1)
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#define GPUFREQ_PDCA_ENABLE (1)
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#define GPUFREQ_GPM1_ENABLE (1)
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#define GPUFREQ_GPM3_ENABLE (0)
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#define GPUFREQ_MERGER_ENABLE (1)
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#define GPUFREQ_AXUSER_PREULTRA_ENABLE (1)
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#define GPUFREQ_DFD_ENABLE (0)
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#define GPUFREQ_AVS_ENABLE (0)
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#define GPUFREQ_ASENSOR_ENABLE (0)
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#define GPUFREQ_IPS_ENABLE (0)
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#define GPUFREQ_SELF_CTRL_MTCMOS (0)
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#define GPUFREQ_SHARED_STATUS_REG (0)
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/**************************************************
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* Clock Setting
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**************************************************/
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#define POSDIV_2_MAX_FREQ (1900000) /* KHz */
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#define POSDIV_2_MIN_FREQ (750000) /* KHz */
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#define POSDIV_4_MAX_FREQ (950000) /* KHz */
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#define POSDIV_4_MIN_FREQ (375000) /* KHz */
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#define POSDIV_8_MAX_FREQ (475000) /* KHz */
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#define POSDIV_8_MIN_FREQ (187500) /* KHz */
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#define POSDIV_16_MAX_FREQ (237500) /* KHz */
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#define POSDIV_16_MIN_FREQ (125000) /* KHz */
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#define POSDIV_SHIFT (24) /* bit */
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#define DDS_SHIFT (14) /* bit */
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#define MFGPLL_FIN (26) /* MHz */
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#define MFG_INT0_SEL_MASK (BIT(16)) /* [16] */
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#define MFGSC_INT1_SEL_MASK (BIT(17)) /* [17] */
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#define MFG_REF_SEL_MASK (GENMASK(17, 16)) /* [17:16] */
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#define MFGSC_REF_SEL_MASK (GENMASK(25, 24)) /* [25:24] */
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#define FREQ_ROUNDUP_TO_10(freq) ((freq % 10) ? (freq - (freq % 10) + 10) : freq)
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/**************************************************
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* Frequency Hopping Setting
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**************************************************/
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#define GPUFREQ_FHCTL_ENABLE (0)
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#define MFG_PLL_NAME "mfg_ao_mfgpll"
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#define MFGSC_PLL_NAME "mfgsc_ao_mfgscpll"
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/**************************************************
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* MTCMOS Setting
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**************************************************/
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#define GPUFREQ_CHECK_MFG_PWR_STATUS (0)
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#define MFG_0_1_PWR_MASK (GENMASK(1, 0))
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#define MFG_0_19_PWR_MASK (GENMASK(19, 0))
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#define MFG_1_19_PWR_MASK (GENMASK(19, 1))
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#define MFG_0_1_PWR_STATUS \
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(((readl(SPM_XPU_PWR_STATUS) & BIT(1)) >> 1) | \
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(((readl(MFG_RPC_MFG1_PWR_CON) & BIT(30)) >> 30) << 1))
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#define MFG_0_19_PWR_STATUS \
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(((readl(SPM_XPU_PWR_STATUS) & BIT(1)) >> 1) | \
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(((readl(MFG_RPC_MFG1_PWR_CON) & BIT(30)) >> 30) << 1) | \
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(((readl(MFG_RPC_MFG2_PWR_CON) & BIT(30)) >> 30) << 2) | \
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(((readl(MFG_RPC_MFG3_PWR_CON) & BIT(30)) >> 30) << 3) | \
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(((readl(MFG_RPC_MFG4_PWR_CON) & BIT(30)) >> 30) << 4) | \
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(((readl(MFG_RPC_MFG5_PWR_CON) & BIT(30)) >> 30) << 5) | \
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(((readl(MFG_RPC_MFG6_PWR_CON) & BIT(30)) >> 30) << 6) | \
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(((readl(MFG_RPC_MFG7_PWR_CON) & BIT(30)) >> 30) << 7) | \
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(((readl(MFG_RPC_MFG8_PWR_CON) & BIT(30)) >> 30) << 8) | \
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(((readl(MFG_RPC_MFG9_PWR_CON) & BIT(30)) >> 30) << 9) | \
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(((readl(MFG_RPC_MFG10_PWR_CON) & BIT(30)) >> 30) << 10) | \
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(((readl(MFG_RPC_MFG11_PWR_CON) & BIT(30)) >> 30) << 11) | \
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(((readl(MFG_RPC_MFG12_PWR_CON) & BIT(30)) >> 30) << 12) | \
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(((readl(MFG_RPC_MFG13_PWR_CON) & BIT(30)) >> 30) << 13) | \
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(((readl(MFG_RPC_MFG14_PWR_CON) & BIT(30)) >> 30) << 14) | \
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(((readl(MFG_RPC_MFG15_PWR_CON) & BIT(30)) >> 30) << 15) | \
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(((readl(MFG_RPC_MFG16_PWR_CON) & BIT(30)) >> 30) << 16) | \
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(((readl(MFG_RPC_MFG17_PWR_CON) & BIT(30)) >> 30) << 17) | \
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(((readl(MFG_RPC_MFG18_PWR_CON) & BIT(30)) >> 30) << 18) | \
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(((readl(MFG_RPC_MFG19_PWR_CON) & BIT(30)) >> 30) << 19))
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/**************************************************
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* Shader Core Setting
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**************************************************/
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#define MFG3_SHADER_STACK0 (T0C0 | T0C1) /* MFG9, MFG12 */
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#define MFG4_SHADER_STACK1 (T1C0 | T1C1) /* MFG10, MFG13 */
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#define MFG5_SHADER_STACK2 (T2C0 | T2C1) /* MFG11, MFG14 */
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#define MFG6_SHADER_STACK4 (T4C0) /* MFG15 */
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#define MFG7_SHADER_STACK5 (T5C0 | T5C1) /* MFG16, MFG18 */
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#define MFG8_SHADER_STACK6 (T6C0 | T6C1) /* MFG17, MFG19 */
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#define GPU_SHADER_PRESENT_1 \
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(MFG6_SHADER_STACK4)
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#define GPU_SHADER_PRESENT_2 \
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(MFG3_SHADER_STACK0)
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#define GPU_SHADER_PRESENT_3 \
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(MFG3_SHADER_STACK0 | MFG6_SHADER_STACK4)
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#define GPU_SHADER_PRESENT_4 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1)
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#define GPU_SHADER_PRESENT_5 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1 | MFG6_SHADER_STACK4)
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#define GPU_SHADER_PRESENT_6 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1 | MFG5_SHADER_STACK2)
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#define GPU_SHADER_PRESENT_7 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1 | MFG5_SHADER_STACK2 | \
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MFG6_SHADER_STACK4)
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#define GPU_SHADER_PRESENT_8 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1 | MFG5_SHADER_STACK2 | \
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MFG7_SHADER_STACK5)
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#define GPU_SHADER_PRESENT_9 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1 | MFG5_SHADER_STACK2 | \
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MFG6_SHADER_STACK4 | MFG7_SHADER_STACK5)
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#define GPU_SHADER_PRESENT_10 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1 | MFG5_SHADER_STACK2 | \
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MFG7_SHADER_STACK5 | MFG8_SHADER_STACK6)
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#define GPU_SHADER_PRESENT_11 \
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(MFG3_SHADER_STACK0 | MFG4_SHADER_STACK1 | MFG5_SHADER_STACK2 | \
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MFG6_SHADER_STACK4 | MFG7_SHADER_STACK5 | MFG8_SHADER_STACK6)
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#define SHADER_CORE_NUM (11)
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struct gpufreq_core_mask_info g_core_mask_table[] = {
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{11, GPU_SHADER_PRESENT_11},
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{10, GPU_SHADER_PRESENT_10},
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{9, GPU_SHADER_PRESENT_9},
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{8, GPU_SHADER_PRESENT_8},
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{7, GPU_SHADER_PRESENT_7},
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{6, GPU_SHADER_PRESENT_6},
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{5, GPU_SHADER_PRESENT_5},
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{4, GPU_SHADER_PRESENT_4},
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{3, GPU_SHADER_PRESENT_3},
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{2, GPU_SHADER_PRESENT_2},
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{1, GPU_SHADER_PRESENT_1},
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};
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/**************************************************
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* Dynamic Power Setting
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**************************************************/
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#define GPU_DYN_REF_POWER (826) /* mW */
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#define GPU_DYN_REF_FREQ (1000000) /* KHz */
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#define GPU_DYN_REF_VOLT (90000) /* mV x 100 */
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#define STACK_DYN_REF_POWER (4329) /* mW */
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#define STACK_DYN_REF_FREQ (981000) /* KHz */
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#define STACK_DYN_REF_VOLT (80000) /* mV x 100 */
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/**************************************************
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* PMIC Setting
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**************************************************/
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/*
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* PMIC hardware range:
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* VGPU 0.3 - 1.19375 V (MT6373_VBUCK4)
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* VSTACK 0.3 - 1.19375 V (MT6373_VBUCK2)
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* VSRAM 0.3 - 1.19375 V (MT6373_VSRAM_DIGRF_AIF)
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*/
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#define VGPU_MAX_VOLT (119375) /* mV x 100 */
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#define VGPU_MIN_VOLT (30000) /* mV x 100 */
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#define VSTACK_MAX_VOLT (119375) /* mV x 100 */
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#define VSTACK_MIN_VOLT (30000) /* mV x 100 */
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#define VSRAM_MAX_VOLT (119375) /* mV x 100 */
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#define VSRAM_MIN_VOLT (30000) /* mV x 100 */
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#define VSRAM_THRESH (75000) /* mV x 100 */
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#define PMIC_STEP (625) /* mV x 100 */
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#define VOLT_NORMALIZATION(volt) ((volt % 625) ? (volt - (volt % 625) + 625) : volt)
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/**************************************************
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* Power Throttling Setting
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**************************************************/
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#define GPUFREQ_BATT_OC_ENABLE (0)
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#define GPUFREQ_BATT_PERCENT_ENABLE (0)
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#define GPUFREQ_LOW_BATT_ENABLE (0)
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#define GPUFREQ_BATT_OC_FREQ (484000)
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#define GPUFREQ_BATT_PERCENT_IDX (0)
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#define GPUFREQ_LOW_BATT_FREQ (484000)
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/**************************************************
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* Aging Sensor Setting
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**************************************************/
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#define GPUFREQ_AGING_KEEP_FGPU (945000)
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#define GPUFREQ_AGING_KEEP_VGPU (82500)
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#define GPUFREQ_AGING_KEEP_FSTACK (600000)
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#define GPUFREQ_AGING_KEEP_VSTACK (65000)
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#define GPUFREQ_AGING_KEEP_VSRAM (82500)
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#define GPUFREQ_AGING_LKG_VSTACK (70000)
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#define GPUFREQ_AGING_GAP_MIN (-3)
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#define GPUFREQ_AGING_GAP_1 (2)
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#define GPUFREQ_AGING_GAP_2 (4)
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#define GPUFREQ_AGING_GAP_3 (6)
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#define GPUFREQ_AGING_MAX_TABLE_IDX (1)
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#define GPUFREQ_AGING_MOST_AGRRESIVE (0)
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/**************************************************
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* DVFS Constraint Setting
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**************************************************/
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#define STACK_SEL_OPP (20)
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#define SRAM_DEL_SEL_OPP (36)
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#define CONSTRAINT_OPP_0 (0)
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#define CONSTRAINT_OPP_1 (20)
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#define CONSTRAINT_OPP_2 (36)
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#define CONSTRAINT_OPP_3 (48)
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#define CONSTRAINT_VSRAM_PARK (-1)
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#define NUM_CONSTRAINT_IDX ARRAY_SIZE(g_constraint_idx)
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static const int g_constraint_idx[] = {
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CONSTRAINT_OPP_0,
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CONSTRAINT_OPP_1,
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CONSTRAINT_VSRAM_PARK,
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CONSTRAINT_OPP_2,
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CONSTRAINT_OPP_3,
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};
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/**************************************************
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* DFD Setting
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**************************************************/
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#define MFG_DEBUGMON_CON_00_ENABLE (0xFFFFFFFF)
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#define MFG_DFD_CON_0_ENABLE (0x0F101100)
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#define MFG_DFD_CON_1_ENABLE (0x00000100)
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#define MFG_DFD_CON_2_ENABLE (0x00000000)
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#define MFG_DFD_CON_3_ENABLE (0x0010001F)
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#define MFG_DFD_CON_4_ENABLE (0x00000000)
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#define MFG_DFD_CON_5_ENABLE (0x00000000)
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#define MFG_DFD_CON_6_ENABLE (0x00000000)
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#define MFG_DFD_CON_7_ENABLE (0x00000000)
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#define MFG_DFD_CON_8_ENABLE (0x00000000)
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#define MFG_DFD_CON_9_ENABLE (0x00000000)
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#define MFG_DFD_CON_10_ENABLE (0x00000000)
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#define MFG_DFD_CON_11_ENABLE (0x00000000)
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/**************************************************
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* Leakage Power Setting
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**************************************************/
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#define GPU_LKG_POWER (30)
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#define STACK_LKG_POWER (30)
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/**************************************************
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* Enumeration
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**************************************************/
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enum gpufreq_segment {
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MT6985_SEGMENT = 0,
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};
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enum gpufreq_clk_src {
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CLOCK_SUB = 0,
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CLOCK_MAIN,
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};
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enum gpufreq_sema_op {
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SEMA_RELEASE = 0,
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SEMA_ACQUIRE,
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};
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enum gpufreq_opp_direct {
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SCALE_DOWN = 0,
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SCALE_UP,
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SCALE_STAY,
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};
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/**************************************************
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* Structure
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**************************************************/
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struct gpufreq_pmic_info {
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struct regulator *reg_vgpu;
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struct regulator *reg_vstack;
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struct regulator *reg_vsram;
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};
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struct gpufreq_clk_info {
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struct clk *clk_mux;
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struct clk *clk_main_parent;
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struct clk *clk_sub_parent;
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struct clk *clk_sc_mux;
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struct clk *clk_sc_main_parent;
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struct clk *clk_sc_sub_parent;
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};
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struct gpufreq_mtcmos_info {
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struct device *mfg1_dev; /* CM7, PDCA */
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#if !GPUFREQ_PDCA_ENABLE
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struct device *mfg2_dev; /* L2, MMU, Tiler */
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struct device *mfg3_dev; /* ST0 */
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struct device *mfg4_dev; /* ST1 */
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struct device *mfg5_dev; /* ST2 */
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struct device *mfg6_dev; /* ST4 */
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struct device *mfg7_dev; /* ST5 */
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struct device *mfg8_dev; /* ST6 */
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struct device *mfg9_dev; /* ST0T0 */
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struct device *mfg10_dev; /* ST1T0 */
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struct device *mfg11_dev; /* ST2T0 */
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struct device *mfg12_dev; /* ST0T1 */
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struct device *mfg13_dev; /* ST1T1 */
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struct device *mfg14_dev; /* ST2T1 */
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struct device *mfg15_dev; /* ST4T0 */
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struct device *mfg16_dev; /* ST5T0 */
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struct device *mfg17_dev; /* ST6T0 */
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struct device *mfg18_dev; /* ST5T1 */
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struct device *mfg19_dev; /* ST6T1 */
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#endif /* GPUFREQ_PDCA_ENABLE */
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};
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struct gpufreq_status {
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struct gpufreq_opp_info *signed_table;
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struct gpufreq_opp_info *working_table;
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int buck_count;
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int mtcmos_count;
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int cg_count;
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int power_count;
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int active_count;
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unsigned int segment_id;
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int signed_opp_num;
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int segment_upbound;
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int segment_lowbound;
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int opp_num;
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int max_oppidx;
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int min_oppidx;
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int cur_oppidx;
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unsigned int cur_freq;
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unsigned int cur_volt;
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unsigned int cur_vsram;
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unsigned int lkg_rt_info;
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unsigned int lkg_ht_info;
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unsigned int lkg_rt_info_sram;
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unsigned int lkg_ht_info_sram;
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};
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struct gpufreq_volt_sb {
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unsigned int oppidx;
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unsigned int vgpu;
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unsigned int vstack;
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unsigned int vgpu_up;
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unsigned int vgpu_down;
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unsigned int vstack_up;
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unsigned int vstack_down;
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};
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/**************************************************
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* GPU Platform OPP Table Definition
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**************************************************/
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#define GPU_SIGNED_OPP_0 (0)
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#define GPU_SIGNED_OPP_1 (28)
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#define GPU_SIGNED_OPP_2 (36)
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#define GPU_SIGNED_OPP_3 (48)
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#define NUM_GPU_SIGNED_IDX ARRAY_SIZE(g_gpu_signed_idx)
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#define NUM_GPU_SIGNED_OPP ARRAY_SIZE(g_gpu_default_opp_table)
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static const int g_gpu_signed_idx[] = {
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GPU_SIGNED_OPP_0,
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GPU_SIGNED_OPP_1,
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GPU_SIGNED_OPP_2,
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GPU_SIGNED_OPP_3,
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};
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static struct gpufreq_opp_info g_gpu_default_opp_table[] = {
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 0 sign off */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 1 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 2 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 3 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 4 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 5 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 6 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 7 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 8 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 9 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 10 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 11 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 12 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 13 */
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GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 14 */
|
|
GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 15 */
|
|
GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 16 */
|
|
GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 17 */
|
|
GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 18 */
|
|
GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 19 */
|
|
GPUOP(1000000, 90000, 90000, POSDIV_POWER_2, 0, 0), /* 20 */
|
|
GPUOP(986250, 88125, 88125, POSDIV_POWER_2, 0, 0), /* 21 */
|
|
GPUOP(972500, 86250, 86250, POSDIV_POWER_2, 0, 0), /* 22 */
|
|
GPUOP(958750, 84375, 84375, POSDIV_POWER_2, 0, 0), /* 23 */
|
|
GPUOP(945000, 82500, 82500, POSDIV_POWER_4, 0, 0), /* 24 */
|
|
GPUOP(931250, 80625, 80625, POSDIV_POWER_4, 0, 0), /* 25 */
|
|
GPUOP(917500, 78750, 78750, POSDIV_POWER_4, 0, 0), /* 26 */
|
|
GPUOP(903750, 76875, 76875, POSDIV_POWER_4, 0, 0), /* 27 */
|
|
GPUOP(890000, 75000, 75000, POSDIV_POWER_4, 0, 0), /* 28 sign off */
|
|
GPUOP(866250, 74375, 75000, POSDIV_POWER_4, 0, 0), /* 29 */
|
|
GPUOP(842500, 73125, 75000, POSDIV_POWER_4, 0, 0), /* 30 */
|
|
GPUOP(818750, 72500, 75000, POSDIV_POWER_4, 0, 0), /* 31 */
|
|
GPUOP(795000, 71250, 75000, POSDIV_POWER_4, 0, 0), /* 32 */
|
|
GPUOP(771250, 70625, 75000, POSDIV_POWER_4, 0, 0), /* 33 */
|
|
GPUOP(747500, 69375, 75000, POSDIV_POWER_4, 0, 0), /* 34 */
|
|
GPUOP(723750, 68750, 75000, POSDIV_POWER_4, 0, 0), /* 35 */
|
|
GPUOP(700000, 67500, 75000, POSDIV_POWER_4, 0, 0), /* 36 sign off */
|
|
GPUOP(673750, 66875, 75000, POSDIV_POWER_4, 0, 0), /* 37 */
|
|
GPUOP(647500, 66250, 75000, POSDIV_POWER_4, 0, 0), /* 38 */
|
|
GPUOP(621250, 65000, 75000, POSDIV_POWER_4, 0, 0), /* 39 */
|
|
GPUOP(595000, 64375, 75000, POSDIV_POWER_4, 0, 0), /* 40 */
|
|
GPUOP(568750, 63750, 75000, POSDIV_POWER_4, 0, 0), /* 41 */
|
|
GPUOP(542500, 62500, 75000, POSDIV_POWER_4, 0, 0), /* 42 */
|
|
GPUOP(516250, 61875, 75000, POSDIV_POWER_4, 0, 0), /* 43 */
|
|
GPUOP(490000, 61250, 75000, POSDIV_POWER_4, 0, 0), /* 44 */
|
|
GPUOP(463750, 60000, 75000, POSDIV_POWER_8, 0, 0), /* 45 */
|
|
GPUOP(437500, 59375, 75000, POSDIV_POWER_8, 0, 0), /* 46 */
|
|
GPUOP(411250, 58750, 75000, POSDIV_POWER_8, 0, 0), /* 47 */
|
|
GPUOP(385000, 57500, 75000, POSDIV_POWER_8, 0, 0), /* 48 sign off */
|
|
};
|
|
|
|
#define STACK_SIGNED_OPP_0 (0)
|
|
#define STACK_SIGNED_OPP_1 (20)
|
|
#define STACK_SIGNED_OPP_2 (36)
|
|
#define STACK_SIGNED_OPP_3 (48)
|
|
#define NUM_STACK_SIGNED_IDX ARRAY_SIZE(g_stack_signed_idx)
|
|
#define NUM_STACK_SIGNED_OPP ARRAY_SIZE(g_stack_default_opp_table)
|
|
static const int g_stack_signed_idx[] = {
|
|
STACK_SIGNED_OPP_0,
|
|
STACK_SIGNED_OPP_1,
|
|
STACK_SIGNED_OPP_2,
|
|
STACK_SIGNED_OPP_3,
|
|
};
|
|
static struct gpufreq_opp_info g_stack_default_opp_table[] = {
|
|
GPUOP(981000, 80000, 80000, POSDIV_POWER_2, 0, 0), /* 0 sign off */
|
|
GPUOP(965000, 79375, 79375, POSDIV_POWER_2, 0, 0), /* 1 */
|
|
GPUOP(949000, 78750, 78750, POSDIV_POWER_4, 0, 0), /* 2 */
|
|
GPUOP(934000, 78125, 78125, POSDIV_POWER_4, 0, 0), /* 3 */
|
|
GPUOP(918000, 77500, 77500, POSDIV_POWER_4, 0, 0), /* 4 */
|
|
GPUOP(903000, 76875, 76875, POSDIV_POWER_4, 0, 0), /* 5 */
|
|
GPUOP(887000, 76250, 76250, POSDIV_POWER_4, 0, 0), /* 6 */
|
|
GPUOP(872000, 75625, 75625, POSDIV_POWER_4, 0, 0), /* 7 */
|
|
GPUOP(856000, 75000, 75000, POSDIV_POWER_4, 0, 0), /* 8 */
|
|
GPUOP(841000, 74375, 75000, POSDIV_POWER_4, 0, 0), /* 9 */
|
|
GPUOP(825000, 73750, 75000, POSDIV_POWER_4, 0, 0), /* 10 */
|
|
GPUOP(809000, 73125, 75000, POSDIV_POWER_4, 0, 0), /* 11 */
|
|
GPUOP(794000, 72500, 75000, POSDIV_POWER_4, 0, 0), /* 12 */
|
|
GPUOP(778000, 71875, 75000, POSDIV_POWER_4, 0, 0), /* 13 */
|
|
GPUOP(763000, 71250, 75000, POSDIV_POWER_4, 0, 0), /* 14 */
|
|
GPUOP(747000, 70625, 75000, POSDIV_POWER_4, 0, 0), /* 15 */
|
|
GPUOP(732000, 70000, 75000, POSDIV_POWER_4, 0, 0), /* 16 */
|
|
GPUOP(716000, 69375, 75000, POSDIV_POWER_4, 0, 0), /* 17 */
|
|
GPUOP(701000, 68750, 75000, POSDIV_POWER_4, 0, 0), /* 18 */
|
|
GPUOP(685000, 68125, 75000, POSDIV_POWER_4, 0, 0), /* 19 */
|
|
GPUOP(670000, 67500, 75000, POSDIV_POWER_4, 0, 0), /* 20 sign off */
|
|
GPUOP(652000, 66875, 75000, POSDIV_POWER_4, 0, 0), /* 21 */
|
|
GPUOP(635000, 66250, 75000, POSDIV_POWER_4, 0, 0), /* 22 */
|
|
GPUOP(617000, 65625, 75000, POSDIV_POWER_4, 0, 0), /* 23 */
|
|
GPUOP(600000, 65000, 75000, POSDIV_POWER_4, 0, 0), /* 24 */
|
|
GPUOP(582000, 64375, 75000, POSDIV_POWER_4, 0, 0), /* 25 */
|
|
GPUOP(565000, 63750, 75000, POSDIV_POWER_4, 0, 0), /* 26 */
|
|
GPUOP(547000, 63125, 75000, POSDIV_POWER_4, 0, 0), /* 27 */
|
|
GPUOP(530000, 62500, 75000, POSDIV_POWER_4, 0, 0), /* 28 */
|
|
GPUOP(512000, 61875, 75000, POSDIV_POWER_4, 0, 0), /* 29 */
|
|
GPUOP(495000, 61250, 75000, POSDIV_POWER_4, 0, 0), /* 30 */
|
|
GPUOP(477000, 60625, 75000, POSDIV_POWER_4, 0, 0), /* 31 */
|
|
GPUOP(460000, 60000, 75000, POSDIV_POWER_8, 0, 0), /* 32 */
|
|
GPUOP(442000, 59375, 75000, POSDIV_POWER_8, 0, 0), /* 33 */
|
|
GPUOP(425000, 58750, 75000, POSDIV_POWER_8, 0, 0), /* 34 */
|
|
GPUOP(407000, 58125, 75000, POSDIV_POWER_8, 0, 0), /* 35 */
|
|
GPUOP(390000, 57500, 75000, POSDIV_POWER_8, 0, 0), /* 36 sign off */
|
|
GPUOP(376000, 56875, 75000, POSDIV_POWER_8, 0, 0), /* 37 */
|
|
GPUOP(362000, 56250, 75000, POSDIV_POWER_8, 0, 0), /* 38 */
|
|
GPUOP(348000, 55625, 75000, POSDIV_POWER_8, 0, 0), /* 39 */
|
|
GPUOP(334000, 55000, 75000, POSDIV_POWER_8, 0, 0), /* 40 */
|
|
GPUOP(320000, 54375, 75000, POSDIV_POWER_8, 0, 0), /* 41 */
|
|
GPUOP(307000, 53750, 75000, POSDIV_POWER_8, 0, 0), /* 42 */
|
|
GPUOP(293000, 53125, 75000, POSDIV_POWER_8, 0, 0), /* 43 */
|
|
GPUOP(279000, 52500, 75000, POSDIV_POWER_8, 0, 0), /* 44 */
|
|
GPUOP(265000, 51875, 75000, POSDIV_POWER_8, 0, 0), /* 45 */
|
|
GPUOP(251000, 51250, 75000, POSDIV_POWER_8, 0, 0), /* 46 */
|
|
GPUOP(237000, 50625, 75000, POSDIV_POWER_16, 0, 0), /* 47 */
|
|
GPUOP(224000, 50000, 75000, POSDIV_POWER_16, 0, 0), /* 48 sign off */
|
|
};
|
|
|
|
/**************************************************
|
|
* OPP Adjustment
|
|
**************************************************/
|
|
static struct gpufreq_adj_info g_gpu_avs_table[NUM_GPU_SIGNED_IDX] = {
|
|
ADJOP(GPU_SIGNED_OPP_0, 0, 0, 0),
|
|
ADJOP(GPU_SIGNED_OPP_1, 0, 0, 0),
|
|
ADJOP(GPU_SIGNED_OPP_2, 0, 0, 0),
|
|
ADJOP(GPU_SIGNED_OPP_3, 0, 0, 0),
|
|
};
|
|
|
|
static struct gpufreq_adj_info g_stack_avs_table[NUM_STACK_SIGNED_IDX] = {
|
|
ADJOP(STACK_SIGNED_OPP_0, 0, 0, 0),
|
|
ADJOP(STACK_SIGNED_OPP_1, 0, 0, 0),
|
|
ADJOP(STACK_SIGNED_OPP_2, 0, 0, 0),
|
|
ADJOP(STACK_SIGNED_OPP_3, 0, 0, 0),
|
|
};
|
|
|
|
static struct gpufreq_adj_info g_gpu_aging_table[][NUM_GPU_SIGNED_IDX] = {
|
|
{ /* aging table 0 */
|
|
ADJOP(GPU_SIGNED_OPP_0, 0, 625, 0),
|
|
ADJOP(GPU_SIGNED_OPP_1, 0, 625, 0),
|
|
ADJOP(GPU_SIGNED_OPP_2, 0, 625, 0),
|
|
ADJOP(GPU_SIGNED_OPP_3, 0, 0, 0),
|
|
},
|
|
{ /* aging table 1 */
|
|
ADJOP(GPU_SIGNED_OPP_0, 0, 0, 0),
|
|
ADJOP(GPU_SIGNED_OPP_1, 0, 0, 0),
|
|
ADJOP(GPU_SIGNED_OPP_2, 0, 0, 0),
|
|
ADJOP(GPU_SIGNED_OPP_3, 0, 0, 0),
|
|
},
|
|
/* aging table 2: remove for code size */
|
|
/* aging table 3: remove for code size */
|
|
};
|
|
|
|
static struct gpufreq_adj_info g_stack_aging_table[][NUM_STACK_SIGNED_IDX] = {
|
|
{ /* aging table 0 */
|
|
ADJOP(STACK_SIGNED_OPP_0, 0, 625, 0),
|
|
ADJOP(STACK_SIGNED_OPP_1, 0, 625, 0),
|
|
ADJOP(STACK_SIGNED_OPP_2, 0, 625, 0),
|
|
ADJOP(STACK_SIGNED_OPP_3, 0, 0, 0),
|
|
},
|
|
{ /* aging table 1 */
|
|
ADJOP(STACK_SIGNED_OPP_0, 0, 0, 0),
|
|
ADJOP(STACK_SIGNED_OPP_1, 0, 0, 0),
|
|
ADJOP(STACK_SIGNED_OPP_2, 0, 0, 0),
|
|
ADJOP(STACK_SIGNED_OPP_3, 0, 0, 0),
|
|
},
|
|
/* aging table 2: remove for code size */
|
|
/* aging table 3: remove for code size */
|
|
};
|
|
|
|
#endif /* __GPUFREQ_MT6985_H__ */
|