327 lines
13 KiB
C
327 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#ifndef __GPUFREQ_MT6886_H__
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#define __GPUFREQ_MT6886_H__
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/**************************************************
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* GPUFREQ Local Config
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**************************************************/
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/* 0 -> power on once then never off and disable DDK power on/off callback */
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#define GPUFREQ_POWER_CTRL_ENABLE (1)
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/* 0 -> disable DDK runtime active-idle callback */
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#define GPUFREQ_ACTIVE_IDLE_CTRL_ENABLE (0)
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/*
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* (DVFS_ENABLE, CUST_INIT)
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* (1, 1) -> DVFS enable and init to CUST_INIT_OPPIDX
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* (1, 0) -> DVFS enable
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* (0, 1) -> DVFS disable but init to CUST_INIT_OPPIDX (do DVFS only onces)
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* (0, 0) -> DVFS disable
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*/
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#define GPUFREQ_DVFS_ENABLE (1)
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#define GPUFREQ_CUST_INIT_ENABLE (0)
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#define GPUFREQ_CUST_INIT_OPPIDX (0)
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/* MFGSYS Feature */
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#define GPUFREQ_HWDCM_ENABLE (1)
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#define GPUFREQ_ACP_ENABLE (1)
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#define GPUFREQ_PDCA_ENABLE (1)
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#define GPUFREQ_GPM1_ENABLE (1)
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#define GPUFREQ_MERGER_ENABLE (1)
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#define GPUFREQ_DFD_ENABLE (1)
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#define GPUFREQ_AVS_ENABLE (0)
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#define GPUFREQ_ASENSOR_ENABLE (0)
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#define GPUFREQ_SELF_CTRL_MTCMOS (1)
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#define GPUFREQ_SHARED_STATUS_REG (0)
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/**************************************************
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* Clock Setting
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**************************************************/
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#define POSDIV_2_MAX_FREQ (1900000) /* KHz */
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#define POSDIV_2_MIN_FREQ (750000) /* KHz */
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#define POSDIV_4_MAX_FREQ (950000) /* KHz */
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#define POSDIV_4_MIN_FREQ (375000) /* KHz */
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#define POSDIV_8_MAX_FREQ (475000) /* KHz */
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#define POSDIV_8_MIN_FREQ (187500) /* KHz */
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#define POSDIV_16_MAX_FREQ (237500) /* KHz */
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#define POSDIV_16_MIN_FREQ (125000) /* KHz */
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#define POSDIV_SHIFT (24) /* bit */
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#define DDS_SHIFT (14) /* bit */
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#define MFGPLL_FIN (26) /* MHz */
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#define CKMUX_SEL_CORE (4)
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#define CKMUX_SEL_PARK (5)
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#define CKMUX_SEL_STACK (7)
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#define CKMUX_SEL_STACK_PARK (8)
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#define GPUPLL_ID (0x0)
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#define STACKPLL_ID (0x3)
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#define FREQ_ROUNDUP_TO_10(freq) ((freq % 10) ? (freq - (freq % 10) + 10) : freq)
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/**************************************************
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* Frequency Hopping Setting
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**************************************************/
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#define GPUFREQ_FHCTL_ENABLE (0)
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#define MFG_PLL_NAME "mfgpll"
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#define MFGSC_PLL_NAME "mfgscpll"
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/**************************************************
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* MTCMOS Setting
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**************************************************/
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#define GPUFREQ_CHECK_MFG_PWR_STATUS (0)
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#define MFG_0_1_PWR_MASK (GENMASK(1, 0))
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#define MFG_0_12_PWR_MASK (GENMASK(6, 0))
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#define MFG_1_12_PWR_MASK (GENMASK(6, 1))
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#define MFG_0_1_PWR_STATUS \
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(((readl(SPM_MFG0_PWR_CON) & BIT(30)) >> 30) | \
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(((readl(MFG_RPC_MFG1_PWR_CON) & BIT(30)) >> 30) << 1))
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#define MFG_0_12_PWR_STATUS \
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(((readl(SPM_MFG0_PWR_CON) & BIT(30)) >> 30) | \
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(((readl(MFG_RPC_MFG1_PWR_CON) & BIT(30)) >> 30) << 1) | \
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(((readl(MFG_RPC_MFG2_PWR_CON) & BIT(30)) >> 30) << 2) | \
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(((readl(MFG_RPC_MFG9_PWR_CON) & BIT(30)) >> 30) << 3) | \
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(((readl(MFG_RPC_MFG10_PWR_CON) & BIT(30)) >> 30) << 4) | \
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(((readl(MFG_RPC_MFG11_PWR_CON) & BIT(30)) >> 30) << 5) | \
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(((readl(MFG_RPC_MFG12_PWR_CON) & BIT(30)) >> 30) << 6))
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/**************************************************
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* Shader Core Setting
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**************************************************/
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#define MFG9_SHADER_STACK0 (T0C0) /* MFG9 */
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#define MFG10_SHADER_STACK2 (T2C0) /* MFG10 */
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#define MFG11_SHADER_STACK4 (T4C0) /* MFG11 */
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#define MFG12_SHADER_STACK6 (T6C0) /* MFG12 */
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#define GPU_SHADER_PRESENT_1 \
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(MFG9_SHADER_STACK0)
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#define GPU_SHADER_PRESENT_2 \
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(MFG9_SHADER_STACK0 | MFG10_SHADER_STACK2)
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#define GPU_SHADER_PRESENT_3 \
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(MFG9_SHADER_STACK0 | MFG10_SHADER_STACK2 | MFG11_SHADER_STACK4)
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#define GPU_SHADER_PRESENT_4 \
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(MFG9_SHADER_STACK0 | MFG10_SHADER_STACK2 | MFG11_SHADER_STACK4 | MFG12_SHADER_STACK6)
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#define SHADER_CORE_NUM (4)
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struct gpufreq_core_mask_info g_core_mask_table[] = {
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{4, GPU_SHADER_PRESENT_4},
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{3, GPU_SHADER_PRESENT_3},
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{2, GPU_SHADER_PRESENT_2},
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{1, GPU_SHADER_PRESENT_1},
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};
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/**************************************************
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* Reference Power Setting MT6789 TBD
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**************************************************/
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#define GPU_ACT_REF_POWER (977) /* mW */
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#define GPU_ACT_REF_FREQ (1100000) /* KHz */
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#define GPU_ACT_REF_VOLT (85000) /* mV x 100 */
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#define GPU_LEAKAGE_POWER (71)
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/**************************************************
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* PMIC Setting MT6886
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**************************************************/
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/*
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* PMIC hardware range:
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* vgpu 0.4 ~ 1.19375 V (MT6368)
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* vsram 0.4 ~ 1.19375 V (MT6363)
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*/
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#define VGPU_MAX_VOLT (119375) /* mV x 100 */
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#define VGPU_MIN_VOLT (40000) /* mV x 100 */
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#define VSRAM_MAX_VOLT (119375) /* mV x 100 */
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#define VSRAM_MIN_VOLT (40000) /* mV x 100 */
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#define VSRAM_THRESH (75000)
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#define PMIC_STEP (625) /* mV x 100 */
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/*
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* (0)mv <= (VSRAM - VGPU) <= (200)mV
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*/
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#define VSRAM_VLOGIC_DIFF (20000) /* mV x 100 */
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#define VOLT_NORMALIZATION(volt) ((volt % 625) ? (volt - (volt % 625) + 625) : volt)
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/**************************************************
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* Power Throttling Setting
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**************************************************/
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#define GPUFREQ_BATT_OC_ENABLE (0)
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#define GPUFREQ_BATT_PERCENT_ENABLE (0)
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#define GPUFREQ_LOW_BATT_ENABLE (0)
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#define GPUFREQ_BATT_OC_FREQ (485000)
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#define GPUFREQ_BATT_PERCENT_IDX (0)
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#define GPUFREQ_LOW_BATT_FREQ (485000)
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/**************************************************
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* Aging Sensor Setting
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**************************************************/
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#define GPUFREQ_AGING_KEEP_FGPU (670000)
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#define GPUFREQ_AGING_KEEP_VGPU (65000)
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#define GPUFREQ_AGING_KEEP_VSRAM (75000)
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#define GPUFREQ_AGING_LKG_VGPU (70000)
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#define GPUFREQ_AGING_GAP_MIN (-3)
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#define GPUFREQ_AGING_GAP_1 (2)
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#define GPUFREQ_AGING_GAP_2 (4)
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#define GPUFREQ_AGING_MAX_TABLE_IDX (1)
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#define GPUFREQ_AGING_MOST_AGRRESIVE (0)
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/**************************************************
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* DFD Setting
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**************************************************/
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#define MFG_DEBUGMON_CON_00_ENABLE (0xFFFFFFFF)
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#define MFG_DFD_CON_0_ENABLE (0x0F101100)
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#define MFG_DFD_CON_1_ENABLE (0x00008C20)
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#define MFG_DFD_CON_2_ENABLE (0x0000DB9E)
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#define MFG_DFD_CON_3_ENABLE (0x0021547C)
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#define MFG_DFD_CON_4_ENABLE (0x00000000)
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#define MFG_DFD_CON_5_ENABLE (0x00000000)
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#define MFG_DFD_CON_6_ENABLE (0x00000000)
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#define MFG_DFD_CON_7_ENABLE (0x00000000)
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#define MFG_DFD_CON_8_ENABLE (0x00000000)
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#define MFG_DFD_CON_9_ENABLE (0x00000000)
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#define MFG_DFD_CON_10_ENABLE (0x00000000)
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#define MFG_DFD_CON_11_ENABLE (0x00000000)
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/**************************************************
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* Enumeration MT6886
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**************************************************/
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enum gpufreq_segment {
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MT6886_SEGMENT = 1,
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};
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enum gpufreq_clk_src {
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CLOCK_SUB = 0,
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CLOCK_MAIN,
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};
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enum gpufreq_opp_direct {
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SCALE_DOWN = 0,
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SCALE_UP,
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SCALE_STAY,
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};
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/**************************************************
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* Structure MT6886
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**************************************************/
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struct gpufreq_pmic_info {
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struct regulator *reg_vgpu;
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struct regulator *reg_vsram;
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};
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struct gpufreq_clk_info {
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struct clk *clk_main_parent;
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struct clk *clk_sc_main_parent;
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};
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struct gpufreq_mtcmos_info {
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struct device *mfg1_dev; /* CM7, PDCA */
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#if !GPUFREQ_PDCA_ENABLE
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struct device *mfg2_dev; /* L2, MMU, Tiler */
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struct device *mfg9_dev; /* ST0 */
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struct device *mfg10_dev; /* ST2 */
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struct device *mfg11_dev; /* ST4 */
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struct device *mfg12_dev; /* ST6 */
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#endif
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};
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struct gpufreq_status {
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struct gpufreq_opp_info *signed_table;
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struct gpufreq_opp_info *working_table;
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int buck_count;
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int mtcmos_count;
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int cg_count;
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int power_count;
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int active_count;
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unsigned int segment_id;
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int signed_opp_num;
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int segment_upbound;
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int segment_lowbound;
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int opp_num;
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int max_oppidx;
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int min_oppidx;
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int cur_oppidx;
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unsigned int cur_freq;
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unsigned int cur_volt;
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unsigned int cur_vsram;
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};
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/**************************************************
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* GPU Platform OPP Table Definition
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**************************************************/
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#define GPU_BINNING_OPP_0 (0)
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#define GPU_BINNING_OPP_1 (28)
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#define GPU_BINNING_OPP_2 (44)
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#define NUM_GPU_BINNING_IDX ARRAY_SIZE(g_gpu_binning_idx)
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#define NUM_GPU_SIGNED_OPP ARRAY_SIZE(g_gpu_default_opp_table)
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static const int g_gpu_binning_idx[] = {
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GPU_BINNING_OPP_0,
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GPU_BINNING_OPP_1,
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GPU_BINNING_OPP_2,
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};
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struct gpufreq_opp_info g_gpu_default_opp_table[] = {
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GPUOP(1130000, 85000, 85000, POSDIV_POWER_2, 0, 0), /* 0 sign off */
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GPUOP(1115000, 85000, 85000, POSDIV_POWER_2, 0, 0), /* 1 */
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GPUOP(1100000, 84375, 84375, POSDIV_POWER_2, 0, 0), /* 2 */
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GPUOP(1085000, 83750, 83750, POSDIV_POWER_2, 0, 0), /* 3 */
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GPUOP(1070000, 83125, 83125, POSDIV_POWER_2, 0, 0), /* 4 */
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GPUOP(1055000, 82500, 82500, POSDIV_POWER_2, 0, 0), /* 5 */
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GPUOP(1040000, 81875, 81875, POSDIV_POWER_2, 0, 0), /* 6 */
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GPUOP(1025000, 81250, 81250, POSDIV_POWER_2, 0, 0), /* 7 */
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GPUOP(1010000, 80625, 80625, POSDIV_POWER_2, 0, 0), /* 8 */
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GPUOP(995000, 80000, 80000, POSDIV_POWER_2, 0, 0), /* 9 */
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GPUOP(980000, 79375, 79375, POSDIV_POWER_2, 0, 0), /* 10 */
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GPUOP(965000, 78750, 78750, POSDIV_POWER_2, 0, 0), /* 11 */
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GPUOP(950000, 78125, 78125, POSDIV_POWER_4, 0, 0), /* 12 */
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GPUOP(935000, 77500, 77500, POSDIV_POWER_4, 0, 0), /* 13 */
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GPUOP(920000, 77500, 77500, POSDIV_POWER_4, 0, 0), /* 14 */
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GPUOP(905000, 76875, 76875, POSDIV_POWER_4, 0, 0), /* 15 */
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GPUOP(890000, 76250, 76250, POSDIV_POWER_4, 0, 0), /* 16 */
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GPUOP(872000, 75625, 75625, POSDIV_POWER_4, 0, 0), /* 17 */
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GPUOP(854000, 75000, 75000, POSDIV_POWER_4, 0, 0), /* 18 sign off */
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GPUOP(836000, 73750, 75000, POSDIV_POWER_4, 0, 0), /* 19 */
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GPUOP(818000, 73125, 75000, POSDIV_POWER_4, 0, 0), /* 20 */
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GPUOP(800000, 72500, 75000, POSDIV_POWER_4, 0, 0), /* 21 */
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GPUOP(782000, 71875, 75000, POSDIV_POWER_4, 0, 0), /* 22 */
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GPUOP(764000, 71250, 75000, POSDIV_POWER_4, 0, 0), /* 23 */
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GPUOP(746000, 70625, 75000, POSDIV_POWER_4, 0, 0), /* 24 */
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GPUOP(728000, 70000, 75000, POSDIV_POWER_4, 0, 0), /* 25 */
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GPUOP(710000, 69375, 75000, POSDIV_POWER_4, 0, 0), /* 26 */
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GPUOP(692000, 68750, 75000, POSDIV_POWER_4, 0, 0), /* 27 */
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GPUOP(675000, 67500, 75000, POSDIV_POWER_4, 0, 0), /* 28 sign off*/
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GPUOP(655000, 66875, 75000, POSDIV_POWER_4, 0, 0), /* 29 */
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GPUOP(635000, 66250, 75000, POSDIV_POWER_4, 0, 0), /* 30 */
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GPUOP(615000, 65625, 75000, POSDIV_POWER_4, 0, 0), /* 31 */
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GPUOP(596000, 65000, 75000, POSDIV_POWER_4, 0, 0), /* 32 */
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GPUOP(576000, 64375, 75000, POSDIV_POWER_4, 0, 0), /* 33 */
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GPUOP(556000, 63750, 75000, POSDIV_POWER_4, 0, 0), /* 34 */
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GPUOP(537000, 63125, 75000, POSDIV_POWER_4, 0, 0), /* 35 */
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GPUOP(517000, 62500, 75000, POSDIV_POWER_4, 0, 0), /* 36 */
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GPUOP(497000, 61875, 75000, POSDIV_POWER_4, 0, 0), /* 37 */
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GPUOP(478000, 61250, 75000, POSDIV_POWER_4, 0, 0), /* 38 */
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GPUOP(458000, 60625, 75000, POSDIV_POWER_8, 0, 0), /* 39 */
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GPUOP(438000, 60000, 75000, POSDIV_POWER_8, 0, 0), /* 40 */
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GPUOP(419000, 59375, 75000, POSDIV_POWER_8, 0, 0), /* 41 */
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GPUOP(399000, 58750, 75000, POSDIV_POWER_8, 0, 0), /* 42 */
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GPUOP(379000, 58125, 75000, POSDIV_POWER_8, 0, 0), /* 43 */
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GPUOP(360000, 57500, 75000, POSDIV_POWER_8, 0, 0), /* 44 sign off*/
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};
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/**************************************************
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* OPP Adjustment
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**************************************************/
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static struct gpufreq_adj_info g_avs_table[NUM_GPU_BINNING_IDX] = {
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ADJOP(GPU_BINNING_OPP_0, 0, 0, 0),
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ADJOP(GPU_BINNING_OPP_1, 0, 0, 0),
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ADJOP(GPU_BINNING_OPP_2, 0, 0, 0),
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};
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static struct gpufreq_adj_info g_aging_table[][NUM_GPU_BINNING_IDX] = {
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{ /* aging table 0 */
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ADJOP(GPU_BINNING_OPP_0, 0, 625, 0),
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ADJOP(GPU_BINNING_OPP_1, 0, 625, 0),
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ADJOP(GPU_BINNING_OPP_2, 0, 625, 0),
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},
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{ /* aging table 1 */
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ADJOP(GPU_BINNING_OPP_0, 0, 0, 0),
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ADJOP(GPU_BINNING_OPP_1, 0, 0, 0),
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ADJOP(GPU_BINNING_OPP_2, 0, 0, 0),
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},
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/* aging table 2: remove for code size */
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/* aging table 3: remove for code size */
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};
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#endif /* __GPUFREQ_MT6886_H__ */
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