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kernel-brax3-ubuntu-touch/arch/arm64/boot/dts/mediatek/mt8195.dts
erascape f319b992b1 kernel-5.15: Initial import brax3 UT kernel 
* halium configs enabled

Signed-off-by: erascape <erascape@proton.me>
2025-09-23 15:17:10 +00:00

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2020 MediaTek Inc.
*
*/
/dts-v1/;
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/memory/mt8195-larb-port.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/apusys/mt8195-apusys-power.h>
#include <dt-bindings/regulator/mtk,mt6315.h>
#include <dt-bindings/interconnect/mtk,mt8195-emi.h>
#include <dt-bindings/interconnect/mtk,mmqos.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "MT8195";
compatible = "mediatek,MT8195";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
qos@0011bb00 {
compatible = "mediatek,qos-2.0";
reg = <0 0x0011bb00 0 0x100>;
};
performance: performance-controller@11bc10 {
compatible = "mediatek,cpufreq-hw";
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
#performance-domain-cells = <1>;
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <2>;
#redistributor-regions = <1>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, // distributor
<0 0x0c040000 0 0x200000>; // redistributor
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
};
};
};
cm_mgr: cm_mgr@0c530000 {
compatible = "mediatek,mt8195-cm-mgr";
reg = <0 0x0c530000 0 0x9000>;
reg-names = "cm_mgr_base";
required-opps = <&dvfsrc_freq_opp0>,
<&dvfsrc_freq_opp1>,
<&dvfsrc_freq_opp2>,
<&dvfsrc_freq_opp3>,
<&dvfsrc_freq_opp4>,
<&dvfsrc_freq_opp5>,
<&dvfsrc_freq_opp6>;
cm_mgr,cp_down = <140 100 140 100 140>;
cm_mgr,cp_up = <100 100 100 100 100>;
cm_mgr,dt_down = <3 0 0 0 0>;
cm_mgr,dt_up = <0 0 0 0 0>;
cm_mgr,vp_down = <100 100 100 100 100>;
cm_mgr,vp_up = <100 100 100 100 100>;
};
mcupm: mcupm@c540000 {
compatible = "mediatek,mcupm";
reg = <0 0x0c540000 0 0x22000>,
<0 0x0c55fb00 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fba0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fc40 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fce0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fd80 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fe20 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55fec0 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>,
<0 0x0c55ff60 0 0xa0>,
<0 0x0c562004 0 0x4>,
<0 0x0c562018 0 0x4>,
<0 0x0c562000 0 0x4>,
<0 0x0c562010 0 0x4>;
reg-names = "mcupm_base",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox0_send",
"mbox0_recv",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox1_send",
"mbox1_recv",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox2_send",
"mbox2_recv",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox3_send",
"mbox3_recv",
"mbox4_base",
"mbox4_set",
"mbox4_clr",
"mbox4_send",
"mbox4_recv",
"mbox5_base",
"mbox5_set",
"mbox5_clr",
"mbox5_send",
"mbox5_recv",
"mbox6_base",
"mbox6_set",
"mbox6_clr",
"mbox6_send",
"mbox6_recv",
"mbox7_base",
"mbox7_set",
"mbox7_clr",
"mbox7_send",
"mbox7_recv";
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4",
"mbox5",
"mbox6",
"mbox7";
};
bus_tracer@0d040000 {
compatible = "mediatek,bus_tracer-v1";
reg = <0 0x0d040000 0 0x100>, /* dem base */
<0 0x0d01a000 0 0x1000>, /* dbgao base */
<0 0x0d041000 0 0x3000>, /* funnel/rep/etr base */
<0 0x0d010000 0 0x1000>, /* bus tracer etb base */
<0 0x0d040800 0 0x100>, /* infra bus tracer base */
<0 0x0d040900 0 0x100>, /* peri1 bus tracer base */
<0 0x0d040a00 0 0x100>; /* peri2 bus tracer base */
mediatek,err_flag = <0xfbf8ffff>;
/*
* index 0 for infra bus tracer
* index 1 for peri1 bus tracer
* index 2 for peri2 bus tracer
*/
mediatek,num_tracer = <3>;
mediatek,enabled_tracer = <1 1 1>;
mediatek,at_id = <0x10 0x30 0x70>;
/* filters: disabled by default */
/*
* mediatek,watchpoint_filter = <0x0 0x10010000 0xfffff000>;
* mediatek,bypass_filter = <0x14000000 0xffff0000>;
* mediatek,id_filter = <0x10 0x40>;
* mediatek,rw_filter = <0x0 0x1>;
*/
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8195-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
infracfg_rst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
0x120 1 0x124 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
>;
};
};
scpsys_ao: scpsys@10001000 {
compatible = "mediatek,scpsys";
reg = <0 0x10001000 0 0x1000>; /* infracfg_ao */
#clock-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt8195-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt8195-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d40000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11eb0000 0 0x1000>,
<0 0x11f40000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg_bm",
"iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_rb", "iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 144>;
interrupt-controller;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
mediatek,eint = <&eint>;
watchdog_pins_default: watchdog_pins {
wdt_op {
pinmux = <PINMUX_GPIO37__FUNC_WATCHDOG>;
};
};
hdmi_pin: hdmipinctrl {
hdmi_hotplug {
pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>;
bias-pull-down;
};
hdmi_ddc {
pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>,
<PINMUX_GPIO35__FUNC_HDMITX20_SDA>;
mediatek,drive-strength-adv = <0>;
drive-strength = <MTK_DRIVE_10mA>;
};
hdmi_cec {
pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>;
bias-disable;
};
hdmi_5vctrl {
pinmux = <PINMUX_GPIO31__FUNC_GPIO31>;
slew-rate = <1>;
output-high;
};
};
pmif_pin: pmif_default_pin {
pinmux = <PINMUX_GPIO36__FUNC_RTC32K_CK>,
<PINMUX_GPIO40__FUNC_PWRAP_SPI0_CSN>,
<PINMUX_GPIO41__FUNC_PWRAP_SPI0_CK>,
<PINMUX_GPIO42__FUNC_PWRAP_SPI0_MO>,
<PINMUX_GPIO43__FUNC_PWRAP_SPI0_MI>,
<PINMUX_GPIO44__FUNC_SPMI_M_SCL>,
<PINMUX_GPIO45__FUNC_SPMI_M_SDA>;
};
scp_default: scp_default {
scp_pin {
pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
bias-disable;
input-enable;
};
};
srclken_pin: srclkenpinctrl {
srclken0 {
pinmux = <PINMUX_GPIO38__FUNC_SRCLKENA0>;
};
srclken1 {
pinmux = <PINMUX_GPIO39__FUNC_SRCLKENA1>;
};
};
};
spmtwam: spmtwam@10006000 {
compatible = "mediatek,spmtwam";
reg = <0 0x10006000 0 0x1000>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>;
spm_twam_con = <0x990>;
spm_twam_window_len = <0x994>;
spm_twam_idle_sel = <0x998>;
spm_irq_mask = <0x78>;
spm_irq_sta = <0x138>;
spm_twam_last_sta0 = <0x1d0>;
spm_twam_last_sta1 = <0x1d4>;
spm_twam_last_sta2 = <0x1d8>;
spm_twam_last_sta3 = <0x1dc>;
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8195-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domain of the SoC */
pcie_mac_p0@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
pcie_mac_p1@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
pcie_phy@MT8195_POWER_DOMAIN_PCIE_PHY {
reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
#power-domain-cells = <0>;
};
ssusb_pcie_phy@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
#power-domain-cells = <0>;
};
csi_rx_top@MT8195_POWER_DOMAIN_CSI_RX_TOP {
reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
clocks = <&topckgen CLK_TOP_SENINF_SEL>,
<&topckgen CLK_TOP_SENINF2_SEL>;
clock-names = "csi_rx_top", "csi_rx_top1";
#power-domain-cells = <0>;
};
ether@MT8195_POWER_DOMAIN_ETHER {
reg = <MT8195_POWER_DOMAIN_ETHER>;
clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
clock-names = "ether";
#power-domain-cells = <0>;
};
adsp@MT8195_POWER_DOMAIN_ADSP {
reg = <MT8195_POWER_DOMAIN_ADSP>;
clocks = <&topckgen CLK_TOP_ADSP_SEL>,
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>;
clock-names = "adsp", "adsp1";
#address-cells = <1>;
#size-cells = <0>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <1>;
audio_asrc@MT8195_POWER_DOMAIN_AUDIO_ASRC {
reg = <MT8195_POWER_DOMAIN_AUDIO_ASRC>;
clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
clock-names = "audio_asrc", "audio_asrc1";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
audio@MT8195_POWER_DOMAIN_AUDIO {
reg = <MT8195_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
clock-names = "audio", "audio1", "audio2", "audio3";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
nna@MT8195_POWER_DOMAIN_NNA {
reg = <MT8195_POWER_DOMAIN_NNA>;
clocks = <&topckgen CLK_TOP_NNA0_SEL>;
clock-names = "nna";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
nna0@MT8195_POWER_DOMAIN_NNA0 {
reg = <MT8195_POWER_DOMAIN_NNA0>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
nna1@MT8195_POWER_DOMAIN_NNA1 {
reg = <MT8195_POWER_DOMAIN_NNA1>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
mfg0: mfg0@MT8195_POWER_DOMAIN_MFG0 {
reg = <MT8195_POWER_DOMAIN_MFG0>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
mfg1@MT8195_POWER_DOMAIN_MFG1 {
reg = <MT8195_POWER_DOMAIN_MFG1>;
clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
clock-names = "mfg";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
mfg2@MT8195_POWER_DOMAIN_MFG2 {
reg = <MT8195_POWER_DOMAIN_MFG2>;
#power-domain-cells = <0>;
};
mfg3@MT8195_POWER_DOMAIN_MFG3 {
reg = <MT8195_POWER_DOMAIN_MFG3>;
#power-domain-cells = <0>;
};
mfg4@MT8195_POWER_DOMAIN_MFG4 {
reg = <MT8195_POWER_DOMAIN_MFG4>;
#power-domain-cells = <0>;
};
mfg5@MT8195_POWER_DOMAIN_MFG5 {
reg = <MT8195_POWER_DOMAIN_MFG5>;
#power-domain-cells = <0>;
};
mfg6@MT8195_POWER_DOMAIN_MFG6 {
reg = <MT8195_POWER_DOMAIN_MFG6>;
#power-domain-cells = <0>;
};
};
};
vppsys0@MT8195_POWER_DOMAIN_VPPSYS0 {
reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
clocks = <&topckgen CLK_TOP_VPP_SEL>,
<&topckgen CLK_TOP_CAM_SEL>,
<&topckgen CLK_TOP_CCU_SEL>,
<&topckgen CLK_TOP_IMG_SEL>,
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&topckgen CLK_TOP_WPE_VPP_SEL>,
<&topckgen CLK_TOP_CFG_VPP0>,
<&vppsys0 CLK_VPP0_SMI_COMMON>,
<&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
<&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
<&vppsys0 CLK_VPP0_GALS_VENCSYS>,
<&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
<&vppsys0 CLK_VPP0_GALS_INFRA>,
<&vppsys0 CLK_VPP0_GALS_CAMSYS>,
<&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
<&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
<&vppsys0 CLK_VPP0_SMI_REORDER>,
<&vppsys0 CLK_VPP0_SMI_IOMMU>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
<&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
<&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
<&vppsys0 CLK_VPP0_SMI_RSI>,
<&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
<&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
<&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
"vppsys4", "vppsys5", "vppsys6", "vppsys7",
"vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
"vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
"vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
"vppsys0-12", "vppsys0-13", "vppsys0-14",
"vppsys0-15", "vppsys0-16", "vppsys0-17",
"vppsys0-18";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
vdec1@MT8195_POWER_DOMAIN_VDEC1 {
reg = <MT8195_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys CLK_VDEC_LARB1>;
clock-names = "vdec1-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
venc_core1@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
vdosys0@MT8195_POWER_DOMAIN_VDOSYS0 {
reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&topckgen CLK_TOP_CFG_VDO0>,
<&vdosys0 CLK_VDO0_SMI_GALS>,
<&vdosys0 CLK_VDO0_SMI_COMMON>,
<&vdosys0 CLK_VDO0_SMI_EMI>,
<&vdosys0 CLK_VDO0_SMI_IOMMU>,
<&vdosys0 CLK_VDO0_SMI_LARB>,
<&vdosys0 CLK_VDO0_SMI_RSI>;
clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
"vdosys0-2", "vdosys0-3", "vdosys0-4",
"vdosys0-5";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
vppsys1@MT8195_POWER_DOMAIN_VPPSYS1 {
reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
clocks = <&topckgen CLK_TOP_CFG_VPP1>,
<&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
<&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
clock-names = "vppsys1", "vppsys1-0", "vppsys1-1";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
wepsys@MT8195_POWER_DOMAIN_WPESYS {
reg = <MT8195_POWER_DOMAIN_WPESYS>;
clocks = <&wpesys CLK_WPE_SMI_LARB7>,
<&wpesys CLK_WPE_SMI_LARB8>,
<&wpesys CLK_WPE_SMI_LARB7_P>,
<&wpesys CLK_WPE_SMI_LARB8_P>;
clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
"wepsys-3";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
vdec0@MT8195_POWER_DOMAIN_VDEC0 {
reg = <MT8195_POWER_DOMAIN_VDEC0>;
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "vdec0-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
vdec2@MT8195_POWER_DOMAIN_VDEC2 {
reg = <MT8195_POWER_DOMAIN_VDEC2>;
clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
clock-names = "vdec2-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
venc@MT8195_POWER_DOMAIN_VENC {
reg = <MT8195_POWER_DOMAIN_VENC>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
vdosys1@MT8195_POWER_DOMAIN_VDOSYS1 {
reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&topckgen CLK_TOP_CFG_VDO1>,
<&vdosys1 CLK_VDO1_SMI_LARB2>,
<&vdosys1 CLK_VDO1_SMI_LARB3>,
<&vdosys1 CLK_VDO1_GALS>;
clock-names = "vdosys1", "vdosys1-0",
"vdosys1-1", "vdosys1-2";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
dp_tx@MT8195_POWER_DOMAIN_DP_TX {
reg = <MT8195_POWER_DOMAIN_DP_TX>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
epd_tx@MT8195_POWER_DOMAIN_EPD_TX {
reg = <MT8195_POWER_DOMAIN_EPD_TX>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
hdmi_tx@MT8195_POWER_DOMAIN_HDMI_TX {
reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
clocks = <&topckgen CLK_TOP_HDMI_APB_SEL>;
clock-names = "hdmi_tx";
#power-domain-cells = <0>;
};
hdmi_rx@MT8195_POWER_DOMAIN_HDMI_RX {
reg = <MT8195_POWER_DOMAIN_HDMI_RX>;
clocks = <&topckgen CLK_TOP_HDMI_APB_SEL>;
clock-names = "hdmi_rx";
#power-domain-cells = <0>;
};
};
img@MT8195_POWER_DOMAIN_IMG {
reg = <MT8195_POWER_DOMAIN_IMG>;
clocks = <&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_GALS>;
clock-names = "img-0", "img-1";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
dip@MT8195_POWER_DOMAIN_DIP {
reg = <MT8195_POWER_DOMAIN_DIP>;
#power-domain-cells = <0>;
};
ipe@MT8195_POWER_DOMAIN_IPE {
reg = <MT8195_POWER_DOMAIN_IPE>;
clocks = <&topckgen CLK_TOP_IPE_SEL>,
<&imgsys CLK_IMG_IPE>,
<&ipesys CLK_IPE_SMI_LARB12>;
clock-names = "ipe", "ipe-0", "ipe-1";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
cam@MT8195_POWER_DOMAIN_CAM {
reg = <MT8195_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_CAM2MM0_GALS>,
<&camsys CLK_CAM_CAM2MM1_GALS>,
<&camsys CLK_CAM_CAM2SYS_GALS>;
clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
"cam-4";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
cam_rawa@MT8195_POWER_DOMAIN_CAM_RAWA {
reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
#power-domain-cells = <0>;
};
cam_rawb@MT8195_POWER_DOMAIN_CAM_RAWB {
reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
#power-domain-cells = <0>;
};
cam_mraw@MT8195_POWER_DOMAIN_CAM_MRAW {
reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
#power-domain-cells = <0>;
};
};
};
};
};
};
sleep: sleep@10006000 {
compatible = "mediatek,mt8195-sleep", "syscon";
reg = <0 0x10006000 0 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&srclken_pin>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
};
stc: stc@10008000 {
compatible = "mediatek,gpt-stc";
reg = <0 0x10008000 0 0x40>;
};
eint: apirq@1000b000 {
compatible = "mediatek,mtk-eint";
reg = <0 0x1000b000 0 0x1000>;
reg-name = "eint";
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,total-pin-number = <224>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8195-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
dbgtop@1000d000 {
compatible = "mediatek,dbgtop";
reg = <0 0x1000d000 0 0x1000>;
};
keypad: keypad@10010000 {
compatible = "mediatek,mt8195-keypad", "mediatek,kp";
reg = <0 0x10010000 0 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING 0>;
};
ddr_emi: dvfsrc@10012000 {
compatible = "mediatek,mt8195-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
reg-names = "dvfsrc";
#interconnect-cells = <1>;
dvfsrc_vcore: dvfsrc-vcore {
regulator-name = "dvfsrc-vcore";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
};
dvfsrc_vscp: dvfsrc-vscp {
regulator-name = "dvfsrc-vscp";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
};
dvfsrc_freq_opp6: opp6 {
opp-peak-KBps = <0>;
};
dvfsrc_freq_opp5: opp5 {
opp-peak-KBps = <2500000>;
};
dvfsrc_freq_opp4: opp4 {
opp-peak-KBps = <3800000>;
};
dvfsrc_freq_opp3: opp3 {
opp-peak-KBps = <5100000>;
};
dvfsrc_freq_opp2: opp2 {
opp-peak-KBps = <5900000>;
};
dvfsrc_freq_opp1: opp1 {
opp-peak-KBps = <7600000>;
};
dvfsrc_freq_opp0: opp0 {
opp-peak-KBps = <10200000>;
};
dvfsrc-helper {
compatible = "mediatek,dvfsrc-helper";
rc-vcore-supply = <&dvfsrc_vcore>;
rc-vscp-supply = <&dvfsrc_vscp>;
interconnects = <&ddr_emi MT8195_MASTER_DBGIF
&ddr_emi MT8195_SLAVE_DDR_EMI>,
<&ddr_emi MT8195_MASTER_DBGIF
&ddr_emi MT8195_SLAVE_DDR_EMI>,
<&ddr_emi MT8195_MASTER_HRT_DBGIF
&ddr_emi MT8195_SLAVE_HRT_DDR_EMI>;
interconnect-names = "icc-bw", "icc-perf-bw", "icc-hrt-bw";
required-opps = <&dvfsrc_freq_opp0>,
<&dvfsrc_freq_opp1>,
<&dvfsrc_freq_opp2>,
<&dvfsrc_freq_opp3>,
<&dvfsrc_freq_opp4>,
<&dvfsrc_freq_opp5>,
<&dvfsrc_freq_opp6>;
};
dvfsrc-met {
compatible = "mediatek,dvfsrc-met";
};
};
cec: cec@10014000 {
compatible = "mediatek,mt8195-cec";
reg = <0 0x10014000 0 0x100>;
interrupts = <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_CEC_66M_H>,
<&infracfg_ao CLK_INFRA_AO_CEC_66M_B>,
<&infracfg_ao CLK_INFRA_AO_HDMI_32K>,
<&infracfg_ao CLK_INFRA_AO_HDMI_26M>;
clock-names = "cec_66m_h",
"cec_66m_b",
"hdmi_32k",
"hdmi_26m";
hdmi = <&hdmi0>;
};
sys_timer@10017000 {
compatible = "mediatek,mt8195-timer";
reg = <0 0x10017000 0 0x1000>;
reg-names = "sys_timer_base";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_CLK26M_D2>;
};
pwrap: pwrap@10024000 {
compatible = "mediatek,mt8195-pwrap", "syscon";
reg = <0 0x10024000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
clock-names = "spi", "wrap";
assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
pinctrl-names = "default";
pinctrl-0 = <&pmif_pin>;
};
spmi: spmi@10027000 {
compatible = "mediatek,mt8195-spmi";
reg = <0 0x10027000 0 0x000e00>,
<0 0x10029000 0 0x000100>;
reg-names = "pmif", "spmimst";
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
irq_event_en = <0x18000000 0x0001c000 0x0 0x0 0x0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
<&topckgen CLK_TOP_SPMI_M_MST_SEL>;
clock-names = "pmif_sys_ck",
"pmif_tmr_ck",
"spmimst_clk_mux";
assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
};
pwm: pwm@10048000 {
compatible = "mediatek,mt8195-pwm";
reg = <0 0x10048000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PWM_H>,
<&infracfg_ao CLK_INFRA_AO_PWM>,
<&infracfg_ao CLK_INFRA_AO_PWM1>,
<&infracfg_ao CLK_INFRA_AO_PWM2>,
<&infracfg_ao CLK_INFRA_AO_PWM3>,
<&infracfg_ao CLK_INFRA_AO_PWM4>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4";
status = "disabled";
};
mcucfg@c530000 {
compatible = "mediatek,mcucfg";
reg = <0 0xc530000 0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
};
sys_cirq@10204000 {
compatible = "mediatek,sys_cirq";
reg = <0 0x10204000 0 0x1000>;
interrupts = <GIC_SPI 826 IRQ_TYPE_LEVEL_HIGH 0>;
};
systracker: systracker@10208000 {
compatible = "mediatek,bus_dbg-v2";
reg = <0 0x10208000 0 0x1000>,
<0 0x10001000 0 0x1000>;
mediatek,bus_dbg_con_offset = <0x2fc>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH 0>;
};
infracfg@1020e000 {
compatible = "mediatek,infracfg";
reg = <0 0x1020e000 0 0x1000>;
};
trng@1020f000 {
compatible = "mediatek,mt8195-rng";
reg = <0 0x1020f000 0 0x1000>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_TRNG>;
clock-names = "rng";
};
nnasys: syscon@10211000 {
compatible = "mediatek,mt8195-nnasys", "syscon";
reg = <0 0x10211000 0 0x1000>;
#clock-cells = <1>;
};
emicen: emicen@10219000 {
compatible = "mediatek,mt8195-emicen",
"mediatek,common-emicen";
reg = <0 0x10219000 0 0x1000>,
<0 0x1021d000 0 0x1000>;
mediatek,emi-reg = <&emichn>;
};
emimpu@10226000 {
compatible = "mediatek,mt8195-emimpu",
"mediatek,common-emimpu";
reg = <0 0x10226000 0 0x1000>,
<0 0x10225000 0 0x1000>;
mediatek,emi-reg = <&emicen>;
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 0>;
region_cnt = <32>;
domain_cnt = <16>;
addr_align = <16>;
ap_region = <31>;
ap_apc = <0 5 5 5 0 0 6 5>,
<0 0 5 0 0 0 5 5>;
dump = <0x1f0 0x1f8 0x1fc>;
clear = <0x160 0xffffffff 16>,
<0x200 0x00000003 16>,
<0x1f0 0x80000000 1>;
clear_md = <0x1fc 0x80000000 1>;
ctrl_intf = <1>;
slverr = <0>;
};
dramc@10230000 {
compatible = "mediatek,mt8195-dramc",
"mediatek,common-dramc";
reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
<0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
<0 0x10250000 0 0x2000>, /* DRAMC AO CHC */
<0 0x10260000 0 0x2000>, /* DRAMC AO CHD */
<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
<0 0x10254000 0 0x1000>, /* DRAMC NAO CHC */
<0 0x10264000 0 0x1000>, /* DRAMC NAO CHD */
<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
<0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
<0 0x10258000 0 0x2000>, /* DDRPHY AO CHC */
<0 0x10268000 0 0x2000>, /* DDRPHY AO CHD */
<0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */
<0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */
<0 0x10256000 0 0x1000>, /* DDRPHY NAO CHC */
<0 0x10266000 0 0x1000>, /* DDRPHY NAO CHD */
<0 0x10006000 0 0x1000>; /* SLEEP BASE */
mr4_version = <1>;
mr4_rg = <0x0090 0x0000ffff 0>;
fmeter_version = <1>;
crystal_freq = <52>;
pll_id = <0x050c 0x00000100 8>;
shu_lv = <0x050c 0x00030000 16>;
shu_of = <0x700>;
sdmpcw = <0x0704 0xffff0000 16>,
<0x0724 0xffff0000 16>;
prediv = <0x0708 0x000c0000 18>,
<0x0728 0x000c0000 18>;
posdiv = <0x0708 0x00000007 0>,
<0x0728 0x00000007 0>;
ckdiv4 = <0x0874 0x00000004 2>,
<0x0874 0x00000004 2>;
pll_md = <0x0744 0x00000100 8>,
<0x0744 0x00000100 8>;
cldiv2 = <0x08b4 0x00000002 1>,
<0x08b4 0x00000002 1>;
fbksel = <0x070c 0x00000040 6>,
<0x070c 0x00000040 6>;
dqsopen = <0x0870 0x00100000 20>,
<0x0870 0x00100000 20>;
dqopen = <0x0870 0x00200000 21>,
<0x0870 0x00200000 21>;
};
emichn: emichn@10235000 {
compatible = "mediatek,mt8195-emichn",
"mediatek,common-emichn";
reg = <0 0x10235000 0 0x1000>,
<0 0x10245000 0 0x1000>,
<0 0x10255000 0 0x1000>,
<0 0x10265000 0 0x1000>;
};
sys_cirq@10312000 {
compatible = "mediatek,sys_cirq";
reg = <0 0x10312000 0 0x1000>;
};
sys_cirq@10313000 {
compatible = "mediatek,sys_cirq";
reg = <0 0x10313000 0 0x1000>;
};
sys_cirq@10314000 {
compatible = "mediatek,sys_cirq";
reg = <0 0x10314000 0 0x1000>;
};
iommu4: infra-iommu@10315000 {
compatible = "mediatek,mt8195-iommu-infra";
reg = <0 0x10315000 0 0x5000>;
interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>;
clock-names = "bclk";
#iommu-cells = <1>;
};
gce_mbox: gce_mbox@10320000 {
compatible = "mediatek,mt8195-gce";
reg = <0 0x10320000 0 0x4000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <3>;
#gce-event-cells = <1>;
#gce-subsys-cells = <2>;
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
clock-names = "gce", "gce-d", "gce-timer";
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
<&infracfg_ao CLK_INFRA_AO_GCE2>,
<&infracfg_ao CLK_INFRA_AO_GCE_26M>;
};
gce_mbox_sec: gce_mbox_sec@10320000 {
compatible = "mediatek,mailbox-gce-sec";
reg = <0 0x10320000 0 0x4000>;
#mbox-cells = <3>;
mboxes = <&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
clock-names = "gce", "gce-d";
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
<&infracfg_ao CLK_INFRA_AO_GCE2>;
};
gce_mbox_d: gce_mbox_d@10330000 {
compatible = "mediatek,mt8195-gce-d";
reg = <0 0x10330000 0 0x4000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <3>;
#gce-event-cells = <1>;
#gce-subsys-cells = <2>;
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
clock-names = "gce", "gce-d", "gce-timer";
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
<&infracfg_ao CLK_INFRA_AO_GCE2>,
<&infracfg_ao CLK_INFRA_AO_GCE_26M>;
};
gce_mbox_d_sec: gce_mbox_d_sec@10330000 {
compatible = "mediatek,mailbox-gce-sec-d";
reg = <0 0x10330000 0 0x4000>;
#mbox-cells = <3>;
mboxes = <&gce_mbox_d 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
clock-names = "gce", "gce-d";
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
<&infracfg_ao CLK_INFRA_AO_GCE2>;
};
sspm@10400000 {
compatible = "mediatek,sspm";
reg = <0 0x10400000 0 0x28000>,
<0 0x10440000 0 0x10000>,
<0 0x10450000 0 0x100>,
<0 0x10451000 0 0x4>,
<0 0x10451004 0 0x4>,
<0 0x10460000 0 0x100>,
<0 0x10461000 0 0x4>,
<0 0x10461004 0 0x4>,
<0 0x10470000 0 0x100>,
<0 0x10471000 0 0x4>,
<0 0x10471004 0 0x4>,
<0 0x10480000 0 0x100>,
<0 0x10481000 0 0x4>,
<0 0x10481004 0 0x4>,
<0 0x10490000 0 0x100>,
<0 0x10491000 0 0x4>,
<0 0x10491004 0 0x4>;
reg-names = "sspm_base",
"cfgreg",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox4_base",
"mbox4_set",
"mbox4_clr";
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "ipc",
"mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4";
clock-names = "sspm",
"sspm_bus_h";
clocks = <&infracfg_ao CLK_INFRA_AO_PWRMCU>,
<&infracfg_ao CLK_INFRA_AO_PWRMCU_BUS_H>;
};
scp: scp@10700000 {
compatible = "mediatek,scp";
status = "okay";
reg = <0 0x10500000 0 0x100000>, /* tcm */
<0 0x10724000 0 0x1000>, /* cfg */
<0 0x10721000 0 0x1000>, /* clk*/
<0 0x10730000 0 0x1000>, /* cfg core0 */
<0 0x10740000 0 0x1000>, /* cfg core1 */
<0 0x10752000 0 0x1000>, /* bus tracker */
<0 0x10760000 0 0x40000>, /* llc */
<0 0x107a5000 0 0x4>, /* cfg_sec */
<0 0x107fb000 0 0x100>, /* mbox0 base */
<0 0x107fb100 0 0x4>, /* mbox0 set */
<0 0x107fb10c 0 0x4>, /* mbox0 clr */
<0 0x107a5020 0 0x4>, /* mbox0 init */
<0 0x107fc000 0 0x100>, /* mbox1 base */
<0 0x107fc100 0 0x4>, /* mbox1 set */
<0 0x107fc10c 0 0x4>, /* mbox1 clr */
<0 0x107a5024 0 0x4>, /* mbox1 init */
<0 0x107fd000 0 0x100>, /* mbox2 base */
<0 0x107fd100 0 0x4>, /* mbox2 set */
<0 0x107fd10c 0 0x4>, /* mbox2 clr */
<0 0x107a5028 0 0x4>, /* mbox2 init */
<0 0x107fe000 0 0x100>, /* mbox3 base */
<0 0x107fe100 0 0x4>, /* mbox3 set */
<0 0x107fe10c 0 0x4>, /* mbox3 clr */
<0 0x107a502c 0 0x4>, /* mbox3 init */
<0 0x107ff000 0 0x100>, /* mbox4 base */
<0 0x107ff100 0 0x4>, /* mbox4 set */
<0 0x107ff10c 0 0x4>, /* mbox4 clr */
<0 0x107a5030 0 0x4>; /* mbox4 init */
reg-names = "scp_sram_base",
"scp_cfgreg",
"scp_clkreg",
"scp_cfgreg_core0",
"scp_cfgreg_core1",
"scp_bus_tracker",
"scp_l1creg",
"scp_cfgreg_sec",
"mbox0_base",
"mbox0_set",
"mbox0_clr",
"mbox0_init",
"mbox1_base",
"mbox1_set",
"mbox1_clr",
"mbox1_init",
"mbox2_base",
"mbox2_set",
"mbox2_clr",
"mbox2_init",
"mbox3_base",
"mbox3_set",
"mbox3_clr",
"mbox3_init",
"mbox4_base",
"mbox4_set",
"mbox4_clr",
"mbox4_init";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "ipc0",
"ipc1",
"mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4";
core_0 = "enable";
scp_sramSize = <0x000c0000>;
pinctrl-names = "default";
pinctrl-0 = <&scp_default>;
scp_dvfs: scp_dvfs {
compatible = "mediatek,scp-dvfs";
dvfsrc-vscp-supply = <&dvfsrc_vscp>;
};
};
scp_adsp: syscon@10720000 {
compatible = "mediatek,mt8195-scp_adsp", "syscon";
reg = <0 0x10720000 0 0x1000>;
#clock-cells = <1>;
};
adsp: adsp@10803000 {
compatible = "mediatek,mt8195-audio_dsp";
reg = <0 0x10803000 0 0x1000>,
<0 0x10840000 0 0x40000>,
<0 0x10816000 0 0x1000>;
reg-names = "cfg", "sram", "mbox0";
interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>;
interrupts-name = "ipi", "wdt";
clocks = <&topckgen CLK_TOP_ADSP_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
<&topckgen CLK_TOP_MAINPLL_D7_D2>,
<&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
<&topckgen CLK_TOP_AUDIO_H_SEL>;
clock-names = "adsp_sel",
"clk26m_ck",
"audio_local_bus",
"mainpll_d7_d2",
"scp_adsp_audiodsp",
"audio_h_sel";
memory-region = <&adsp_mem_reserved>;
power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
};
audsys: syscon@10890000 {
compatible = "mediatek,mt8195-audsys", "syscon";
reg = <0 0x10890000 0 0x10000>;
#clock-cells = <1>;
afe: audio-controller {
compatible = "mediatek,mt8195-audio";
topckgen = <&topckgen>;
power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&apmixedsys CLK_APMIXED_APLL1>,
<&apmixedsys CLK_APMIXED_APLL2>,
<&apmixedsys CLK_APMIXED_APLL3>,
<&apmixedsys CLK_APMIXED_APLL4>,
<&apmixedsys CLK_APMIXED_APLL5>,
<&apmixedsys CLK_APMIXED_HDMIRX_APLL>,
<&topckgen CLK_TOP_APLL1>,
<&topckgen CLK_TOP_APLL1_D4>,
<&topckgen CLK_TOP_APLL2>,
<&topckgen CLK_TOP_APLL2_D4>,
<&topckgen CLK_TOP_APLL3>,
<&topckgen CLK_TOP_APLL3_D4>,
<&topckgen CLK_TOP_APLL4>,
<&topckgen CLK_TOP_APLL4_D4>,
<&topckgen CLK_TOP_APLL5>,
<&topckgen CLK_TOP_APLL5_D4>,
<&topckgen CLK_TOP_APLL12_DIV0>,
<&topckgen CLK_TOP_APLL12_DIV1>,
<&topckgen CLK_TOP_APLL12_DIV2>,
<&topckgen CLK_TOP_APLL12_DIV3>,
<&topckgen CLK_TOP_APLL12_DIV4>,
<&topckgen CLK_TOP_APLL12_DIV9>,
<&topckgen CLK_TOP_HDMIRX_APLL>,
<&topckgen CLK_TOP_MAINPLL_D4_D4>,
<&topckgen CLK_TOP_MAINPLL_D5_D2>,
<&topckgen CLK_TOP_MAINPLL_D7_D2>,
<&topckgen CLK_TOP_UNIVPLL_D4>,
<&topckgen CLK_TOP_APLL1_SEL>,
<&topckgen CLK_TOP_APLL2_SEL>,
<&topckgen CLK_TOP_APLL3_SEL>,
<&topckgen CLK_TOP_APLL4_SEL>,
<&topckgen CLK_TOP_APLL5_SEL>,
<&topckgen CLK_TOP_A1SYS_HP_SEL>,
<&topckgen CLK_TOP_A2SYS_SEL>,
<&topckgen CLK_TOP_A3SYS_SEL>,
<&topckgen CLK_TOP_A4SYS_SEL>,
<&topckgen CLK_TOP_ASM_H_SEL>,
<&topckgen CLK_TOP_ASM_M_SEL>,
<&topckgen CLK_TOP_ASM_L_SEL>,
<&topckgen CLK_TOP_AUD_IEC_SEL>,
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&topckgen CLK_TOP_AUDIO_H_SEL>,
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
<&topckgen CLK_TOP_DPTX_M_SEL>,
<&topckgen CLK_TOP_INTDIR_SEL>,
<&topckgen CLK_TOP_I2SO1_M_SEL>,
<&topckgen CLK_TOP_I2SO2_M_SEL>,
<&topckgen CLK_TOP_I2SI1_M_SEL>,
<&topckgen CLK_TOP_I2SI2_M_SEL>,
<&topckgen CLK_TOP_MPHONE_SLAVE_B>,
<&topckgen CLK_TOP_CFG_26M_AUD>,
<&infracfg_ao CLK_INFRA_AO_AUDIO>,
<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
<&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_LRCK_CNT>,
<&audsys CLK_AUD_SPDIFIN_TUNER_APLL>,
<&audsys CLK_AUD_SPDIFIN_TUNER_DBG>,
<&audsys CLK_AUD_UL_TML>,
<&audsys CLK_AUD_APLL1_TUNER>,
<&audsys CLK_AUD_APLL2_TUNER>,
<&audsys CLK_AUD_TOP0_SPDF>,
<&audsys CLK_AUD_APLL>,
<&audsys CLK_AUD_APLL2>,
<&audsys CLK_AUD_DAC>,
<&audsys CLK_AUD_DAC_PREDIS>,
<&audsys CLK_AUD_TML>,
<&audsys CLK_AUD_ADC>,
<&audsys CLK_AUD_DAC_HIRES>,
<&audsys CLK_AUD_A1SYS_HP>,
<&audsys CLK_AUD_AFE_DMIC1>,
<&audsys CLK_AUD_AFE_DMIC2>,
<&audsys CLK_AUD_AFE_DMIC3>,
<&audsys CLK_AUD_AFE_DMIC4>,
<&audsys CLK_AUD_AFE_26M_DMIC_TM>,
<&audsys CLK_AUD_UL_TML_HIRES>,
<&audsys CLK_AUD_ADC_HIRES>,
<&audsys CLK_AUD_ADDA6_ADC>,
<&audsys CLK_AUD_ADDA6_ADC_HIRES>,
<&audsys CLK_AUD_LINEIN_TUNER>,
<&audsys CLK_AUD_EARC_TUNER>,
<&audsys CLK_AUD_I2SIN>,
<&audsys CLK_AUD_TDM_IN>,
<&audsys CLK_AUD_I2S_OUT>,
<&audsys CLK_AUD_TDM_OUT>,
<&audsys CLK_AUD_HDMI_OUT>,
<&audsys CLK_AUD_ASRC11>,
<&audsys CLK_AUD_ASRC12>,
<&audsys CLK_AUD_MULTI_IN>,
<&audsys CLK_AUD_INTDIR>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_PCMIF>,
<&audsys CLK_AUD_A3SYS>,
<&audsys CLK_AUD_A4SYS>,
<&audsys CLK_AUD_MEMIF_UL1>,
<&audsys CLK_AUD_MEMIF_UL2>,
<&audsys CLK_AUD_MEMIF_UL3>,
<&audsys CLK_AUD_MEMIF_UL4>,
<&audsys CLK_AUD_MEMIF_UL5>,
<&audsys CLK_AUD_MEMIF_UL6>,
<&audsys CLK_AUD_MEMIF_UL8>,
<&audsys CLK_AUD_MEMIF_UL9>,
<&audsys CLK_AUD_MEMIF_UL10>,
<&audsys CLK_AUD_MEMIF_DL2>,
<&audsys CLK_AUD_MEMIF_DL3>,
<&audsys CLK_AUD_MEMIF_DL6>,
<&audsys CLK_AUD_MEMIF_DL7>,
<&audsys CLK_AUD_MEMIF_DL8>,
<&audsys CLK_AUD_MEMIF_DL10>,
<&audsys CLK_AUD_MEMIF_DL11>,
<&audsys CLK_AUD_GASRC0>,
<&audsys CLK_AUD_GASRC1>,
<&audsys CLK_AUD_GASRC2>,
<&audsys CLK_AUD_GASRC3>,
<&audsys CLK_AUD_GASRC4>,
<&audsys CLK_AUD_GASRC5>,
<&audsys CLK_AUD_GASRC6>,
<&audsys CLK_AUD_GASRC7>,
<&audsys CLK_AUD_GASRC8>,
<&audsys CLK_AUD_GASRC9>,
<&audsys CLK_AUD_GASRC10>,
<&audsys CLK_AUD_GASRC11>,
<&audsys CLK_AUD_GASRC12>,
<&audsys CLK_AUD_GASRC13>,
<&audsys CLK_AUD_GASRC14>,
<&audsys CLK_AUD_GASRC15>,
<&audsys CLK_AUD_GASRC16>,
<&audsys CLK_AUD_GASRC17>,
<&audsys CLK_AUD_GASRC18>,
<&audsys CLK_AUD_GASRC19>;
clock-names = "clk26m",
"apll1",
"apll2",
"apll3",
"apll4",
"apll5",
"hdmirx_apll",
"apll1_ck",
"apll1_d4",
"apll2_ck",
"apll2_d4",
"apll3_ck",
"apll3_d4",
"apll4_ck",
"apll4_d4",
"apll5_ck",
"apll5_d4",
"apll12_div0",
"apll12_div1",
"apll12_div2",
"apll12_div3",
"apll12_div4",
"apll12_div9",
"hdmirx_apll_ck",
"mainpll_d4_d4",
"mainpll_d5_d2",
"mainpll_d7_d2",
"univpll_d4",
"apll1_sel",
"apll2_sel",
"apll3_sel",
"apll4_sel",
"apll5_sel",
"a1sys_hp_sel",
"a2sys_sel",
"a3sys_sel",
"a4sys_sel",
"asm_h_sel",
"asm_m_sel",
"asm_l_sel",
"aud_iec_sel",
"aud_intbus_sel",
"audio_h_sel",
"audio_local_bus_sel",
"dptx_m_sel",
"intdir_sel",
"i2so1_m_sel",
"i2so2_m_sel",
"i2si1_m_sel",
"i2si2_m_sel",
"mphone_slave_b",
"cfg_26m_aud",
"infra_ao_audio",
"infra_ao_audio_26m_b",
"scp_adsp_audiodsp",
"aud_afe",
"aud_lrck_cnt",
"aud_spdifin_tuner_apll",
"aud_spdifin_tuner_dbg",
"aud_ul_tml",
"aud_apll1_tuner",
"aud_apll2_tuner",
"aud_top0_spdf",
"aud_apll",
"aud_apll2",
"aud_dac",
"aud_dac_predis",
"aud_tml",
"aud_adc",
"aud_dac_hires",
"aud_a1sys_hp",
"aud_afe_dmic1",
"aud_afe_dmic2",
"aud_afe_dmic3",
"aud_afe_dmic4",
"aud_afe_26m_dmic_tm",
"aud_ul_tml_hires",
"aud_adc_hires",
"aud_adda6_adc",
"aud_adda6_adc_hires",
"aud_linein_tuner",
"aud_earc_tuner",
"aud_i2sin",
"aud_tdm_in",
"aud_i2s_out",
"aud_tdm_out",
"aud_hdmi_out",
"aud_asrc11",
"aud_asrc12",
"aud_multi_in",
"aud_intdir",
"aud_a1sys",
"aud_a2sys",
"aud_pcmif",
"aud_a3sys",
"aud_a4sys",
"aud_memif_ul1",
"aud_memif_ul2",
"aud_memif_ul3",
"aud_memif_ul4",
"aud_memif_ul5",
"aud_memif_ul6",
"aud_memif_ul8",
"aud_memif_ul9",
"aud_memif_ul10",
"aud_memif_dl2",
"aud_memif_dl3",
"aud_memif_dl6",
"aud_memif_dl7",
"aud_memif_dl8",
"aud_memif_dl10",
"aud_memif_dl11",
"aud_gasrc0",
"aud_gasrc1",
"aud_gasrc2",
"aud_gasrc3",
"aud_gasrc4",
"aud_gasrc5",
"aud_gasrc6",
"aud_gasrc7",
"aud_gasrc8",
"aud_gasrc9",
"aud_gasrc10",
"aud_gasrc11",
"aud_gasrc12",
"aud_gasrc13",
"aud_gasrc14",
"aud_gasrc15",
"aud_gasrc16",
"aud_gasrc17",
"aud_gasrc18",
"aud_gasrc19";
status = "disabled";
adsp_pcm: mt8195-adsp-pcm {
compatible = "mediatek,mt8195-adsp";
reg = <0 0x10880000 0 0x10000>;
status = "disabled";
};
};
};
audsys_src: syscon@108a0000 {
compatible = "mediatek,mt8195-audsys_src", "syscon";
reg = <0 0x108a0000 0 0x2000>;
#clock-cells = <1>;
audio_asrc: audio_asrc {
compatible = "mediatek,mt8195-audio-asrc";
power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO_ASRC>;
interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_ASM_H_SEL>,
<&apmixedsys CLK_APMIXED_APLL1>,
<&apmixedsys CLK_APMIXED_APLL2>,
<&audsys_src CLK_AUD_SRC_ASRC0>,
<&audsys_src CLK_AUD_SRC_ASRC1>,
<&audsys_src CLK_AUD_SRC_ASRC2>,
<&audsys_src CLK_AUD_SRC_ASRC3>,
<&audsys_src CLK_AUD_SRC_ASRC4>,
<&audsys_src CLK_AUD_SRC_ASRC5>,
<&audsys_src CLK_AUD_SRC_ASRC6>,
<&audsys_src CLK_AUD_SRC_ASRC7>,
<&audsys_src CLK_AUD_SRC_ASRC8>,
<&audsys_src CLK_AUD_SRC_ASRC9>,
<&audsys_src CLK_AUD_SRC_ASRC10>,
<&audsys_src CLK_AUD_SRC_ASRC11>,
<&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
clock-names = "asm_h_sel",
"apll1",
"apll2",
"asrc0",
"asrc1",
"asrc2",
"asrc3",
"asrc4",
"asrc5",
"asrc6",
"asrc7",
"asrc8",
"asrc9",
"asrc10",
"asrc11",
"scp_adsp_audiodsp";
status = "disabled";
};
};
uart0: serial@11001100 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11001100 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "baud", "bus";
};
auxadc: adc@11002000 {
compatible = "mediatek,mt8195-auxadc";
reg = <0 0x11002000 0 0x1000>;
clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
clock-names = "main";
#io-channel-cells = <1>;
nvmem-cells = <&auxadc_cali>;
nvmem-cell-names = "auxadc-efuse";
status = "disabled";
};
pericfg_ao: syscon@11003000 {
compatible = "mediatek,mt8195-pericfg_ao", "syscon";
reg = <0 0x11003000 0 0x1000>;
#clock-cells = <1>;
};
spi0: spi@1100a000 {
compatible = "mediatek,mt8195-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg_ao CLK_INFRA_AO_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
svs: svs@1100b000 {
compatible = "mediatek,mt8195-svs";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
clock-names = "main";
nvmem-cells = <&svs_calibration>,
<&lvts_e_data1>;
nvmem-cell-names = "svs-calibration-data",
"t-calibration-data";
resets = <&infracfg_rst 0>;
reset-names = "svs_rst";
};
lvts: lvts@1100b000 {
compatible = "mediatek,mt8195-lvts";
#thermal-sensor-cells = <1>;
reg = <0 0x1100b000 0 0x1000>,
<0 0x11278000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
clock-names = "lvts_clk";
resets = <&infracfg_rst 1>,
<&infracfg_rst 2>;
nvmem-cells = <&lvts_e_data1 &lvts_e_data2>;
nvmem-cell-names = "e_data1","e_data2";
};
disp_pwm0: disp_pwm0@1100e000 {
compatible = "mediatek,mt8195-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
#pwm-cells = <2>;
clocks = <&topckgen CLK_TOP_DISP_PWM0_SEL>,
<&infracfg_ao CLK_INFRA_AO_DISP_PWM>,
<&topckgen CLK_TOP_ULPOSC_D4>;
clock-names = "main", "mm", "pwm_src";
status = "disabled";
};
disp_pwm1: disp_pwm1@1100f000 {
compatible = "mediatek,mt8195-disp-pwm";
reg = <0 0x1100f000 0 0x1000>;
interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_DISP_PWM1_SEL>,
<&infracfg_ao CLK_INFRA_AO_DISP_PWM1>,
<&topckgen CLK_TOP_ULPOSC_D4>;
clock-names = "main", "mm", "pwm_src";
status = "disabled";
};
spi1: spi@11010000 {
compatible = "mediatek,mt8195-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11010000 0 0x100>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg_ao CLK_INFRA_AO_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi2: spi@11012000 {
compatible = "mediatek,mt8195-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11012000 0 0x100>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg_ao CLK_INFRA_AO_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi3: spi@11013000 {
compatible = "mediatek,mt8195-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11013000 0 0x100>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg_ao CLK_INFRA_AO_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi4: spi@11018000 {
compatible = "mediatek,mt8195-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11018000 0 0x100>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg_ao CLK_INFRA_AO_SPI4>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi5: spi@11019000 {
compatible = "mediatek,mt8195-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11019000 0 0x100>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg_ao CLK_INFRA_AO_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spis0: spi@1101d000 {
compatible = "mediatek,mt8195-spi-slave";
reg = <0 0x1101d000 0 0x100>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
clock-names = "spi";
assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
status = "disabled";
};
spis1: spi@1101e000 {
compatible = "mediatek,mt8195-spi-slave";
reg = <0 0x1101e000 0 0x100>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
clock-names = "spi";
assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
status = "disabled";
};
eth: ethernet@11021000 {
compatible = "mediatek,mt8195-gmac";
reg = <0 0x11021000 0 0x4000>;
interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "macirq";
mac-address = [00 55 7b b5 7d f7];
clock-names = "axi",
"apb",
"mac_cg",
"mac_main",
"ptp_ref",
"rmii_internal";
clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
<&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
<&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>,
<&topckgen CLK_TOP_SNPS_ETH_250M_SEL>,
<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
<&topckgen CLK_TOP_SNPS_ETH_50M_RMII_SEL>;
assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M_SEL>,
<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
<&topckgen CLK_TOP_SNPS_ETH_50M_RMII_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
<&topckgen CLK_TOP_ETHPLL_D8>,
<&topckgen CLK_TOP_ETHPLL_D10>;
power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
mediatek,infracfg_ao = <&infracfg_ao>;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,txpbl = <1>;
snps,rxpbl = <1>;
clk_csr = <0>;
status = "disabled";
};
ssusb: usb@11201000 {
compatible = "mediatek,mt8195-mtu3";
reg = <0 0x11201000 0 0x2dff>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>;
assigned-clocks = <&topckgen CLK_TOP_USB_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
<&topckgen CLK_TOP_SSUSB_REF>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 5>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host0: xhci@11200000 {
compatible = "mediatek,mt8195-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts-extended = <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>,
<&pio 219 IRQ_TYPE_EDGE_FALLING>;
assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
clock-names = "sys_ck";
status = "disabled";
};
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8195-mmc";
reg = <0 0x11230000 0 0x10000>,
<0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
<&infracfg_ao CLK_INFRA_AO_MSDC0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
<&infracfg_ao CLK_INFRA_AO_AES_MSDCFDE_0P>;
clock-names = "source", "hclk", "source_cg", "crypto_clk";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt8195-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11c70000 0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
<&infracfg_ao CLK_INFRA_AO_MSDC1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
clock-names = "source", "hclk", "source_cg";
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
status = "disabled";
};
ufshci@11270000 {
compatible = "mediatek,mt8183-ufshci";
reg = <0 0x11270000 0 0x2300>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&ufsphy>;
bootmode = <&chosen>;
clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>,
<&infracfg_ao CLK_INFRA_AO_AES>,
<&infracfg_ao CLK_INFRA_AO_UFS_TICK>,
<&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>,
<&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>,
<&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>,
<&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>,
<&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>;
clock-names = "ufshci", "ufs_aes", "ufs_tick",
"unipro_sysclk", "unipro_tick",
"unipro_mp_bclk", "ufs_tx_symbol",
"ufs_mem_sub";
freq-table-hz = <0 0>, <0 0>, <0 0>,
<0 0>, <0 0>, <0 0>,
<0 0>, <0 0>;
/* vcc-supply = <&mt_pmic_vemc_ldo_reg>;*/
vcc-fixed-regulator;
/* Number of lanes available per direction - either 1 or 2 */
lanes-per-direction = <2>;
/* Auto-Hibern8 Timer. Unit: ms (0 means disabled) */
mediatek,auto-hibern8-timer = <10>;
/* System Suspend Level */
mediatek,spm-level = <3>;
/* Runtime Suspend Configuration, 1. Runtime PM on/off (on: 1, off: 0) */
mediatek,rpm-enable = <1>;
/* 2. Auto Suspend Delay. Unit: ms */
mediatek,rpm-autosuspend-delay = <2000>;
/* 3. Runtime Suspend Level */
mediatek,rpm-level = <3>;
/* Performance Mode */
mediatek,perf-crypto-vcore = <2>;
/* Reference clock control mode, SW mode: 0, Half-HW mode: 1, HW mode: 2 */
};
usb30: xhci30@11290000 {
compatible = "mediatek,mt8195-xhci";
reg = <0 0x11290000 0 0x1000>,
<0 0x11293e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts-extended = <&gic GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>,
<&pio 218 IRQ_TYPE_EDGE_FALLING>;
assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>,
<&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
<&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
<&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
<&topckgen CLK_TOP_SSUSB_P1_REF>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 3>;
status = "disabled";
};
ssusb1: usb1@112a1000 {
compatible = "mediatek,mt8195-mtu3";
reg = <0 0x112a1000 0 0x2dff>,
<0 0x112a3e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&u2port2 PHY_TYPE_USB2>;
assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
<&topckgen CLK_TOP_SSUSB_P2_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host1: xhci1@112a0000 {
compatible = "mediatek,mt8195-xhci";
reg = <0 0x112a0000 0 0x1000>;
reg-names = "mac";
interrupts-extended = <&gic GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>,
<&pio 220 IRQ_TYPE_EDGE_FALLING>;
assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck";
status = "disabled";
};
};
ssusb2: usb2@112b1000 {
compatible = "mediatek,mt8195-mtu3";
reg = <0 0x112b1000 0 0x2dff>,
<0 0x112b3e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&u2port3 PHY_TYPE_USB2>;
assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
<&topckgen CLK_TOP_SSUSB_P3_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host2: xhci2@112b0000 {
compatible = "mediatek,mt8195-xhci";
reg = <0 0x112b0000 0 0x1000>;
reg-names = "mac";
interrupts-extended = <&gic GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>,
<&pio 221 IRQ_TYPE_EDGE_FALLING>;
assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck";
status = "disabled";
};
};
pcie0: pcie@112f0000 {
compatible = "mediatek,mt8195-pcie";
reg = <0 0x112f0000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000
0x0 0x20000000 0 0x04000000>;
iommu-map = <0x0000 &iommu4 M4U_PORT_INFRA_PCIE0_BASE 0xFFFF>;
iommu-map-mask = <0x0>;
status = "disabled";
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
<&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>;
phys = <&pciephy0>;
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@112f8000 {
compatible = "mediatek,mt8195-pcie";
reg = <0 0x112f8000 0 0x2000>;
reg-names = "pcie-mac";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x24000000
0x0 0x24000000 0 0x04000000>;
iommu-map = <0x0000 &iommu4 M4U_PORT_INFRA_PCIE1_BASE 0xFFFF>;
iommu-map-mask = <0x0>;
status = "disabled";
resets = <&infracfg_rst 3>;
reset-names = "phy-rst";
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
<&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>;
phys = <&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
nor_flash: nor@1132C000 {
compatible = "mediatek,mt8173-nor";
reg = <0 0x1132C000 0 0x1000>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_SPINOR_SEL>,
<&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>;
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
efuse: efuse@11c10000 {
compatible = "mediatek,devinfo";
reg = <0 0x11c10000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
edp_calibration: edp_data {
reg = <0x1ac 0x10>;
};
dp_calibration: dp_data {
reg = <0x1ac 0x10>;
};
lvts_e_data1: data1 {
reg = <0x1cc 0x14>;
};
lvts_e_data2: data1-1 {
reg = <0x2f8 0x38>;
};
hdmirx_efuse: data2 {
reg = <0x01c 0xc>;
};
hdmirx_rterm: data3 {
reg = <0x1bc 0x4>;
};
hdmitx_efuse: calib@190 {
reg = <0x190 0x4>;
};
svs_calibration: calib@c8 {
reg = <0xc8 0x64>;
};
gpu_segment_table: gpu_efuse1 {
reg = <0x20c 0x4>;
};
auxadc_cali: auxadc_efuse {
reg = <0x330 0x15>;
};
pcie_calibration: calib@1a0 {
reg = <0x1a0 0x4>;
};
csi_efuse0: csi_data0 {
reg = <0x1a4 0x4>;
};
csi_efuse1: csi_data1 {
reg = <0x1a8 0x4>;
};
csi_efuse2: csi_data2 {
reg = <0x1ac 0x4>;
};
};
u3phy2: usb-phy2@11c40000 {
compatible = "mediatek,mt8195-tphy",
"mediatek,generic-tphy-v3";
clocks = <&clk26m>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
u2port2: usb2-phy2@11c40000 {
reg = <0 0x11c40000 0 0x700>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
clock-names = "ref";
mediatek,eye-rev6 = <1>;
#phy-cells = <1>;
status = "disabled";
};
};
u3phy3: usb-phy3@11c50000 {
compatible = "mediatek,mt8195-tphy",
"mediatek,generic-tphy-v3";
clocks = <&clk26m>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
u2port3: usb2-phy3@11c50000 {
reg = <0 0x11c50000 0 0x700>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
clock-names = "ref";
mediatek,eye-rev6 = <1>;
#phy-cells = <1>;
status = "disabled";
};
};
mipi_tx_config0: mipi_dphy0@11c80000 {
compatible = "mediatek,mt8195-mipi-tx";
reg = <0 0x11c80000 0 0x1000>;
clocks = <&clk26m>;
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "mipi_tx0_pll";
status = "disabled";
};
mipi_tx_config1: mipi_dphy1@11c90000 {
compatible = "mediatek,mt8195-mipi-tx";
reg = <0 0x11c90000 0 0x1000>;
clocks = <&clk26m>;
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "mipi_tx1_pll";
status = "disabled";
};
i2c5: i2c@11d00000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11d00000 0 0x1000>,
<0 0x10220580 0 0x80>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@11d01000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11d01000 0 0x1000>,
<0 0x10220600 0 0x80>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@11d02000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11d02000 0 0x1000>,
<0 0x10220680 0 0x80>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
imp_iic_wrap_s: syscon@11d03000 {
compatible = "mediatek,mt8195-imp_iic_wrap_s", "syscon";
reg = <0 0x11d03000 0 0x1000>;
#clock-cells = <1>;
};
hdmi_phy: hdmi-phy@11d5f000 {
compatible = "mediatek,mt8195-hdmi-phy";
nvmem-cells = <&hdmitx_efuse>;
nvmem-cell-names = "hdmitx_phy_efuse";
reg = <0 0x11d5f000 0 0x100>;
clocks = <&topckgen CLK_TOP_HDMI_XTAL_SEL>;
clock-names = "hdmi_xtal_sel";
clock-output-names = "hdmi_txpll";
#clock-cells = <0>;
#phy-cells = <0>;
};
i2c0: i2c@11e00000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11e00000 0 0x1000>,
<0 0x10220080 0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11e01000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11e01000 0 0x1000>,
<0 0x10220200 0 0x80>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11e02000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11e02000 0 0x1000>,
<0 0x10220380 0 0x80>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@11e03000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11e03000 0 0x1000>,
<0 0x10220480 0 0x80>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@11e04000 {
compatible = "mediatek,mt8195-i2c";
reg = <0 0x11e04000 0 0x1000>,
<0 0x10220500 0 0x80>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
<&infracfg_ao CLK_INFRA_AO_APDMA_B>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
imp_iic_wrap_w: syscon@11e05000 {
compatible = "mediatek,mt8195-imp_iic_wrap_w", "syscon";
reg = <0 0x11e05000 0 0x1000>;
#clock-cells = <1>;
};
u3phy1: usb-phy1@11e30000 {
compatible = "mediatek,mt8195-tphy",
"mediatek,generic-tphy-v3";
clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
status = "disabled";
u2port1: usb2-phy1@11e30000 {
reg = <0 0x11e30000 0 0x700>;
clocks = <&apmixedsys CLK_APMIXED_USB1PLL>;
clock-names = "ref";
mediatek,eye-rev6 = <1>;
#phy-cells = <1>;
status = "disabled";
};
u3port1: usb3-phy1@11e30700 {
reg = <0 0x11e30700 0 0x700>;
clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>;
clock-names = "ref";
#phy-cells = <1>;
status = "disabled";
};
};
u3phy0: usb-phy0@11e40000 {
compatible = "mediatek,mt8195-tphy",
"mediatek,generic-tphy-v3";
clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
u2port0: usb2-phy0@11e40000 {
reg = <0 0x11e40000 0 0x700>;
clocks = <&apmixedsys CLK_APMIXED_USB1PLL>;
clock-names = "ref";
mediatek,eye-rev6 = <1>;
#phy-cells = <1>;
status = "disabled";
};
u3port0: usb3-phy0@11e40700 {
reg = <0 0x11e40700 0 0x700>;
clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>;
clock-names = "ref";
#phy-cells = <1>;
status = "disabled";
};
};
pciephy0: phy0@11e80000 {
compatible = "mediatek,mt8195-pcie-phy";
#address-cells = <2>;
#size-cells = <2>;
#phy-cells = <0>;
reg = <0 0x11e80000 0 0x10000>,
<0 0x11e90000 0 0x10000>;
reg-names = "phy-sif", "phy-ckm";
nvmem-cells = <&pcie_calibration>;
nvmem-cell-names = "pciegen3_efuse_segment";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
};
ufsphy: phy@11fa0000 {
compatible = "mediatek,mt8183-ufsphy";
reg = <0 0x11fa0000 0 0xc000>;
};
mali: mali@13000000 {
compatible = "mediatek,mali", "arm,mali-valhall";
reg = <0 0x13000000 0 0x4000>;
interrupts =
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names =
"GPU",
"MMU",
"JOB",
"EVENT",
"PWR";
operating-points-v2 = <&gpu_mali_opp>;
#cooling-cells = <2>;
ion-supply = <&ion>;
gpufreq-supply = <&gpufreq>;
};
mali_dvfs_hint@13fbb000 {
compatible = "mediatek,mali_dvfs_hint", "syscon";
reg = <0 0x13fbb000 0 0x1000>;
};
g3d_secure_reg@13fbc000 {
compatible = "mediatek,g3d_secure_reg";
reg = <0 0x13fbc000 0 0x1000>;
};
g3d_testbench@13fbd000 {
compatible = "mediatek,g3d_testbench", "syscon";
reg = <0 0x13fbd000 0 0x1000>;
};
mfgcfg: syscon@13fbf000 {
compatible = "mediatek,mt8195-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
vppsys0: syscon@14000000 {
compatible = "mediatek,mt8195-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
vpp0_mutex: vpp0_mutex@1400f000 {
compatible = "mediatek,vpp0_mutex";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
#clock-names = "MDP_MUTEX0";
clocks = <&vppsys0 CLK_VPP0_MUTEX>;
clock-names = "MDP_MUTEX0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_rdma0: mdp_rdma0@14001000 {
compatible = "mediatek,mdp_rdma0", "mediatek,mdp";
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>,
<&infracfg_ao CLK_INFRA_AO_GCE>,
<&infracfg_ao CLK_INFRA_AO_GCE_26M>,
<&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>,
<&vppsys0 CLK_VPP0_WARP1_ASYNC_TX>,
<&vppsys0 CLK_VPP0_VPP02VPP1_RELAY>,
<&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>,
<&vppsys0 CLK_VPP0_MMSYSRAM_TOP>,
<&vppsys0 CLK_VPP0_WARP0_RELAY>,
<&vppsys0 CLK_VPP0_WARP0_MDP_DL_ASYNC>,
<&vppsys0 CLK_VPP0_WARP1_RELAY>,
<&vppsys0 CLK_VPP0_WARP1_MDP_DL_ASYNC>,
<&vppsys1 CLK_VPP1_SVPP2_VDO0_DL_RELAY>,
<&vppsys1 CLK_VPP1_SVPP3_VDO1_DL_RELAY>,
<&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
<&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
<&vppsys1 CLK_VPP1_DL_ASYNC>,
<&vppsys1 CLK_VPP1_SVPP2_VDO1_DL_RELAY>,
<&vppsys1 CLK_VPP1_SVPP3_VDO0_DL_RELAY>,
<&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>,
<&vppsys1 CLK_VPP1_HDMI_META>,
<&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
<&vppsys1 CLK_VPP1_DGI_IN>,
<&vppsys1 CLK_VPP1_DGI_OUT>,
<&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
<&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>,
<&vppsys1 CLK_VPP1_VPP0_DL_RELAY>,
<&vppsys1 CLK_VPP1_VPP_SPLIT_26M>,
<&topckgen CLK_TOP_CFG_VPP0>,
<&topckgen CLK_TOP_CFG_26M_VPP0>,
<&topckgen CLK_TOP_CFG_VPP1>,
<&topckgen CLK_TOP_CFG_26M_VPP1>;
clock-names = "MDP_RDMA0",
"GCE",
"GCE_TIMER",
"WARP0_ASYNC_TX",
"WARP1_ASYNC_TX",
"VPP02VPP1_RELAY",
"VPP12VPP0_ASYNC",
"MMSYSRAM_TOP",
"WARP0_RELAY",
"WARP0_MDP_DL_ASYNC",
"WARP1_RELAY",
"WARP1_MDP_DL_ASYNC",
"SVPP2_VDO0_DL_RELAY",
"SVPP3_VDO1_DL_RELAY",
"VPPSYS1_GALS",
"VPPSYS1_LARB",
"VPP0_DL_ASYNC_VPP1",
"SVPP2_VDO1_DL_RELAY",
"SVPP3_VDO0_DL_RELAY",
"VPP0_DL1_RELAY",
"HDMI_META",
"SPLIT_HDMI",
"DGI_IN",
"DGI_OUT",
"SPLIT_DGI",
"VPP0_DL_ASYNC_VPP0",
"VPP0_DL_RELAY",
"VPP_SPLIT_26M",
"TOP_CFG_VPP0",
"TOP_CFG_26M_VPP0",
"TOP_CFG_VPP1",
"TOP_CFG_26M_VPP1";
operating-points-v2 = <&opp_table_vpp>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_MDP_RDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_SVPP1_MDP_RDMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_SVPP2_MDP_RDMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L6_SVPP3_MDP_RDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L4_MDP_WROT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_SVPP1_MDP_WROT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L5_SVPP2_MDP_WROT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L6_SVPP3_MDP_WROT)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"l4_mdp_rdma",
"l5_svpp1_mdp_rdma",
"l5_svpp2_mdp_rdma",
"l6_svpp3_mdp_rdma",
"l4_mdp_wrot",
"l5_svpp1_mdp_wrot",
"l5_svpp2_mdp_wrot",
"l6_svpp3_mdp_wrot";
mmsys2_config = <&vppsys1>;
mm_mutex2 = <&vpp1_mutex>;
mmsys_config = <&vppsys0>;
mm_mutex = <&vpp0_mutex>;
mboxes =
<&gce_mbox 13 1000 CMDQ_THR_PRIO_1>,
<&gce_mbox 14 1000 CMDQ_THR_PRIO_1>,
<&gce_mbox 16 1000 CMDQ_THR_PRIO_1>,
<&gce_mbox 21 1000 CMDQ_THR_PRIO_1>,
<&gce_mbox 22 1000 CMDQ_THR_PRIO_1>;
/* To be removed after DRM enabled --> */
/* To Do: refine after mdp3 */
mdp_rdma0 = <&mdp_rdma0>;
mdp_rdma1 = <&svpp1_mdp_rdma>;
mdp_rdma2 = <&svpp2_mdp_rdma>;
mdp_rdma3 = <&svpp3_mdp_rdma>;
mdp_stitch = <&mdp_stich0>;
mdp_rsz0 = <&mdp_rsz0>;
mdp_rsz1 = <&svpp1_mdp_rsz>;
mdp_rsz2 = <&svpp2_mdp_rsz>;
mdp_rsz3 = <&svpp3_mdp_rsz>;
mdp_wrot0 = <&mdp_wrot0>;
mdp_wrot1 = <&svpp1_mdp_wrot>;
mdp_wrot2 = <&svpp2_mdp_wrot>;
mdp_wrot3 = <&svpp3_mdp_wrot>;
mdp_tdshp0 = <&mdp_tdshp0>;
mdp_tdshp1 = <&svpp1_mdp_tdshp>;
mdp_tdshp2 = <&svpp2_mdp_tdshp>;
mdp_tdshp3 = <&svpp3_mdp_tdshp>;
mdp_aal0 = <&mdp_aal0>;
mdp_aal1 = <&svpp1_mdp_aal>;
mdp_aal2 = <&svpp2_mdp_aal>;
mdp_aal3 = <&svpp3_mdp_aal>;
mdp_color0 = <&mdp_color0>;
mdp_color1 = <&svpp1_mdp_color>;
mdp_color2 = <&svpp2_mdp_color>;
mdp_color3 = <&svpp3_mdp_color>;
mdp_hdr0 = <&mdp_hdr0>;
mdp_hdr1 = <&svpp1_mdp_hdr>;
mdp_hdr2 = <&svpp2_mdp_hdr>;
mdp_hdr3 = <&svpp3_mdp_hdr>;
mdp_fg0 = <&mdp_fg0>;
mdp_fg1 = <&svpp1_mdp_fg>;
mdp_fg2 = <&svpp2_mdp_fg>;
mdp_fg3 = <&svpp3_mdp_fg>;
mdp_tcc0 = <&mdp_tcc0>;
mdp_tcc1 = <&svpp1_mdp_tcc>;
mdp_ovl0 = <&mdp_ovl0>;
mdp_ovl1 = <&svpp1_mdp_ovl>;
mdp_pad0 = <&mdp_pad0>;
mdp_pad1 = <&svpp1_mdp_pad>;
mdp_pad2 = <&svpp2_mdp_pad>;
mdp_pad3 = <&svpp3_mdp_pad>;
mdp_split = <&vpp_split0>;
mdp_merge2 = <&svpp2_mdp_merge>;
mdp_merge3 = <&svpp3_mdp_merge>;
/* To Do: refine after DRM enabled */
thread_count = <24>;
mediatek,mailbox-gce = <&gce_mbox>;
disp_mutex_reg = <0x14120000 0x1000>;
g3d_config_base = <0x13000000 0 0xffff0000>;
mmsys_config_base = <0x13000000 1 0xffff0000>;
disp_dither_base = <0x1c007000 2 0xffff0000>;
mm_na_base = <0x14020000 3 0xffff0000>;
imgsys_base = <0x15020000 4 0xffff0000>;
vdec_gcon_base = <0x18800000 5 0xffff0000>;
venc_gcon_base = <0x18810000 6 0xffff0000>;
conn_peri_base = <0x18820000 7 0xffff0000>;
topckgen_base = <0x18830000 8 0xffff0000>;
kp_base = <0x18840000 9 0xffff0000>;
scp_sram_base = <0x10000000 10 0xffff0000>;
infra_na3_base = <0x10010000 11 0xffff0000>;
infra_na4_base = <0x10020000 12 0xffff0000>;
scp_base = <0x10030000 13 0xffff0000>;
mcucfg_base = <0xc530000 14 0xffff0000>;
gcpu_base = <0x10050000 15 0xffff0000>;
usb0_base = <0x10200000 16 0xffff0000>;
usb_sif_base = <0x10280000 17 0xffff0000>;
audio_base = <0x17000000 18 0xffff0000>;
vdec_base = <0x17010000 19 0xffff0000>;
msdc2_base = <0x17020000 20 0xffff0000>;
vdec1_base = <0x17030000 21 0xffff0000>;
msdc3_base = <0x18000000 22 0xffff0000>;
ap_dma_base = <0x18010000 23 0xffff0000>;
gce_base = <0x10320000 24 0xffff0000>;
vdec2_base = <0x18040000 25 0xffff0000>;
vdec3_base = <0x18050000 26 0xffff0000>;
camsys_base = <0x18080000 27 0xffff0000>;
camsys1_base = <0x180a0000 28 0xffff0000>;
camsys2_base = <0x180b0000 29 0xffff0000>;
dip2_cq_thread0_frame_done = <1>;
dip2_cq_thread1_frame_done = <2>;
dip2_cq_thread2_frame_done = <3>;
dip2_cq_thread3_frame_done = <4>;
dip2_cq_thread4_frame_done = <5>;
dip2_cq_thread5_frame_done = <6>;
dip2_cq_thread6_frame_done = <7>;
dip2_cq_thread7_frame_done = <8>;
dip2_cq_thread8_frame_done = <9>;
dip2_cq_thread9_frame_done = <10>;
dip2_cq_thread10_frame_done = <11>;
dip2_cq_thread11_frame_done = <12>;
dip2_cq_thread12_frame_done = <13>;
dip2_cq_thread13_frame_done = <14>;
dip2_cq_thread14_frame_done = <15>;
dip2_cq_thread15_frame_done = <16>;
dip2_cq_thread16_frame_done = <17>;
dip2_cq_thread17_frame_done = <18>;
dip2_cq_thread18_frame_done = <19>;
dip2_cq_thread19_frame_done = <20>;
dip2_cq_thread20_frame_done = <21>;
dip2_cq_thread21_frame_done = <22>;
dip2_cq_thread23_frame_done = <24>;
dip_cq_thread0_frame_done = <33>;
dip_cq_thread1_frame_done = <34>;
dip_cq_thread2_frame_done = <35>;
dip_cq_thread3_frame_done = <36>;
dip_cq_thread4_frame_done = <37>;
dip_cq_thread5_frame_done = <38>;
dip_cq_thread6_frame_done = <39>;
dip_cq_thread7_frame_done = <40>;
dip_cq_thread8_frame_done = <41>;
dip_cq_thread9_frame_done = <42>;
dip_cq_thread10_frame_done = <43>;
dip_cq_thread11_frame_done = <44>;
dip_cq_thread12_frame_done = <45>;
dip_cq_thread13_frame_done = <46>;
dip_cq_thread14_frame_done = <47>;
dip_cq_thread15_frame_done = <48>;
dip_cq_thread16_frame_done = <49>;
dip_cq_thread17_frame_done = <50>;
dip_cq_thread18_frame_done = <51>;
dip_cq_thread19_frame_done = <52>;
dip_cq_thread20_frame_done = <53>;
dip_cq_thread21_frame_done = <54>;
dip_cq_thread23_frame_done = <56>;
ipe_event_tx_frame_done_0 = <129>;
ipe_event_tx_frame_done_1 = <130>;
rsc_frame_done = <131>;
ipe_event_tx_frame_done_3 = <132>;
ipe_event_tx_frame_done_4 = <133>;
isp_frame_done_a = <193>;
isp_frame_done_b = <194>;
isp_frame_done_c = <195>;
camsv_0_pass1_done = <196>;
camsv_0_2_pass1_done = <197>;
camsv_1_pass1_done = <198>;
camsv_2_pass1_done = <199>;
camsv_3_pass1_done = <200>;
mraw_0_pass1_done = <201>;
mraw_1_pass1_done = <202>;
seninf_0_fifo_full = <203>;
seninf_1_fifo_full = <204>;
seninf_2_fifo_full = <205>;
seninf_3_fifo_full = <206>;
seninf_4_fifo_full = <207>;
seninf_5_fifo_full = <208>;
seninf_6_fifo_full = <209>;
seninf_7_fifo_full = <210>;
seninf_cam8_fifo_full = <211>;
seninf_cam9_fifo_full = <212>;
seninf_cam10_fifo_full = <213>;
seninf_cam11_fifo_full = <214>;
seninf_cam12_fifo_full = <215>;
tg_ovrun_a_int_dly = <216>;
tg_graberr_a_int_dly = <217>;
tg_ovrun_b_int_dly = <218>;
tg_graberr_b_int_dly = <219>;
tg_ovrun_c_int = <220>;
tg_graberr_c_int = <221>;
tg_ovrun_m0_int = <222>;
dma_r1_error_m0_int = <223>;
/* sof */
mdp_rdma0_sof = <256>;
mdp_fg0_sof = <257>;
mdp_hdr0_sof = <259>;
mdp_aal0_sof = <260>;
mdp_tdshp0_sof = <262>;
mdp_color0_sof = <263>;
mdp_pad0_sof = <265>;
mdp_rsz0_sof = <268>;
mdp_wrot0_sof = <267>;
mdp_tcc0_sof = <280>;
/* frame done */
mdp_rdma0_frame_done = <288>;
mdp_fg0_frame_done = <289>;
mdp_stitch0_frame_done = <290>;
mdp_hdr0_frame_done = <291>;
mdp_aal0_frame_done = <292>;
mdp_rsz0_frame_done = <293>;
mdp_tdshp0_frame_done = <294>;
mdp_color0_frame_done = <295>;
mdp_tcc0_frame_done = <298>;
mdp_wrot0_write_frame_done = <299>;
/* rst done */
mdp_rdma0_rst_done = <352>;
mdp_wrot0_rst_done = <355>;
/* sof */
mdp_hdmi_meta_sof = <384>;
mdp_dgi_sof = <385>;
mdp_split_sof = <386>;
mdp_tcc1_sof = <387>;
mdp_rdma1_sof = <388>;
mdp_rdma2_sof = <389>;
mdp_rdma3_sof = <390>;
mdp_fg1_sof = <391>;
mdp_fg2_sof = <392>;
mdp_fg3_sof = <393>;
mdp_hdr1_sof = <394>;
mdp_hdr2_sof = <395>;
mdp_hdr3_sof = <396>;
mdp_aal1_sof = <397>;
mdp_aal2_sof = <398>;
mdp_aal3_sof = <399>;
mdp_rsz1_sof = <400>;
mdp_rsz2_sof = <401>;
mdp_rsz3_sof = <402>;
mdp_tdshp1_sof = <403>;
mdp_tdshp2_sof = <404>;
mdp_tdshp3_sof = <405>;
mdp_merge2_sof = <406>;
mdp_merge3_sof = <407>;
mdp_color1_sof = <408>;
mdp_color2_sof = <409>;
mdp_color3_sof = <410>;
mdp_ovl1_sof = <411>;
mdp_pad1_sof = <412>;
mdp_pad2_sof = <413>;
mdp_pad3_sof = <414>;
mdp_wrot1_sof = <415>;
mdp_wrot2_sof = <416>;
mdp_wrot3_sof = <417>;
img_dl_irly_sof = <418>;
img_dl_orly_sof = <419>;
img_dl_relay0_sof = <420>;
img_dl_relay1_sof = <421>;
img_dl_relay2_sof = <422>;
img_dl_relay3_sof = <423>;
/* frame done */
mdp_rdma1_frame_done = <424>;
mdp_rdma2_frame_done = <425>;
mdp_rdma3_frame_done = <426>;
mdp_wrot1_write_frame_done = <427>;
mdp_wrot2_write_frame_done = <428>;
mdp_wrot3_write_frame_done = <429>;
mdp_ovl1_frame_done = <430>;
mdp_rsz1_frame_done = <431>;
mdp_rsz2_frame_done = <432>;
mdp_rsz3_frame_done = <433>;
wpe_a_frame_done = <962>;
wpe_b_frame_done = <969>;
};
mdp_fg0: mdp_fg0@14002000 {
compatible = "mediatek,mdp_fg0";
reg = <0 0x14002000 0 0x1000>;
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
clock-names = "MDP_FG0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_stich0: mdp_stich0@14003000 {
compatible = "mediatek,mdp_stich0";
reg = <0 0x14003000 0 0x1000>;
interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_STITCH>;
clock-names = "MDP_STITCH";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_hdr0: mdp_hdr0@14004000 {
compatible = "mediatek,mdp_hdr0";
reg = <0 0x14004000 0 0x1000>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
clock-names = "MDP_HDR0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_aal0: mdp_aal0@14005000 {
compatible = "mediatek,mdp_aal0";
reg = <0 0x14005000 0 0x1000>;
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
clock-names = "MDP_AAL0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_rsz0: mdp_rsz0@14006000 {
compatible = "mediatek,mdp_rsz0";
reg = <0 0x14006000 0 0x1000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
clock-names = "MDP_RSZ0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_tdshp0: mdp_tdshp0@14007000 {
compatible = "mediatek,mdp_tdshp0";
reg = <0 0x14007000 0 0x1000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
clock-names = "MDP_TDSHP0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_color0: mdp_color0@14008000 {
compatible = "mediatek,mdp_color0";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
clock-names = "MDP_COLOR0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_ovl0: mdp_ovl0@14009000 {
compatible = "mediatek,mdp_ovl0";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
clock-names = "MDP_OVL0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_pad0: mdp_pad0@1400a000 {
compatible = "mediatek,mdp_pad0";
reg = <0 0x1400a000 0 0x1000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_PADDING>;
clock-names = "MDP_PAD0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_tcc0: mdp_tcc0@1400b000 {
compatible = "mediatek,mdp_tcc0";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
clock-names = "MDP_TCC0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mdp_wrot0: mdp_wrot0@1400c000 {
compatible = "mediatek,mdp_wrot0";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
clock-names = "MDP_WROT0";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
mmsram: mmsram@1400d000 {
compatible = "mediatek,mmsram";
reg = <0 0x1400d000 0 0x1000>,
<0 0x1e000000 0 0x260000>;
interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MMSYSRAM_TOP>;
clock-names = "MMSYSRAM_TOP";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
smi_common2: smi@1400e000 {
compatible = "mediatek,mt8195-smi-common";
mediatek,common-id = <2>;
reg = <0 0x1400e000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_SMI_COMMON>,
<&vppsys0 CLK_VPP0_SMI_COMMON>,
<&vppsys0 CLK_VPP0_GALS_INFRA>,
<&vppsys0 CLK_VPP0_GALS_CAMSYS>,
<&vppsys0 CLK_VPP0_SMI_REORDER>;
clock-names = "apb", "smi", "gals0", "gals1", "gals2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
smi_common1: smi@14012000 {
compatible = "mediatek,mt8195-smi-common";
mediatek,common-id = <1>;
reg = <0 0x14012000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
<&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
<&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
<&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>;
clock-names = "apb", "smi", "gals0", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
larb4: larb@14013000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x14013000 0 0x1000>;
mediatek,larb-id = <4>;
mediatek,smi = <&smi_common1>;
clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
<&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
clock-names = "apb", "smi";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
iommu1: mm-iommu@14018000 {
compatible = "mediatek,mt8195-iommu-vpp";
reg = <0 0x14018000 0 0x1000>;
mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
&larb12 &larb14 &larb16 &larb18
&larb20 &larb22 &larb23 &larb26
&larb27>;
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>,
<&vppsys0 CLK_VPP0_SMI_RSI>;
clock-names = "bclk", "rsi";
#iommu-cells = <1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
sec_iommu1: vpp_sec_iommu {
compatible = "mediatek,secure_m4u";
main-bank = <&iommu1>;
iommus = <&iommu1 M4U_PORT_L1_DISP_FAKE0>;
};
wpesys: syscon@14e00000 {
compatible = "mediatek,mt8195-wpesys", "syscon";
reg = <0 0x14e00000 0 0x1000>;
#clock-cells = <1>;
};
wpesys_vpp0: syscon@14e02000 {
compatible = "mediatek,mt8195-wpesys_vpp0", "syscon";
reg = <0 0x14e02000 0 0x1000>;
#clock-cells = <1>;
};
wpe_a: wpe@14e02000 {
compatible = "mediatek,mt8195-wpe", "mediatek,wpe";
reg = <0 0x14e02000 0 0x1000>;
mediatek,larb-id = <7>;
mediatek,larb = <&larb7 &larb8>;
iommus = <&iommu0 M4U_PORT_L7_IMG_WPE_RDMA0>,
<&iommu0 M4U_PORT_L7_IMG_WPE_RDMA1>,
<&iommu0 M4U_PORT_L7_IMG_WPE_WDMA0>;
clocks = <&wpesys CLK_WPE_VPP0>,
<&wpesys CLK_WPE_EVENT_TX>,
<&wpesys_vpp0 CLK_WPE_VPP0_VECI>,
<&wpesys_vpp0 CLK_WPE_VPP0_VEC2I>,
<&wpesys_vpp0 CLK_WPE_VPP0_VEC3I>,
<&wpesys_vpp0 CLK_WPE_VPP0_WPEO>,
<&wpesys_vpp0 CLK_WPE_VPP0_MSKO>,
<&wpesys_vpp0 CLK_WPE_VPP0_VGEN>,
<&wpesys_vpp0 CLK_WPE_VPP0_EXT>,
<&wpesys_vpp0 CLK_WPE_VPP0_VFC>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH0_TOP>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH0_DMA>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH1_TOP>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH1_DMA>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH2_TOP>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH2_DMA>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH3_TOP>,
<&wpesys_vpp0 CLK_WPE_VPP0_CACH3_DMA>,
<&wpesys_vpp0 CLK_WPE_VPP0_PSP>,
<&wpesys_vpp0 CLK_WPE_VPP0_PSP2>,
<&wpesys_vpp0 CLK_WPE_VPP0_SYNC>,
<&wpesys_vpp0 CLK_WPE_VPP0_C24>,
<&wpesys_vpp0 CLK_WPE_VPP0_MDP_CROP>,
<&wpesys_vpp0 CLK_WPE_VPP0_ISP_CROP>,
<&wpesys_vpp0 CLK_WPE_VPP0_TOP>;
power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
operating-points-v2 = <&opp_table_warp>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_IMG_WPE_RDMA0) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_IMG_WPE_RDMA1) &mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L7_IMG_WPE_WDMA0) &mmqos SLAVE_COMMON(0)>;
interconnect-names = "vppwpe_rdma0", "vppwpe_rdma1", "vppwpe_wdma";
};
wpesys_vpp1: syscon@14e03000 {
compatible = "mediatek,mt8195-wpesys_vpp1", "syscon";
reg = <0 0x14e03000 0 0x1000>;
#clock-cells = <1>;
};
wpe_b: wpe@14e03000 {
compatible = "mediatek,mt8195-wpe", "mediatek,wpe";
reg = <0 0x14e03000 0 0x1000>;
mediatek,larb-id = <8>;
mediatek,larb = <&larb7 &larb8>;
iommus = <&iommu1 M4U_PORT_L8_IMG_WPE_RDMA0>,
<&iommu1 M4U_PORT_L8_IMG_WPE_RDMA1>,
<&iommu1 M4U_PORT_L8_IMG_WPE_WDMA0>;
clocks = <&wpesys CLK_WPE_VPP1>,
<&wpesys_vpp1 CLK_WPE_VPP1_VECI>,
<&wpesys_vpp1 CLK_WPE_VPP1_VEC2I>,
<&wpesys_vpp1 CLK_WPE_VPP1_VEC3I>,
<&wpesys_vpp1 CLK_WPE_VPP1_WPEO>,
<&wpesys_vpp1 CLK_WPE_VPP1_MSKO>,
<&wpesys_vpp1 CLK_WPE_VPP1_VGEN>,
<&wpesys_vpp1 CLK_WPE_VPP1_EXT>,
<&wpesys_vpp1 CLK_WPE_VPP1_VFC>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH0_TOP>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH0_DMA>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH1_TOP>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH1_DMA>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH2_TOP>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH2_DMA>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH3_TOP>,
<&wpesys_vpp1 CLK_WPE_VPP1_CACH3_DMA>,
<&wpesys_vpp1 CLK_WPE_VPP1_PSP>,
<&wpesys_vpp1 CLK_WPE_VPP1_PSP2>,
<&wpesys_vpp1 CLK_WPE_VPP1_SYNC>,
<&wpesys_vpp1 CLK_WPE_VPP1_C24>,
<&wpesys_vpp1 CLK_WPE_VPP1_MDP_CROP>,
<&wpesys_vpp1 CLK_WPE_VPP1_ISP_CROP>,
<&wpesys_vpp1 CLK_WPE_VPP1_TOP>;
power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L8_IMG_WPE_RDMA0) &mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L8_IMG_WPE_RDMA1) &mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L8_IMG_WPE_WDMA0) &mmqos SLAVE_COMMON(1)>;
interconnect-names = "vppwpe_rdma0", "vppwpe_rdma1", "vppwpe_wdma";
};
larb7: larb@14e04000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x14e04000 0 0x1000>;
mediatek,larb-id = <7>;
mediatek,smi = <&smi_common0>;
clocks = <&wpesys CLK_WPE_SMI_LARB7>,
<&wpesys CLK_WPE_SMI_LARB7>;
clock-names = "apb", "smi";
power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
};
larb8: larb@14e05000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x14e05000 0 0x1000>;
mediatek,larb-id = <8>;
mediatek,smi = <&smi_common1>;
clocks = <&wpesys CLK_WPE_SMI_LARB8>,
<&wpesys CLK_WPE_SMI_LARB8>,
<&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
};
vppsys1: syscon@14f00000 {
compatible = "mediatek,mt8195-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
};
vpp1_mutex: vpp1_mutex@14f01000 {
compatible = "mediatek,vpp1_mutex";
reg = <0 0x14f01000 0 0x1000>;
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
clock-names = "DISP_MUTEX";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
larb5: larb@14f02000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x14f02000 0 0x1000>;
mediatek,larb-id = <5>;
mediatek,smi = <&smi_common0 &smi_common2>;
clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
<&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
<&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
larb6: larb@14f03000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x14f03000 0 0x1000>;
mediatek,larb-id = <6>;
mediatek,smi = <&smi_common1 &smi_common2>;
clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
<&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
<&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
vpp_split0: vpp_split0@14f06000 {
compatible = "mediatek,vpp_split0";
reg = <0 0x14f06000 0 0x1000>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>;
clock-names = "MDP_SPLIT";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_tcc: svpp1_mdp_tcc@14f07000 {
compatible = "mediatek,svpp1_mdp_tcc";
reg = <0 0x14f07000 0 0x1000>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
clock-names = "MDP_TCC1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_rdma: svpp1_mdp_rdma@14f08000 {
compatible = "mediatek,svpp1_mdp_rdma";
reg = <0 0x14f08000 0 0x1000>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
clock-names = "MDP_RDMA1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_rdma: svpp2_mdp_rdma@14f09000 {
compatible = "mediatek,svpp2_mdp_rdma";
reg = <0 0x14f09000 0 0x1000>;
interrupts = <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
clock-names = "MDP_RDMA2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_rdma: svpp3_mdp_rdma@14f0a000 {
compatible = "mediatek,svpp3_mdp_rdma";
reg = <0 0x14f0a000 0 0x1000>;
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
clock-names = "MDP_RDMA3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_fg: svpp1_mdp_fg@14f0b000 {
compatible = "mediatek,svpp1_mdp_fg";
reg = <0 0x14f0b000 0 0x1000>;
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
clock-names = "MDP_FG1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_fg: svpp2_mdp_fg@14f0c000 {
compatible = "mediatek,svpp2_mdp_fg";
reg = <0 0x14f0c000 0 0x1000>;
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
clock-names = "MDP_FG2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_fg: svpp3_mdp_fg@14f0c000 {
compatible = "mediatek,svpp3_mdp_fg";
reg = <0 0x14f0d000 0 0x1000>;
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
clock-names = "MDP_FG3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_hdr: svpp1_mdp_hdr@14f0e000 {
compatible = "mediatek,svpp1_mdp_hdr";
reg = <0 0x14f0e000 0 0x1000>;
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
clock-names = "MDP_HDR1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_hdr: svpp2_mdp_hdr@14f0f000 {
compatible = "mediatek,svpp2_mdp_hdr";
reg = <0 0x14f0f000 0 0x1000>;
interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
clock-names = "MDP_HDR2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_hdr: svpp3_mdp_hdr@14f10000 {
compatible = "mediatek,svpp3_mdp_hdr";
reg = <0 0x14f10000 0 0x1000>;
interrupts = <GIC_SPI 616 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
clock-names = "MDP_HDR3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_aal: svpp1_mdp_aal@14f11000 {
compatible = "mediatek,svpp1_mdp_aal";
reg = <0 0x14f11000 0 0x1000>;
interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
clock-names = "MDP_AAL1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_aal: svpp2_mdp_aal@14f12000 {
compatible = "mediatek,svpp2_mdp_aal";
reg = <0 0x14f12000 0 0x1000>;
interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
clock-names = "MDP_AAL2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_aal: svpp3_mdp_aal@14f13000 {
compatible = "mediatek,svpp3_mdp_aal";
reg = <0 0x14f13000 0 0x1000>;
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
clock-names = "MDP_AAL3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_rsz: svpp1_mdp_rsz@14f14000 {
compatible = "mediatek,svpp1_mdp_rsz";
reg = <0 0x14f14000 0 0x1000>;
interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
clock-names = "MDP_RSZ1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_rsz: svpp2_mdp_rsz@14f15000 {
compatible = "mediatek,svpp2_mdp_rsz";
reg = <0 0x14f15000 0 0x1000>;
interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
clock-names = "MDP_RSZ2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_rsz: svpp3_mdp_rsz@14f16000 {
compatible = "mediatek,svpp3_mdp_rsz";
reg = <0 0x14f16000 0 0x1000>;
interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
clock-names = "MDP_RSZ3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_tdshp: svpp1_mdp_tdshp@14f17000 {
compatible = "mediatek,svpp1_mdp_tdshp";
reg = <0 0x14f17000 0 0x1000>;
interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
clock-names = "MDP_TDSHP1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_tdshp: svpp2_mdp_tdshp@14f18000 {
compatible = "mediatek,svpp2_mdp_tdshp";
reg = <0 0x14f18000 0 0x1000>;
interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
clock-names = "MDP_TDSHP2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_tdshp: svpp3_mdp_tdshp@14f19000 {
compatible = "mediatek,svpp3_mdp_tdshp";
reg = <0 0x14f19000 0 0x1000>;
interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
clock-names = "MDP_TDSHP3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_merge: svpp2_mdp_merge@14f1a000 {
compatible = "mediatek,svpp2_mdp_merge";
reg = <0 0x14f1a000 0 0x1000>;
interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
clock-names = "MDP_MERGE2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_merge: svpp3_mdp_merge@14f1b000 {
compatible = "mediatek,svpp3_mdp_merge";
reg = <0 0x14f1b000 0 0x1000>;
interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
clock-names = "MDP_MERGE3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_color: svpp1_mdp_color@14f1c000 {
compatible = "mediatek,svpp1_mdp_color";
reg = <0 0x14f1c000 0 0x1000>;
interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
clock-names = "MDP_COLOR1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_color: svpp2_mdp_color@14f1d000 {
compatible = "mediatek,svpp2_mdp_color";
reg = <0 0x14f1d000 0 0x1000>;
interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
clock-names = "MDP_COLOR2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_color: svpp3_mdp_color@14f1e000 {
compatible = "mediatek,svpp3_mdp_color";
reg = <0 0x14f1e000 0 0x1000>;
interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
clock-names = "MDP_COLOR3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_ovl: svpp1_mdp_ovl@14f1f000 {
compatible = "mediatek,svpp1_mdp_ovl";
reg = <0 0x14f1f000 0 0x1000>;
interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
clock-names = "MDP_OVL1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_pad: svpp1_mdp_pad@14f20000 {
compatible = "mediatek,svpp1_mdp_pad";
reg = <0 0x14f20000 0 0x1000>;
interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
clock-names = "MDP_PAD1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_pad: svpp2_mdp_pad@14f21000 {
compatible = "mediatek,svpp2_mdp_pad";
reg = <0 0x14f21000 0 0x1000>;
interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
clock-names = "MDP_PAD2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_pad: svpp3_mdp_pad@14f22000 {
compatible = "mediatek,svpp3_mdp_pad";
reg = <0 0x14f22000 0 0x1000>;
interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
clock-names = "MDP_PAD3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp1_mdp_wrot: svpp1_mdp_wrot@14f23000 {
compatible = "mediatek,svpp1_mdp_wrot";
reg = <0 0x14f23000 0 0x1000>;
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
/* iommus = <&iommu0 M4U_PORT_L5_SVPP1_MDP_WROT>; */
clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
clock-names = "MDP_WROT1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp2_mdp_wrot: svpp2_mdp_wrot@14f24000 {
compatible = "mediatek,svpp2_mdp_wrot";
reg = <0 0x14f24000 0 0x1000>;
interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
/* iommus = <&iommu0 M4U_PORT_L5_SVPP2_MDP_WROT>; */
clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
clock-names = "MDP_WROT2";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
svpp3_mdp_wrot: svpp3_mdp_wrot@14f25000 {
compatible = "mediatek,svpp3_mdp_wrot";
reg = <0 0x14f25000 0 0x1000>;
interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>;
/* iommus = <&iommu1 M4U_PORT_L6_SVPP3_MDP_WROT>; */
clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
clock-names = "MDP_WROT3";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
imgsys: syscon@15000000 {
compatible = "mediatek,mt8195-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
imgsys_fw: imgsys_fw@15000000 {
compatible = "mediatek,imgsys";
ion-supply = <&ion>;
reg = <0 0x15000000 0 0x4000>, /* 0 IMGSYS_TOP */
<0 0x15020000 0 0x10000>, /* 1 IMGSYS_TRAW */
<0 0x15040000 0 0x10000>, /* 2 IMGSYS_LTRAW */
<0 0x15100000 0 0x10000>, /* 3 IMGSYS_DIP */
<0 0x15140000 0 0x10000>, /* 4 IMGSYS_PQDIP_A */
<0 0x15150000 0 0x10000>, /* 5 IMGSYS_PQDIP_B */
<0 0x15200000 0 0x10000>, /* 6 IMGSYS_WPE_EIS */
<0 0x15210000 0 0x10000>, /* 7 IMGSYS_WPE_TNR */
<0 0x15220000 0 0x00100>, /* 8 IMGSYS_WPE_DIP1 */
<0 0x15320000 0 0x10000>; /* 9 IMGSYS_ME */
mediatek,hcp = <&hcp>;
mediatek,larb = <&larb9 &larb10 &larb11>;
iommus = <&iommu0 M4U_PORT_L9_IMG_IMGI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_IMGBI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_IMGCI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TNCSTI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TNCSTI_T4_A>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TIMGO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T2_A>,
<&iommu0 M4U_PORT_L9_IMG_IMGI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_IMGBI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_IMGCI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T5_A>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_TNCSO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TNCSTO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T2_B>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T5_B>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_T1_B>,
<&iommu0 M4U_PORT_L10_IMG_IMGI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMGCI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_DEPI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_DMGI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_VIPI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_TNRWI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_RECI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_SMTI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_SMTI_D6_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGI_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGBI_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGCI_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGI_P1_B>,
<&iommu0 M4U_PORT_L10_IMG_PIMGBI_P1_B>,
<&iommu0 M4U_PORT_L10_IMG_PIMGCI_P1_B>,
<&iommu0 M4U_PORT_L10_IMG_IMG3O_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMG4O_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMG3CO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_FEO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMG2O_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_TNRWO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_SMTO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_WROT_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_WROT_P1_B>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_CQ0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_CQ1_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_CQ0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_CQ1_A>;
mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 1 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 2 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 3 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 4 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 5 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 6 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 7 0 CMDQ_THR_PRIO_1>;
traw_cq_thread0_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_0>;
traw_cq_thread1_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_1>;
traw_cq_thread2_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_2>;
traw_cq_thread3_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_3>;
traw_cq_thread4_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_4>;
traw_cq_thread5_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_5>;
traw_cq_thread6_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_6>;
traw_cq_thread7_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_7>;
traw_cq_thread8_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_8>;
traw_cq_thread9_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_9>;
traw_cq_thread10_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_10>;
traw_cq_thread11_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_11>;
traw_cq_thread12_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_12>;
traw_cq_thread13_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_13>;
traw_cq_thread14_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW0_14>;
ltraw_cq_thread0_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_0>;
ltraw_cq_thread1_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_1>;
ltraw_cq_thread2_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_2>;
ltraw_cq_thread3_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_3>;
ltraw_cq_thread4_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_4>;
ltraw_cq_thread5_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_5>;
ltraw_cq_thread6_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_6>;
ltraw_cq_thread7_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_7>;
ltraw_cq_thread8_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_8>;
ltraw_cq_thread9_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_9>;
ltraw_cq_thread10_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_10>;
ltraw_cq_thread11_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_11>;
ltraw_cq_thread12_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_12>;
ltraw_cq_thread13_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_13>;
ltraw_cq_thread14_frame_done =
/bits/ 16 <CMDQ_EVENT_CQ_THR_DONE_TRAW1_14>;
dip_cq_thread0_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_0>;
dip_cq_thread1_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_1>;
dip_cq_thread2_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_2>;
dip_cq_thread3_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_3>;
dip_cq_thread4_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_4>;
dip_cq_thread5_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_5>;
dip_cq_thread6_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_6>;
dip_cq_thread7_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_7>;
dip_cq_thread8_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_8>;
dip_cq_thread9_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_9>;
dip_cq_thread10_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_10>;
dip_cq_thread11_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_11>;
dip_cq_thread12_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_12>;
dip_cq_thread13_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_13>;
dip_cq_thread14_frame_done =
/bits/ 16 <CMDQ_EVENT_DIP0_FRAME_DONE_P2_14>;
pqa_cq_thread0_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_0>;
pqa_cq_thread1_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_1>;
pqa_cq_thread2_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_2>;
pqa_cq_thread3_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_3>;
pqa_cq_thread4_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_4>;
pqa_cq_thread5_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_5>;
pqa_cq_thread6_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_6>;
pqa_cq_thread7_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_7>;
pqa_cq_thread8_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_8>;
pqa_cq_thread9_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_9>;
pqa_cq_thread10_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_10>;
pqa_cq_thread11_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_11>;
pqa_cq_thread12_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_12>;
pqa_cq_thread13_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_13>;
pqa_cq_thread14_frame_done =
/bits/ 16 <CMDQ_EVENT_PQA0_FRAME_DONE_P2_14>;
pqb_cq_thread0_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_0>;
pqb_cq_thread1_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_1>;
pqb_cq_thread2_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_2>;
pqb_cq_thread3_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_3>;
pqb_cq_thread4_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_4>;
pqb_cq_thread5_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_5>;
pqb_cq_thread6_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_6>;
pqb_cq_thread7_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_7>;
pqb_cq_thread8_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_8>;
pqb_cq_thread9_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_9>;
pqb_cq_thread10_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_10>;
pqb_cq_thread11_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_11>;
pqb_cq_thread12_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_12>;
pqb_cq_thread13_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_13>;
pqb_cq_thread14_frame_done =
/bits/ 16 <CMDQ_EVENT_PQB0_FRAME_DONE_P2_14>;
wpe_eis_cq_thread0_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_0>;
wpe_eis_cq_thread1_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_1>;
wpe_eis_cq_thread2_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_2>;
wpe_eis_cq_thread3_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_3>;
wpe_eis_cq_thread4_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_4>;
wpe_eis_cq_thread5_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_5>;
wpe_eis_cq_thread6_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_6>;
wpe_eis_cq_thread7_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_7>;
wpe_eis_cq_thread8_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_8>;
wpe_eis_cq_thread9_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_9>;
wpe_eis_cq_thread10_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_10>;
wpe_eis_cq_thread11_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_11>;
wpe_eis_cq_thread12_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_12>;
wpe_eis_cq_thread13_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_13>;
wpe_eis_cq_thread14_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_14>;
wpe_tnr_cq_thread0_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_0>;
wpe_tnr_cq_thread1_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_1>;
wpe_tnr_cq_thread2_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_2>;
wpe_tnr_cq_thread3_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_3>;
wpe_tnr_cq_thread4_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_4>;
wpe_tnr_cq_thread5_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_5>;
wpe_tnr_cq_thread6_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_6>;
wpe_tnr_cq_thread7_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_7>;
wpe_tnr_cq_thread8_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_8>;
wpe_tnr_cq_thread9_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_9>;
wpe_tnr_cq_thread10_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_10>;
wpe_tnr_cq_thread11_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_11>;
wpe_tnr_cq_thread12_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_12>;
wpe_tnr_cq_thread13_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_13>;
wpe_tnr_cq_thread14_frame_done =
/bits/ 16 <CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_14>;
me_done =
/bits/ 16 <CMDQ_EVENT_IMGSYS_IPE_ME_DONE>;
wpe_eis_sync_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS>;
wpe_tnr_sync_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR>;
traw_sync_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_TRAW>;
ltraw_sync_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_LTRAW>;
dip_sync_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_DIP>;
pqdip_a_sync_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A>;
pqdip_b_sync_token =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B>;
sw_sync_token_pool_1 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_1>;
sw_sync_token_pool_2 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_2>;
sw_sync_token_pool_3 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_3>;
sw_sync_token_pool_4 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_4>;
sw_sync_token_pool_5 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_5>;
sw_sync_token_pool_6 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_6>;
sw_sync_token_pool_7 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_7>;
sw_sync_token_pool_8 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_8>;
sw_sync_token_pool_9 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_9>;
sw_sync_token_pool_10 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_10>;
sw_sync_token_pool_11 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_11>;
sw_sync_token_pool_12 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_12>;
sw_sync_token_pool_13 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_13>;
sw_sync_token_pool_14 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_14>;
sw_sync_token_pool_15 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_15>;
sw_sync_token_pool_16 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_16>;
sw_sync_token_pool_17 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_17>;
sw_sync_token_pool_18 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_18>;
sw_sync_token_pool_19 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_19>;
sw_sync_token_pool_20 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_20>;
sw_sync_token_pool_21 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_21>;
sw_sync_token_pool_22 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_22>;
sw_sync_token_pool_23 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_23>;
sw_sync_token_pool_24 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_24>;
sw_sync_token_pool_25 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_25>;
sw_sync_token_pool_26 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_26>;
sw_sync_token_pool_27 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_27>;
sw_sync_token_pool_28 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_28>;
sw_sync_token_pool_29 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_29>;
sw_sync_token_pool_30 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_30>;
sw_sync_token_pool_31 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_31>;
sw_sync_token_pool_32 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_32>;
sw_sync_token_pool_33 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_33>;
sw_sync_token_pool_34 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_34>;
sw_sync_token_pool_35 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_35>;
sw_sync_token_pool_36 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_36>;
sw_sync_token_pool_37 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_37>;
sw_sync_token_pool_38 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_38>;
sw_sync_token_pool_39 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_39>;
sw_sync_token_pool_40 =
/bits/ 16 <CMDQ_SYNC_TOKEN_IMGSYS_POOL_40>;
sw_sync_token_camsys_pool_1 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_1>;
sw_sync_token_camsys_pool_2 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_2>;
sw_sync_token_camsys_pool_3 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_3>;
sw_sync_token_camsys_pool_4 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_4>;
sw_sync_token_camsys_pool_5 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_5>;
sw_sync_token_camsys_pool_6 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_6>;
sw_sync_token_camsys_pool_7 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_7>;
sw_sync_token_camsys_pool_8 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_8>;
sw_sync_token_camsys_pool_9 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_9>;
sw_sync_token_camsys_pool_10 =
/bits/ 16 <CMDQ_SYNC_TOKEN_CAMSYS_POOL_10>;
clocks = <&imgsys CLK_IMG_TRAW0>,
<&imgsys CLK_IMG_TRAW1>,
<&imgsys CLK_IMG_TRAW2>,
<&imgsys CLK_IMG_TRAW3>,
<&imgsys CLK_IMG_DIP0>,
<&imgsys CLK_IMG_WPE0>,
<&imgsys CLK_IMG_DIP1>,
<&imgsys CLK_IMG_WPE1>,
<&imgsys1_dip_top CLK_IMG1_DIP_TOP_DIP_TOP>,
<&imgsys1_dip_nr CLK_IMG1_DIP_NR_DIP_NR>,
<&imgsys1_wpe CLK_IMG1_WPE_WPE>;
clock-names = "IMGSYS_CG_IMG_TRAW0",
"IMGSYS_CG_IMG_TRAW1",
"IMGSYS_CG_IMG_TRAW2",
"IMGSYS_CG_IMG_TRAW3",
"IMGSYS_CG_IMG_DIP0",
"IMGSYS_CG_IMG_WPE0",
"IMGSYS_CG_IMG_DIP1",
"IMGSYS_CG_IMG_WPE1",
"DIP_CG_IMG_DIP",
"DIP_NR_DIP_NR",
"WPE_CG_WPE_WPE";
operating-points-v2 = <&opp_table_img>, <&opp_table_ipe>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGI_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGBI_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGCI_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTI_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_TNCSTI_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_TNCSTI_T4_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_YUVO_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_TIMGO_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_YUVO_T2_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGI_T1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGBI_T1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_IMGCI_T1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_YUVO_T5_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTI_T1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_TNCSO_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTO_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_TNCSTO_T1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_YUVO_T2_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_YUVO_T5_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG_SMTO_T1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_IMGI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_IMGCI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_DEPI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_DMGI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_VIPI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_TNRWI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_RECI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_SMTI_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_SMTI_D6_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_PIMGI_P1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_PIMGBI_P1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_PIMGCI_P1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_PIMGI_P1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_PIMGBI_P1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_PIMGCI_P1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_IMG3O_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_IMG4O_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_IMG3CO_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_FEO_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_IMG2O_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_TNRWO_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_SMTO_D1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_WROT_P1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L10_IMG_WROT_P1_B)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_EIS_CQ0_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_EIS_CQ1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_TNR_CQ0_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L11_IMG_WPE_TNR_CQ1_A)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L12_IMG_ME_RDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L12_IMG_ME_WDMA)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"l9_imgi_t1_a",
"l9_imgbi_t1_a",
"l9_imgci_t1_a",
"l9_smti_t1_a",
"l9_tncsti_t1_a",
"l9_tncsti_t4_a",
"l9_yuvo_t1_a",
"l9_timgo_t1_a",
"l9_yuvo_t2_a",
"l9_imgi_t1_b",
"l9_imgbi_t1_b",
"l9_imgci_t1_b",
"l9_yuvo_t5_a",
"l9_smti_t1_b",
"l9_tncso_t1_a",
"l9_smto_t1_a",
"l9_tncsto_t1_a",
"l9_yuvo_t2_b",
"l9_yuvo_t5_b",
"l9_smto_t1_b",
"l10_imgi_d1_a",
"l10_imgci_d1_a",
"l10_depi_d1_a",
"l10_dmgi_d1_a",
"l10_vipi_d1_a",
"l10_tnrwi_d1_a",
"l10_reci_d1_a",
"l10_smti_d1_a",
"l10_smti_d6_a",
"l10_pimgi_p1_a",
"l10_pimgbi_p1_a",
"l10_pimgci_p1_a",
"l10_pimgi_p1_b",
"l10_pimgbi_p1_b",
"l10_pimgci_p1_b",
"l10_img3o_d1_a",
"l10_img4o_d1_a",
"l10_img3co_d1_a",
"l10_feo_d1_a",
"l10_img2o_d1_a",
"l10_tnrwo_d1_a",
"l10_smto_d1_a",
"l10_wrot_p1_a",
"l10_wrot_p1_b",
"l11_wpe_eis_rdma0_a",
"l11_wpe_eis_rdma1_a",
"l11_wpe_eis_wdma0_a",
"l11_wpe_tnr_rdma0_a",
"l11_wpe_tnr_rdma1_a",
"l11_wpe_tnr_wdma0_a",
"l11_wpe_eis_cq0_a",
"l11_wpe_eis_cq1_a",
"l11_wpe_tnr_cq0_a",
"l11_wpe_tnr_cq1_a",
"l12_me_rdma",
"l12_me_wdma";
};
larb9: larb@15001000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,larb-id = <9>;
mediatek,smi = <&smi_common0>;
clocks = <&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_GALS>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
};
imgsys1_dip_top: syscon@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top", "syscon";
reg = <0 0x15110000 0 0x1000>;
#clock-cells = <1>;
};
larb10: larb@15120000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x15120000 0 0x1000>;
mediatek,larb-id = <10>;
mediatek,smi = <&smi_common0>;
clocks = <&imgsys CLK_IMG_DIP0>,
<&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>,
<&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_GALS>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
};
imgsys1_dip_nr: syscon@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr", "syscon";
reg = <0 0x15130000 0 0x1000>;
#clock-cells = <1>;
};
imgsys1_wpe: syscon@15220000 {
compatible = "mediatek,mt8195-imgsys1_wpe", "syscon";
reg = <0 0x15220000 0 0x1000>;
#clock-cells = <1>;
};
larb11: larb@15230000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x15230000 0 0x1000>;
mediatek,larb-id = <11>;
mediatek,smi = <&smi_common0>;
clocks = <&imgsys CLK_IMG_WPE0>,
<&imgsys1_wpe CLK_IMG1_WPE_LARB11>,
<&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_GALS>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
};
aie: aie@15310000 {
compatible = "mediatek,mt8195-aie", "mediatek,aie-hw3.0";
reg = <0 0x15310000 0 0x1000>;
interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,larb = <&larb12>;
iommus = <&iommu1 M4U_PORT_L12_IMG_FDVT_RDA>,
<&iommu1 M4U_PORT_L12_IMG_FDVT_RDB>,
<&iommu1 M4U_PORT_L12_IMG_FDVT_WRA>,
<&iommu1 M4U_PORT_L12_IMG_FDVT_WRB>;
power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
clocks = <&imgsys CLK_IMG_IPE>,
<&ipesys CLK_IPE_FDVT>,
<&ipesys CLK_IPE_SMI_LARB12>,
<&ipesys CLK_IPE_TOP>;
clock-names = "IMG_IPE",
"IPE_FDVT",
"IPE_SMI_LARB12",
"IPE_TOP";
operating-points-v2 = <&opp_table_ipe>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L12_IMG_FDVT_RDA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L12_IMG_FDVT_RDB)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L12_IMG_FDVT_WRA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L12_IMG_FDVT_WRB)
&mmqos SLAVE_COMMON(1)>;
interconnect-names = "l12_fdvt_rda",
"l12_fdvt_rdb",
"l12_fdvt_wra",
"l12_fdvt_wrb";
};
ipesys_me: ipesys_me@15320000 {
compatible = "mediatek,ipesys-me";
reg = <0 0x15320000 0 0x10000>; /* 9 IMGSYS_ME */
mediatek,larb = <&larb12>;
iommus = <&iommu1 M4U_PORT_L12_IMG_ME_RDMA>,
<&iommu1 M4U_PORT_L12_IMG_ME_WDMA>;
clocks =
<&imgsys CLK_IMG_IPE>,
<&ipesys CLK_IPE_TOP>,
<&ipesys CLK_IPE_ME>,
<&ipesys CLK_IPE_SMI_LARB12>;
clock-names =
"ME_CG_IPE",
"ME_CG_IPE_TOP",
"ME_CG",
"ME_CG_LARB12";
};
ipesys: syscon@15330000 {
compatible = "mediatek,mt8195-ipesys", "syscon";
reg = <0 0x15330000 0 0x1000>;
#clock-cells = <1>;
};
larb12: larb@15340000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x15340000 0 0x1000>;
mediatek,larb-id = <12>;
mediatek,smi = <&smi_common1>;
clocks = <&imgsys CLK_IMG_IPE>,
<&ipesys CLK_IPE_SMI_LARB12>,
<&imgsys CLK_IMG_GALS>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
};
camsys: syscon@16000000 {
compatible = "mediatek,mt8195-camsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
camisp: camisp@16000000 {
compatible = "mediatek,mt8195-camisp";
reg = <0 0x16000000 0 0x1000>;
mediatek,ccd = <&remoteproc_ccd>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
operating-points-v2 = <&opp_table_cam>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
};
camisp_l13 {
compatible = "mediatek,mt8195-camisp-larb";
mediatek,larb-id = <13>;
iommus = <&iommu0 M4U_PORT_L13_CAM_CAMSV_CQI_E1>,
<&iommu0 M4U_PORT_L13_CAM_CAMSV_CQI_E2>,
<&iommu0 M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0>,
<&iommu0 M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0>,
<&iommu0 M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0>,
<&iommu0 M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1>,
<&iommu0 M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0>,
<&iommu0 M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0>,
<&iommu0 M4U_PORT_L13_CAM_PDAI_0>,
<&iommu0 M4U_PORT_L13_CAM_FAKE>;
};
camisp_l14 {
compatible = "mediatek,mt8195-camisp-larb";
mediatek,larb-id = <14>;
iommus = <&iommu1 M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1>,
<&iommu1 M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1>,
<&iommu1 M4U_PORT_L14_CAM_GCAMSV_C_IMGO_0>,
<&iommu1 M4U_PORT_L14_CAM_GCAMSV_C_IMGO_1>,
<&iommu1 M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0>,
<&iommu1 M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1>,
<&iommu1 M4U_PORT_L14_CAM_IPUI>,
<&iommu1 M4U_PORT_L14_CAM_IPU2I>,
<&iommu1 M4U_PORT_L14_CAM_IPUO>,
<&iommu1 M4U_PORT_L14_CAM_IPU2O>,
<&iommu1 M4U_PORT_L14_CAM_IPU3O>,
<&iommu1 M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1>,
<&iommu1 M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1>,
<&iommu1 M4U_PORT_L14_CAM_PDAI_1>,
<&iommu1 M4U_PORT_L14_CAM_PDAO>;
};
larb13: larb@16001000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16001000 0 0x1000>;
mediatek,larb-id = <13>;
mediatek,smi = <&smi_common0>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_CAM2MM0_GALS>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
};
larb14: larb@16002000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16002000 0 0x1000>;
mediatek,larb-id = <14>;
mediatek,smi = <&smi_common1 &smi_common2>;
clocks = <&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_CAM2MM1_GALS>,
<&camsys CLK_CAM_CAM2SYS_GALS>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
clock-names = "apb", "smi", "gals", "gals1", "gals2";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
};
seninf_top: seninf_top@16007000 {
compatible = "mediatek,seninf-core";
reg = <0 0x16007000 0 0x8000>,
<0 0x11E50000 0 0xc000>;
reg-names = "base", "ana-rx";
interrupts = <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CSI_RX_TOP>,
<&spm MT8195_POWER_DOMAIN_CAM>;
operating-points-v2 = <&opp_table_cam>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
clocks = <&camsys CLK_CAM_SENINF>,
<&topckgen CLK_TOP_SENINF_SEL>,
<&topckgen CLK_TOP_SENINF1_SEL>,
<&topckgen CLK_TOP_SENINF2_SEL>,
<&topckgen CLK_TOP_SENINF3_SEL>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "clk_cam_seninf",
"clk_top_seninf",
"clk_top_seninf1",
"clk_top_seninf2",
"clk_top_seninf3",
"clk_top_camtm";
};
larb16: larb@16012000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16012000 0 0x1000>;
mediatek,larb-id = <16>;
mediatek,smi = <&smi_common1 &smi_common2>;
clocks = <&camsys CLK_CAM_LARB14>,
<&camsys_rawa CLK_CAM_RAWA_LARBX>,
<&camsys CLK_CAM_CAM2MM1_GALS>,
<&camsys CLK_CAM_CAM2SYS_GALS>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
clock-names = "apb", "smi", "gals", "gals1", "gals2";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
};
larb17: larb@16013000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16013000 0 0x1000>;
mediatek,larb-id = <17>;
mediatek,smi = <&smi_common0>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys_yuva CLK_CAM_YUVA_LARBX>,
<&camsys CLK_CAM_CAM2MM0_GALS>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
};
larb27: larb@16014000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16014000 0 0x1000>;
mediatek,larb-id = <27>;
mediatek,smi = <&smi_common1 &smi_common2>;
clocks = <&camsys CLK_CAM_LARB14>,
<&camsys_rawb CLK_CAM_RAWB_LARBX>,
<&camsys CLK_CAM_CAM2MM1_GALS>,
<&camsys CLK_CAM_CAM2SYS_GALS>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
clock-names = "apb", "smi", "gals", "gals1", "gals2";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
};
larb28: larb@16015000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16015000 0 0x1000>;
mediatek,larb-id = <28>;
mediatek,smi = <&smi_common0>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys_yuvb CLK_CAM_YUVB_LARBX>,
<&camsys CLK_CAM_CAM2MM0_GALS>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
};
cam_raw_a@16030000 {
compatible = "mediatek,mt8195-cam-raw";
reg = <0 0x16030000 0 0x8000>,
<0 0x16038000 0 0x8000>;
reg-names = "base", "inner_base";
mediatek,cam-id = <0>;
interrupts = <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
clocks = <&camsys CLK_CAM_MAIN_CAM>,
<&camsys CLK_CAM_MAIN_CAMTG>,
<&camsys_rawa CLK_CAM_RAWA_LARBX>,
<&camsys_rawa CLK_CAM_RAWA_CAM>,
<&camsys_rawa CLK_CAM_RAWA_CAMTG>,
<&topckgen CLK_TOP_CAM_SEL>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_cam_cgpdn",
"camsys_camtg_cgpdn",
"camsys_rawa_larbx_cgpdn",
"camsys_rawa_cam_cgpdn",
"camsys_rawa_camtg_cgpdn",
"topckgen_top_cam_sel",
"topckgen_top_camtm_sel";
iommus = <&iommu1 M4U_PORT_L16_CAM_IMGO_R1>,
<&iommu1 M4U_PORT_L16_CAM_CQI_R1>,
<&iommu1 M4U_PORT_L16_CAM_CQI_R2>,
<&iommu1 M4U_PORT_L16_CAM_BPCI_R1>,
<&iommu1 M4U_PORT_L16_CAM_LSCI_R1>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R2>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R3>,
<&iommu1 M4U_PORT_L16_CAM_UFDI_R2>,
<&iommu1 M4U_PORT_L16_CAM_UFDI_R3>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R4>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R5>,
<&iommu1 M4U_PORT_L16_CAM_AAI_R1>,
<&iommu1 M4U_PORT_L16_CAM_FHO_R1>,
<&iommu1 M4U_PORT_L16_CAM_AAO_R1>,
<&iommu1 M4U_PORT_L16_CAM_TSFSO_R1>,
<&iommu1 M4U_PORT_L16_CAM_FLKO_R1>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_IMGO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_CQI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_CQI_R2)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_BPCI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_LSCI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_RAWI_R2)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_RAWI_R3)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_UFDI_R2)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_UFDI_R3)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_RAWI_R4)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_RAWI_R5)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_AAI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_FHO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_AAO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_TSFSO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CAM_FLKO_R1)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"l16_imgo_r1",
"l16_cqi_r1",
"l16_cqi_r2",
"l16_bpci_r1",
"l16_lsci_r1",
"l16_rawi_r2",
"l16_rawi_r3",
"l16_ufdi_r2",
"l16_ufdi_r3",
"l16_rawi_r4",
"l16_rawi_r5",
"l16_aai_r1",
"l16_fho_r1",
"l16_aao_r1",
"l16_tsfso_r1",
"l16_flko_r1";
};
cam_yuv_a@16050000 {
compatible = "mediatek,mt8195-cam-yuv";
reg = <0 0x16050000 0 0x8000>;
reg-names = "base";
mediatek,cam-id = <0>;
interrupts = <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
<&camsys_yuva CLK_CAM_YUVA_CAM>,
<&camsys_yuva CLK_CAM_YUVA_CAMTG>;
clock-names = "camsys_yuva_larbx_cgpdn",
"camsys_yuva_cam_cgpdn",
"camsys_yuva_camtg_cgpdn";
iommus = <&iommu0 M4U_PORT_L17_CAM_YUVO_R1>,
<&iommu0 M4U_PORT_L17_CAM_YUVO_R3>,
<&iommu0 M4U_PORT_L17_CAM_YUVCO_R1>,
<&iommu0 M4U_PORT_L17_CAM_YUVO_R2>,
<&iommu0 M4U_PORT_L17_CAM_RZH1N2TO_R1>,
<&iommu0 M4U_PORT_L17_CAM_DRZS4NO_R1>,
<&iommu0 M4U_PORT_L17_CAM_TNCSO_R1>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_CAM_YUVO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_CAM_YUVO_R3)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_CAM_YUVCO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_CAM_YUVO_R2)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_CAM_RZH1N2TO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_CAM_DRZS4NO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L17_CAM_TNCSO_R1)
&mmqos SLAVE_COMMON(0)>;
interconnect-names =
"l17_yuvo_r1",
"l17_yuvo_r3",
"l17_yuvco_r1",
"l17_yuvo_r2",
"l17_rzh1n2to_r1",
"l17_drzs4no_r1",
"l17_tncso_r1";
};
cam_raw_b@16070000 {
compatible = "mediatek,mt8195-cam-raw";
reg = <0 0x16070000 0 0x8000>,
<0 0x16078000 0 0x8000>;
reg-names = "base", "inner_base";
mediatek,cam-id = <1>;
interrupts = <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
clocks = <&camsys CLK_CAM_MAIN_CAM>,
<&camsys CLK_CAM_MAIN_CAMTG>,
<&camsys_rawb CLK_CAM_RAWB_LARBX>,
<&camsys_rawb CLK_CAM_RAWB_CAM>,
<&camsys_rawb CLK_CAM_RAWB_CAMTG>,
<&topckgen CLK_TOP_CAM_SEL>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_cam_cgpdn",
"camsys_camtg_cgpdn",
"camsys_rawb_larbx_cgpdn",
"camsys_rawb_cam_cgpdn",
"camsys_rawb_camtg_cgpdn",
"topckgen_top_cam_sel",
"topckgen_top_camtm_sel";
iommus = <&iommu1 M4U_PORT_L27_CAM_IMGO_R1>,
<&iommu1 M4U_PORT_L27_CAM_CQI_R1>,
<&iommu1 M4U_PORT_L27_CAM_CQI_R2>,
<&iommu1 M4U_PORT_L27_CAM_BPCI_R1>,
<&iommu1 M4U_PORT_L27_CAM_LSCI_R1>,
<&iommu1 M4U_PORT_L27_CAM_RAWI_R2>,
<&iommu1 M4U_PORT_L27_CAM_RAWI_R3>,
<&iommu1 M4U_PORT_L27_CAM_UFDI_R2>,
<&iommu1 M4U_PORT_L27_CAM_UFDI_R3>,
<&iommu1 M4U_PORT_L27_CAM_RAWI_R4>,
<&iommu1 M4U_PORT_L27_CAM_RAWI_R5>,
<&iommu1 M4U_PORT_L27_CAM_AAI_R1>,
<&iommu1 M4U_PORT_L27_CAM_FHO_R1>,
<&iommu1 M4U_PORT_L27_CAM_AAO_R1>,
<&iommu1 M4U_PORT_L27_CAM_TSFSO_R1>,
<&iommu1 M4U_PORT_L27_CAM_FLKO_R1>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_IMGO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_CQI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_CQI_R2)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_BPCI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_LSCI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_RAWI_R2)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_RAWI_R3)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_UFDI_R2)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_UFDI_R3)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_RAWI_R4)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_RAWI_R5)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_AAI_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_FHO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_AAO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_TSFSO_R1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L27_CAM_FLKO_R1)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"l27_imgo_r1",
"l27_cqi_r1",
"l27_cqi_r2",
"l27_bpci_r1",
"l27_lsci_r1",
"l27_rawi_r2",
"l27_rawi_r3",
"l27_ufdi_r2",
"l27_ufdi_r3",
"l27_rawi_r4",
"l27_rawi_r5",
"l27_aai_r1",
"l27_fho_r1",
"l27_aao_r1",
"l27_tsfso_r1",
"l27_flko_r1";
};
cam_yuv_b@16090000 {
compatible = "mediatek,mt8195-cam-yuv";
reg = <0 0x16090000 0 0x8000>;
reg-names = "base";
mediatek,cam-id = <1>;
interrupts = <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
<&camsys_yuvb CLK_CAM_YUVB_CAM>,
<&camsys_yuvb CLK_CAM_YUVB_CAMTG>;
clock-names = "camsys_yuvb_larbx_cgpdn",
"camsys_yuvb_cam_cgpdn",
"camsys_yuvb_camtg_cgpdn";
iommus = <&iommu0 M4U_PORT_L28_CAM_YUVO_R1>,
<&iommu0 M4U_PORT_L28_CAM_YUVO_R3>,
<&iommu0 M4U_PORT_L28_CAM_YUVCO_R1>,
<&iommu0 M4U_PORT_L28_CAM_YUVO_R2>,
<&iommu0 M4U_PORT_L28_CAM_RZH1N2TO_R1>,
<&iommu0 M4U_PORT_L28_CAM_DRZS4NO_R1>,
<&iommu0 M4U_PORT_L28_CAM_TNCSO_R1>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L28_CAM_YUVO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L28_CAM_YUVO_R3)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L28_CAM_YUVCO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L28_CAM_YUVO_R2)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L28_CAM_RZH1N2TO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L28_CAM_DRZS4NO_R1)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L28_CAM_TNCSO_R1)
&mmqos SLAVE_COMMON(0)>;
interconnect-names =
"l28_yuvo_r1",
"l28_yuvo_r3",
"l28_yuvco_r1",
"l28_yuvo_r2",
"l28_rzh1n2to_r1",
"l28_drzs4no_r1",
"l28_tncso_r1";
};
camsv1@160b0000 {
compatible = "mediatek,mt8195-camsv";
reg = <0 0x160b0000 0 0x1000>,
<0 0x160b8000 0 0x1000>;
reg-names = "reg";
mediatek,camsv-id = <0>;
interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_GCAMSVA>,
<&camsys CLK_CAM_CAMSV_TOP>,
<&camsys CLK_CAM_CAMSV_CQ>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_larb13_cgpdn",
"camsys_larb14_cgpdn",
"camsys_gcamsva_cgpdn",
"camsys_camsv_top_cgpdn",
"camsys_camsv_cq_cgpdn",
"topckgen_top_muxcamtm";
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0)
&mmqos SLAVE_COMMON(0)>;
interconnect-names = "l13_imgo_a0";
};
camsv2@160b1000 {
compatible = "mediatek,mt8195-camsv";
reg = <0 0x160b1000 0 0x1000>,
<0 0x160b9000 0 0x1000>;
reg-names = "reg";
mediatek,camsv-id = <1>;
interrupts = <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_GCAMSVA>,
<&camsys CLK_CAM_CAMSV_TOP>,
<&camsys CLK_CAM_CAMSV_CQ>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_larb13_cgpdn",
"camsys_larb14_cgpdn",
"camsys_gcamsva_cgpdn",
"camsys_camsv_top_cgpdn",
"camsys_camsv_cq_cgpdn",
"topckgen_top_muxcamtm";
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1)
&mmqos SLAVE_COMMON(1)>;
interconnect-names = "l14_imgo_a1";
};
camsv3@160b2000 {
compatible = "mediatek,mt8195-camsv";
reg = <0 0x160b2000 0 0x1000>,
<0 0x160ba000 0 0x1000>;
reg-names = "reg";
mediatek,camsv-id = <2>;
interrupts = <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_GCAMSVB>,
<&camsys CLK_CAM_CAMSV_TOP>,
<&camsys CLK_CAM_CAMSV_CQ>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_larb13_cgpdn",
"camsys_larb14_cgpdn",
"camsys_gcamsvb_cgpdn",
"camsys_camsv_top_cgpdn",
"camsys_camsv_cq_cgpdn",
"topckgen_top_muxcamtm";
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0)
&mmqos SLAVE_COMMON(0)>;
interconnect-names = "l13_imgo_b0";
};
camsv4@160b3000 {
compatible = "mediatek,mt8195-camsv";
reg = <0 0x160b3000 0 0x1000>,
<0 0x160bb000 0 0x1000>;
reg-names = "reg";
mediatek,camsv-id = <3>;
interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_GCAMSVB>,
<&camsys CLK_CAM_CAMSV_TOP>,
<&camsys CLK_CAM_CAMSV_CQ>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_larb13_cgpdn",
"camsys_larb14_cgpdn",
"camsys_gcamsvb_cgpdn",
"camsys_camsv_top_cgpdn",
"camsys_camsv_cq_cgpdn",
"topckgen_top_muxcamtm";
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1)
&mmqos SLAVE_COMMON(0)>;
interconnect-names = "l13_imgo_b1";
};
camsv5@160b4000 {
compatible = "mediatek,mt8195-camsv";
reg = <0 0x160b4000 0 0x1000>,
<0 0x160bc000 0 0x1000>;
reg-names = "reg";
mediatek,camsv-id = <4>;
interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_GCAMSVC>,
<&camsys CLK_CAM_CAMSV_TOP>,
<&camsys CLK_CAM_CAMSV_CQ>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_larb13_cgpdn",
"camsys_larb14_cgpdn",
"camsys_gcamsvc_cgpdn",
"camsys_camsv_top_cgpdn",
"camsys_camsv_cq_cgpdn",
"topckgen_top_muxcamtm";
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L14_CAM_GCAMSV_C_IMGO_0)
&mmqos SLAVE_COMMON(1)>;
interconnect-names = "l14_imgo_c0";
};
camsv6@160b5000 {
compatible = "mediatek,mt8195-camsv";
reg = <0 0x160b5000 0 0x1000>,
<0 0x160bd000 0 0x1000>;
reg-names = "reg";
mediatek,camsv-id = <5>;
interrupts = <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_GCAMSVC>,
<&camsys CLK_CAM_CAMSV_TOP>,
<&camsys CLK_CAM_CAMSV_CQ>,
<&topckgen CLK_TOP_CAMTM_SEL>;
clock-names = "camsys_larb13_cgpdn",
"camsys_larb14_cgpdn",
"camsys_gcamsvc_cgpdn",
"camsys_camsv_top_cgpdn",
"camsys_camsv_cq_cgpdn",
"topckgen_top_muxcamtm";
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L14_CAM_GCAMSV_C_IMGO_1)
&mmqos SLAVE_COMMON(1)>;
interconnect-names = "l14_imgo_c1";
};
remoteproc_ccd: remoteproc_ccd@16030000 {
compatible = "mediatek,ccd";
reg = <0 0x16030000 0 0x10000>;
iommus = <&iommu1 M4U_PORT_L16_CAM_IMGO_R1>,
<&iommu1 M4U_PORT_L16_CAM_CQI_R1>,
<&iommu1 M4U_PORT_L16_CAM_CQI_R2>,
<&iommu1 M4U_PORT_L16_CAM_BPCI_R1>,
<&iommu1 M4U_PORT_L16_CAM_LSCI_R1>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R2>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R3>,
<&iommu1 M4U_PORT_L16_CAM_UFDI_R2>,
<&iommu1 M4U_PORT_L16_CAM_UFDI_R3>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R4>,
<&iommu1 M4U_PORT_L16_CAM_RAWI_R5>,
<&iommu1 M4U_PORT_L16_CAM_AAI_R1>,
<&iommu1 M4U_PORT_L16_CAM_FHO_R1>,
<&iommu1 M4U_PORT_L16_CAM_AAO_R1>,
<&iommu1 M4U_PORT_L16_CAM_TSFSO_R1>,
<&iommu1 M4U_PORT_L16_CAM_FLKO_R1>;
msg_dev {
mtk,rpmsg-name = "mtk_ccd_msgdev";
};
};
camsys_rawa: syscon@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa", "syscon";
reg = <0 0x1604f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_yuva: syscon@1606f000 {
compatible = "mediatek,mt8195-camsys_yuva", "syscon";
reg = <0 0x1606f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawb: syscon@1608f000 {
compatible = "mediatek,mt8195-camsys_rawb", "syscon";
reg = <0 0x1608f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_yuvb: syscon@160af000 {
compatible = "mediatek,mt8195-camsys_yuvb", "syscon";
reg = <0 0x160af000 0 0x1000>;
#clock-cells = <1>;
};
pda: pda@160d0000 {
compatible = "mediatek,camera-pda";
reg = <0 0x160d0000 0 0x1000>;
interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&camsys CLK_CAM_PDA>;
clock-names = "PDA_TOP_MUX";
mediatek,pda2 = <&pda2>;
iommus = <&iommu0 M4U_PORT_L13_CAM_PDAI_0>;
};
camsys_mraw: syscon@16140000 {
compatible = "mediatek,mt8195-camsys_mraw", "syscon";
reg = <0 0x16140000 0 0x1000>;
#clock-cells = <1>;
};
larb25: larb@16141000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16141000 0 0x1000>;
mediatek,larb-id = <25>;
mediatek,smi = <&smi_common0>;
clocks = <&camsys CLK_CAM_LARB13>,
<&camsys_mraw CLK_CAM_MRAW_LARBX>,
<&camsys CLK_CAM_CAM2MM0_GALS>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
};
larb26: larb@16142000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x16142000 0 0x1000>;
mediatek,larb-id = <26>;
mediatek,smi = <&smi_common1>;
clocks = <&camsys CLK_CAM_LARB14>,
<&camsys_mraw CLK_CAM_MRAW_LARBX>,
<&camsys CLK_CAM_CAM2MM1_GALS>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
};
ccusys: syscon@17200000 {
compatible = "mediatek,mt8195-ccusys", "syscon";
reg = <0 0x17200000 0 0x1000>;
#clock-cells = <1>;
};
larb18: larb@17201000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x17201000 0 0x1000>;
mediatek,larb-id = <18>;
mediatek,smi = <&smi_common1>;
clocks = <&camsys CLK_CAM_LARB14>,
<&ccusys CLK_CCU_LARB18>,
<&camsys CLK_CAM_CAM2MM1_GALS>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
};
vcu: vcu@18000000 {
compatible = "mediatek-vcu";
mediatek,vcuid = <0>;
mediatek,vcuname = "vcu";
reg = <0 0x18000000 0 0x40000>,/* VDEC_BASE */
<0 0x1a020000 0 0x10000>,/* VENC_BASE */
<0 0x1b020000 0 0x10000>;/* VENC_C1_BASE */
mediatek,mailbox-gce = <&gce_mbox_d>;
mediatek,dec_gce_th_num = <1>;
mediatek,enc_gce_th_num = <2>;
mboxes = <&gce_mbox_d 16 3000 CMDQ_THR_PRIO_1>,
<&gce_mbox_d 17 3000 CMDQ_THR_PRIO_1>,
<&gce_mbox_d 18 3000 CMDQ_THR_PRIO_1>;
gce-event-names = "venc_eof",
"venc_eof_c1",
"venc_wp_2nd_done",
"venc_wp_3nd_done",
"vdec_pic_start",
"vdec_decode_done",
"vdec_pause",
"vdec_dec_error",
"vdec_mc_busy_overflow_timeout",
"vdec_all_dram_req_done",
"vdec_ini_fetch_rdy",
"vdec_process_flag",
"vdec_search_start_code_done",
"vdec_ref_reorder_done",
"vdec_wp_tble_done",
"vdec_count_sram_clr_done",
"vdec_gce_cnt_op_threshold",
"vdec_lat_pic_start",
"vdec_lat_decode_done",
"vdec_lat_pause",
"vdec_lat_dec_error",
"vdec_lat_mc_busy_overflow_timeout",
"vdec_lat_all_dram_req_done",
"vdec_lat_ini_fetch_rdy",
"vdec_lat_process_flag",
"vdec_lat_search_start_code_done",
"vdec_lat_ref_reorder_done",
"vdec_lat_wp_tble_done",
"vdec_lat_count_sram_clr_done",
"vdec_lat_gce_cnt_op_threshold";
gce-events = <&gce_mbox_d CMDQ_EVENT_VENC_TOP_FRAME_DONE>,
<&gce_mbox_d CMDQ_EVENT_VENC_CORE1_TOP_FRAME_DONE>,
<&gce_mbox_d
CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE>,
<&gce_mbox_d
CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE>;
gce-gpr = <GCE_GPR_R10>, <GCE_GPR_R11>;
};
vdec: vdec@18000000 {
compatible = "mediatek,mt8195-vcodec-dec";
reg = <0 0x18000000 0 0x800>,/* VDEC_SYS */
<0 0x18020000 0 0x1000>,/* VDEC_VLD */
<0 0x18025000 0 0x1000>,/* VDEC_MISC */
<0 0x18010000 0 0x800>,/* VDEC_LAT_MISC */
<0 0x18004000 0 0x1000>,/* VDEC_RACING_CTRL */
<0 0x18035000 0 0x1000>,/* VDEC_CORE1_MISC */
<0 0x18018000 0 0x800>,/* VDEC_LAT1_MISC */
<0 0x1800f000 0 0x800>,/* VDEC_SOC_GLOBAL */
<0 0x18010800 0 0x800>,/* VDEC_LAT_WDMA */
<0 0x18018800 0 0x800>,/* VDEC_LAT1_WDMA */
<0 0x18001000 0 0x1000>,/* VDEC_LAT_TOP */
<0 0x18000800 0 0x800>;/* VDEC_UFO_ENC */
iommus = <&iommu1 M4U_PORT_L23_VDEC_UFO_ENC_EXT>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;/* SOC */
interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys CLK_VDEC_LARB1>,
<&vdecsys CLK_VDEC_LAT>,
<&vdecsys CLK_VDEC_VDEC>,
<&vdecsys_core1 CLK_VDEC_CORE1_LARB1>,
<&vdecsys_core1 CLK_VDEC_CORE1_LAT>,
<&vdecsys_core1 CLK_VDEC_CORE1_VDEC>,
<&topckgen CLK_TOP_VDECPLL>;
clock-names = "MT_CG_SOC_LARB1",
"MT_CG_SOC_LAT",
"MT_CG_SOC_VDEC",
"MT_CG_LARB1",
"MT_CG_LAT",
"MT_CG_VDEC",
"MT_CG_CORE1_LARB1",
"MT_CG_CORE1_LAT",
"MT_CG_CORE1_VDEC",
"vdecpll_ck";
mediatek,vcu = <&vcu>;
operating-points-v2 = <&opp_table_vdec>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_MC_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_UFO_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_PP_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_PRED_RD_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_PRED_WR_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_PPWRAP_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_TILE_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_VLD_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_VLD2_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L21_VDEC_AVC_MV_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_MC_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_UFO_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_PP_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_PRED_RD_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_PRED_WR_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_PPWRAP_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_TILE_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_VLD_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_VLD2_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L22_VDEC_AVC_MV_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L23_VDEC_UFO_ENC_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L23_VDEC_RDMA_EXT)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT0_VLD_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT0_VLD2_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT0_TILE_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT0_WDMA_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT1_VLD_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT1_VLD2_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT1_TILE_EXT)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L24_VDEC_LAT1_WDMA_EXT)
&mmqos SLAVE_COMMON(0)>;
interconnect-names =
"l21_mc",
"l21_ufo",
"l21_pp",
"l21_pred_rd",
"l21_pred_wr",
"l21_ppwrap",
"l21_tile",
"l21_vld",
"l21_vld2",
"l21_avc_mv",
"l22_mc",
"l22_ufo",
"l22_pp",
"l22_pred_rd",
"l22_pred_wr",
"l22_ppwrap",
"l22_tile",
"l22_vld",
"l22_vld2",
"l22_avc_mv",
"l23_ufo_enc",
"l23_rdma",
"lat0_vld",
"lat0_vld2",
"lat0_avc_mc",
"lat0_pred_rd",
"lat0_tile",
"lat0_wdma",
"lat1_vld",
"lat1_vld2",
"lat1_avc_mc",
"lat1_pred_rd",
"lat1_tile",
"lat1_wdma";
};
larb24: larb@1800d000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1800d000 0 0x1000>;
mediatek,larb-id = <24>;
mediatek,smi = <&smi_common0>;
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
};
larb23: larb@1800e000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1800e000 0 0x1000>;
mediatek,larb-id = <23>;
mediatek,smi = <&smi_common1>;
clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
};
vdecsys_soc: syscon@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc", "syscon";
reg = <0 0x1800f000 0 0x1000>;
#clock-cells = <1>;
};
larb21: larb@1802e000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1802e000 0 0x1000>;
mediatek,larb-id = <21>;
mediatek,smi = <&smi_common0>;
clocks = <&vdecsys CLK_VDEC_LARB1>,
<&vdecsys CLK_VDEC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
};
vdecsys: syscon@1802f000 {
compatible = "mediatek,mt8195-vdecsys", "syscon";
reg = <0 0x1802f000 0 0x1000>;
#clock-cells = <1>;
};
larb22: larb@1803e000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1803e000 0 0x1000>;
mediatek,larb-id = <22>;
mediatek,smi = <&smi_common1>;
clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
<&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
};
vdecsys_core1: syscon@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1", "syscon";
reg = <0 0x1803f000 0 0x1000>;
#clock-cells = <1>;
};
iommu2: apu-iommu@19010000 {
compatible = "mediatek,mt8195-iommu-apu";
reg = <0 0x19010000 0 0x1000>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
/* mediatek,apu_power = <&apusys_rv>; */
#iommu-cells = <1>;
};
iommu3: apu-iommu@19015000 {
compatible = "mediatek,mt8195-iommu-apu";
reg = <0 0x19015000 0 0x1000>;
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
/* mediatek,apu_power = <&apusys_rv>; */
#iommu-cells = <1>;
};
apu_conn: syscon@19020000 {
compatible = "mediatek,mt8195-apu_conn", "syscon";
reg = <0 0x19020000 0 0x1000>;
};
apusys_reviser@19021000 {
compatible = "mediatek,apusys_reviser";
reg = <0 0x19021000 0 0x1000>, /* apu_sctrl_reviser */
<0 0x1d800000 0 0x400000>, /* VLM */
<0 0x1d000000 0 0x100000>, /* TCM */
<0 0x19001000 0 0x1000>; /* apusys int */
interrupts = <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu2 M4U_PORT_L31_APU_VLM>;
};
apu_conn1: syscon@19024000 {
compatible = "mediatek,mt8195-apu_conn1", "syscon";
reg = <0 0x19024000 0 0x1000>;
};
edma0: edma0@19025000 {
compatible = "mtk,edma-sub";
reg = <0x0 0x19025000 0x0 0x1000>;
interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu2 M4U_PORT_L31_APU_DATA>;
};
edma1: edma1@19026000 {
compatible = "mtk,edma-sub";
reg = <0x0 0x19026000 0x0 0x1000>;
interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu3 M4U_PORT_L31_APU_DATA>;
};
apu_vcore: syscon@19029000 {
compatible = "mediatek,mt8195-apu_vcore", "syscon";
reg = <0 0x19029000 0 0x1000>;
};
apu0: syscon@19030000 {
compatible = "mediatek,mt8195-apu0", "syscon";
reg = <0 0x19030000 0 0x1000>;
};
vpu_core0: vpu_core0@19030000 {
compatible = "mediatek,vpu_core0";
reg = <0 0x19030000 0 0x1000>,
<0 0x1d400000 0 0x40000>,
<0 0x1d440000 0 0x30000>,
<0 0x0d190000 0 0x4000>;
interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH 0>;
id = <0>;
reset-vector = <0x7da00000 0x00100000 0x0>;
main-prog = <0x7db00000 0x00300000 0x100000>;
kernel-lib = <0x7de00000 0x00500000 0xffffffff>;
work-buf = <0x0 0x12000 0xffffffff>;
iommus = <&iommu2 M4U_PORT_L31_APU_CODE>;
#cooling-cells = <2>;
};
apu1: syscon@19031000 {
compatible = "mediatek,mt8195-apu1", "syscon";
reg = <0 0x19031000 0 0x1000>;
};
vpu_core1: vpu_core1@19031000 {
compatible = "mediatek,vpu_core1";
reg = <0 0x19031000 0 0x1000>,
<0 0x1d500000 0 0x40000>,
<0 0x1d540000 0 0x30000>,
<0 0x0d194000 0 0x4000>;
interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH 0>;
id = <1>;
reset-vector = <0x7e300000 0x00100000 0x400000>;
main-prog = <0x7e400000 0x00300000 0x500000>;
kernel-lib = <0x7e700000 0x00500000 0xffffffff>;
work-buf = <0x0 0x12000 0xffffffff>;
iommus = <&iommu3 M4U_PORT_L31_APU_CODE>;
#cooling-cells = <2>;
};
apu_mdla0: syscon@19034000 {
compatible = "mediatek,mt8195-apu_mdla0", "syscon";
reg = <0 0x19034000 0 0x1000>;
};
mtk_mdla: mdla@19034000 {
compatible = "mediatek, mt8195-mdla";
core_num = <2>;
version = <0x81950200>;
reg = <0 0x19034000 0 0x1000>, /* dla0 config */
<0 0x19036000 0 0x1000>, /* dla0 command */
<0 0x19035000 0 0x1000>, /* dla0 biu */
<0 0x19038000 0 0x1000>, /* dla1 config */
<0 0x1903a000 0 0x1000>, /* dla1 command */
<0 0x19039000 0 0x1000>, /* dla1 biu */
<0 0x1d000000 0 0x100000>,/* GSM,TODO */
<0 0x19020000 0 0x40000>; /* APU CONN */
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>;
iommus = <&iommu2 M4U_PORT_L31_APU_DATA>;
#cooling-cells = <2>;
};
apu_mdla1: syscon@19038000 {
compatible = "mediatek,mt8195-apu_mdla1", "syscon";
reg = <0 0x19038000 0 0x1000>;
};
apusys_mnoc@1906e000 {
compatible = "mediatek,apusys_mnoc";
reg = <0 0x1906e000 0 0x6000>, /* mnoc reg */
<0 0x19001000 0 0x1000>, /* apusys int */
<0 0x19020000 0 0x1000>; /* apu_conn_config */
interrupts = <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
};
apu_top: apu_top@0x190f0000 {
compatible = "mediatek,apu_top", "syscon";
reg = <0 0x190f0000 0 0x1000>;
clocks = <&apusys_pll CLK_APUSYS_PLL_APUPLL>,
<&apusys_pll CLK_APUSYS_PLL_NPUPLL>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL1>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL2>;
clock-names = "clk_apupll_apupll",
"clk_apupll_npupll",
"clk_apupll_apupll1",
"clk_apupll_apupll2";
};
apu_pcu: syscon@190f1000 {
compatible = "mediatek,mt8195-apu_pcu", "syscon";
reg = <0 0x190f1000 0 0x1000>;
};
apusys_power: apusys_power@0x190f1000 {
compatible = "mediatek,apusys_power";
reg = <0 0x190f1000 0 0x1000>,
<0 0x190f0000 0 0x1000>,
<0 0x19029000 0 0x1000>;
reg-names = "apusys_pcu",
"apusys_rpc",
"apusys_vcore";
power-domains = <&apuspm MT8195_POWER_DOMAIN_APUSYS_TOP>;
clocks = <&apusys_pll CLK_APUSYS_PLL_APUPLL>,
<&apusys_pll CLK_APUSYS_PLL_NPUPLL>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL1>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL2>;
clock-names = "clk_apupll_apupll",
"clk_apupll_npupll",
"clk_apupll_apupll1",
"clk_apupll_apupll2";
apusys,thermal-zones = "vpu1", "vpu2";
};
apu_ao_ctrl: syscon@190f2000 {
compatible = "mediatek,mt8195-apu_ao_ctrl", "syscon";
reg = <0 0x190f2000 0 0x1000>;
};
apusys_pll: syscon@190f3000 {
compatible = "mediatek,mt8195-apusys_pll", "syscon";
reg = <0 0x190f3000 0 0x1000>;
#clock-cells = <1>;
};
apu_acc: syscon@190f4000 {
compatible = "mediatek,mt8195-apu_acc", "syscon";
reg = <0 0x190f4000 0 0x100>;
};
vencsys: syscon@1a000000 {
compatible = "mediatek,mt8195-vencsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
larb19: larb@1a010000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1a010000 0 0x1000>;
mediatek,larb-id = <19>;
mediatek,smi = <&smi_common0 &smi_common2>;
clocks = <&vencsys CLK_VENC_VENC>,
<&vencsys CLK_VENC_LARB>,
<&vencsys CLK_VENC_GALS>,
<&vppsys0 CLK_VPP0_GALS_VENCSYS>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
};
venc@1a020000 {
compatible = "mediatek,mt8195-vcodec-enc";
reg = <0 0x1a020000 0 0x10000>,/* VENC_C0 */
<0 0x1b020000 0 0x10000>;/* VENC_C1 */
iommus = <&iommu0 M4U_PORT_L19_VENC_RD_COMV>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_VENC>,
<&vencsys_core1 CLK_VENC_CORE1_VENC>;
clock-names = "MT_CG_VENC0",
"MT_CG_VENC1";
mediatek,vcu = <&vcu>;
operating-points-v2 = <&opp_table_venc>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_RCPU)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_REC)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_BSDMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_SV_COMV)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_RD_COMV)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_NBM_RDMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_NBM_RDMA_LITE)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_SUB_W_LUMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_FCS_NBM_RDMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_NBM_WDMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_NBM_WDMA_LITE)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_FCS_NBM_WDMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_CUR_LUMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_CUR_CHROMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_REF_LUMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_REF_CHROMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L19_VENC_SUB_R_CHROMA)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_RCPU)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_REC)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_BSDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_SV_COMV)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_RD_COMV)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_NBM_RDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_NBM_RDMA_LITE)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_SUB_W_LUMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_FCS_NBM_RDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_NBM_WDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_NBM_WDMA_LITE)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_FCS_NBM_WDMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_CUR_LUMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_CUR_CHROMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_REF_LUMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_REF_CHROMA)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L20_VENC_SUB_R_CHROMA)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"l19_venc_rcpu",
"l19_venc_rec",
"l19_venc_bsdma",
"l19_venc_sv_comv",
"l19_venc_rd_comv",
"l19_venc_nbm_rdma",
"l19_venc_nbm_rdma_lite",
"l19_venc_sub_w_luma",
"l19_venc_fcs_nbm_rdma",
"l19_venc_nbm_wdma",
"l19_venc_nbm_wdma_lite",
"l19_venc_fcs_nbm_wdma",
"l19_venc_cur_luma",
"l19_venc_cur_chroma",
"l19_venc_ref_luma",
"l19_venc_ref_chroma",
"l19_venc_sub_r_chroma",
"l20_venc_rcpu",
"l20_venc_rec",
"l20_venc_bsdma",
"l20_venc_sv_comv",
"l20_venc_rd_comv",
"l20_venc_nbm_rdma",
"l20_venc_nbm_rdma_lite",
"l20_venc_sub_w_luma",
"l20_venc_fcs_nbm_rdma",
"l20_venc_nbm_wdma",
"l20_venc_nbm_wdma_lite",
"l20_venc_fcs_nbm_wdma",
"l20_venc_cur_luma",
"l20_venc_cur_chroma",
"l20_venc_ref_luma",
"l20_venc_ref_chroma",
"l20_venc_sub_r_chroma";
};
jpgenc@1a030000 {
compatible = "mediatek,mt8195-jpgenc";
reg = <0 0x1a030000 0 0x10000>;
mediatek,larb-id = <19>;
iommus = <&iommu0 M4U_PORT_L19_JPGENC_Y_RDMA>,
<&iommu0 M4U_PORT_L19_JPGENC_C_RDMA>,
<&iommu0 M4U_PORT_L19_JPGENC_Q_TABLE>,
<&iommu0 M4U_PORT_L19_JPGENC_BSDMA>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGENC>;
clock-names = "jpgenc";
};
jpgdec@1a040000 {
compatible = "mediatek,mt8195-jpgdec";
reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
mediatek,larb-id = <19>;
iommus = <&iommu0 M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu0 M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu0 M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu0 M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu0 M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu0 M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGDEC>;
clock-names = "jpgdec";
};
jpgdec@1a050000 {
compatible = "mediatek,mt8195-jpgdec";
reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
mediatek,larb-id = <19>;
iommus = <&iommu0 M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu0 M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu0 M4U_PORT_L19_JPGDEC_WDMA1>,
<&iommu0 M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu0 M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu0 M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
clock-names = "jpgdec";
};
vencsys_core1: syscon@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
larb20: larb@1b010000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1b010000 0 0x1000>;
mediatek,larb-id = <20>;
mediatek,smi = <&smi_common1 &smi_common2>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
<&vencsys_core1 CLK_VENC_CORE1_LARB>,
<&vencsys_core1 CLK_VENC_CORE1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
<&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>;
clock-names = "apb", "smi", "gals", "gals1", "gals2";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
jpgenc@1b030000 {
compatible = "mediatek,mt8195-jpgenc";
reg = <0 0x1b030000 0 0x10000>;
mediatek,larb-id = <20>;
iommus = <&iommu1 M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu1 M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu1 M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu1 M4U_PORT_L20_JPGENC_BSDMA>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
clock-names = "jpgenc";
};
jpgdec@1b040000 {
compatible = "mediatek,mt8195-jpgdec";
reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
mediatek,larb-id = <20>;
iommus = <&iommu1 M4U_PORT_L20_JPGDEC_WDMA0>,
<&iommu1 M4U_PORT_L20_JPGDEC_BSDMA0>,
<&iommu1 M4U_PORT_L20_JPGDEC_WDMA1>,
<&iommu1 M4U_PORT_L20_JPGDEC_BSDMA1>,
<&iommu1 M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
<&iommu1 M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
clock-names = "jpgdec";
};
disp_ovl0: disp_ovl@1c000000 {
compatible = "mediatek,mt8195-disp-ovl";
reg = <0 0x1c000000 0 0x1000>;
interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
mediatek,larb = <&larb0>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_OVL0_RDMA0>,
<&iommu0 M4U_PORT_L0_DISP_OVL0_RDMA1>,
<&iommu0 M4U_PORT_L0_DISP_OVL0_HDR>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_RDMA0)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_RDMA0)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_RDMA0)
&mmqos SLAVE_COMMON(0)>;
interconnect-names =
"DDP_COMPONENT_OVL0_qos",
"DDP_COMPONENT_OVL0_fbdc_qos",
"DDP_COMPONENT_OVL0_hrt_qos";
};
disp_wdma0: disp_wdma@1c001000 {
compatible = "mediatek,mt8195-disp-wdma";
reg = <0 0x1c001000 0 0x1000>;
interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_WDMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
mediatek,larb = <&larb0>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_WDMA0>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_WDMA0)
&mmqos SLAVE_COMMON(0)>;
interconnect-names =
"l0_disp_wdma0";
};
disp_rdma0: disp_rdma@1c002000 {
compatible = "mediatek,mt8195-disp-rdma";
reg = <0 0x1c002000 0 0x1000>;
interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
mediatek,larb = <&larb0>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
&mmqos SLAVE_COMMON(0)>;
interconnect-names =
"DDP_COMPONENT_RDMA0_qos",
"DDP_COMPONENT_RDMA0_hrt_qos";
};
disp_color0: disp_color@1c003000 {
compatible = "mediatek,mt8195-disp-color";
reg = <0 0x1c003000 0 0x1000>;
interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_ccorr0: disp_ccorr@1c004000 {
compatible = "mediatek,mt8195-disp-ccorr";
reg = <0 0x1c004000 0 0x1000>;
interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_aal0: disp_aal@1c005000 {
compatible = "mediatek,mt8195-disp-aal";
reg = <0 0x1c005000 0 0x1000>;
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_gamma0: disp_gamma@1c006000 {
compatible = "mediatek,mt8195-disp-gamma";
reg = <0 0x1c006000 0 0x1000>;
interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_dither0: disp_dither@1c007000 {
compatible = "mediatek,mt8195-disp-dither";
reg = <0 0x1c007000 0 0x1000>;
interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_dsi0: disp_dsi0@1c008000 {
compatible = "mediatek,mt8195-dsi";
reg = <0 0x1c008000 0 0x1000>;
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&vdosys0 CLK_VDO0_DSI0>,
<&vdosys0 CLK_VDO0_DSI0_DSI>,
<&mipi_tx_config0>;
clock-names = "engine", "digital", "hs";
phys = <&mipi_tx_config0>;
phy-names = "dphy";
status = "disabled";
};
disp_dsc_wrap@1c009000 {
compatible = "mediatek,mt8195-disp-dsc";
reg = <0 0x1c009000 0 0x1000>;
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_ovl1: disp_ovl@1c00a000 {
compatible = "mediatek,mt8195-disp-ovl";
reg = <0 0x1c00a000 0 0x1000>;
interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_OVL1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
mediatek,larb = <&larb1>;
mediatek,smi-id = <1>;
iommus = <&iommu1 M4U_PORT_L1_DISP_OVL0_RDMA0>,
<&iommu1 M4U_PORT_L1_DISP_OVL0_RDMA1>,
<&iommu1 M4U_PORT_L1_DISP_OVL0_HDR>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_RDMA0)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_RDMA0)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_RDMA0)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"DDP_COMPONENT_OVL1_qos",
"DDP_COMPONENT_OVL1_fbdc_qos",
"DDP_COMPONENT_OVL1_hrt_qos";
};
disp_wdma1: disp_wdma@1c00b000 {
compatible = "mediatek,mt8195-disp-wdma";
reg = <0 0x1c00b000 0 0x1000>;
interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_WDMA1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
mediatek,larb = <&larb1>;
mediatek,smi-id = <1>;
iommus = <&iommu1 M4U_PORT_L1_DISP_WDMA0>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_WDMA0)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"l1_disp_wdma0";
};
disp_rdma1: disp_rdma@1c00c000 {
compatible = "mediatek,mt8195-disp-rdma";
reg = <0 0x1c00c000 0 0x1000>;
interrupts = <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_RDMA1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
mediatek,larb = <&larb1>;
mediatek,smi-id = <1>;
iommus = <&iommu1 M4U_PORT_L1_DISP_RDMA0>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA0)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA0)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"DDP_COMPONENT_RDMA1_qos",
"DDP_COMPONENT_RDMA1_hrt_qos";
};
disp_color1: disp_color@1c00d000 {
compatible = "mediatek,mt8195-disp-color";
reg = <0 0x1c00d000 0 0x1000>;
interrupts = <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_COLOR1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_ccorr1: disp_ccorr@1c00e000 {
compatible = "mediatek,mt8195-disp-ccorr";
reg = <0 0x1c00e000 0 0x1000>;
interrupts = <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_CCORR1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_aal1: disp_aal@1c00f000 {
compatible = "mediatek,mt8195-disp-aal";
reg = <0 0x1c00f000 0 0x1000>;
interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_AAL1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_gamma1: disp_gamma@1c010000 {
compatible = "mediatek,mt8195-disp-gamma";
reg = <0 0x1c010000 0 0x1000>;
interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_dither1: disp_dither@1c011000 {
compatible = "mediatek,mt8195-disp-dither";
reg = <0 0x1c011000 0 0x1000>;
interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DISP_DITHER1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
disp_dsi1: disp_dsi1@1c012000 {
compatible = "mediatek,mt8195-dsi";
reg = <0 0x1c012000 0 0x1000>;
interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DSI1>,
<&vdosys0 CLK_VDO0_DSI1_DSI>,
<&mipi_tx_config1>;
clock-names = "engine", "digital", "hs";
phys = <&mipi_tx_config1>;
phy-names = "dphy";
status = "disabled";
};
disp_merge0: disp_vpp_merge0@1c014000 {
compatible = "mediatek,mt8195-disp-merge";
reg = <0 0x1c014000 0 0x1000>;
interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
dp_intf0: dp_intf0@1c015000 {
compatible = "mediatek,mt8195-dp_intf", "mediatek,mt8188-dp_intf";
reg = <0 0x1c015000 0 0x1000>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
<&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
<&topckgen CLK_TOP_EDP_SEL>,
<&topckgen CLK_TOP_TVDPLL1_D2>,
<&topckgen CLK_TOP_TVDPLL1_D4>,
<&topckgen CLK_TOP_TVDPLL1_D8>,
<&topckgen CLK_TOP_TVDPLL1_D16>,
<&topckgen CLK_TOP_TVDPLL1>;
clock-names = "engine",
"ck_cg",
"pixel",
"TVDPLL_D2",
"TVDPLL_D4",
"TVDPLL_D8",
"TVDPLL_D16",
"pll";
status = "disabled";
};
disp_mutex0@1c016000 {
compatible = "mediatek,mt8195-disp-mutex";
reg = <0 0x1c016000 0 0x1000>,
<0 0x1c101000 0 0x1000>;
reg-names = "vdo0_mutex","vdo1_mutex";
clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>,
<&vdosys1 CLK_VDO1_DISP_MUTEX>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clock-names = "vdo0_mutex", "vdo1_mutex";
interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
};
larb0: larb@1c018000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1c018000 0 0x1000>;
mediatek,larb-id = <0>;
mediatek,smi = <&smi_common0 &smi_common2>;
clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
<&vdosys0 CLK_VDO0_SMI_LARB>,
<&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
larb1: larb@1c019000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1c019000 0 0x1000>;
mediatek,larb-id = <1>;
mediatek,smi = <&smi_common1 &smi_common2>;
clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
<&vdosys0 CLK_VDO0_SMI_LARB>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
<&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
#clock-cells = <1>;
};
vdosys_config: vdosys_config@1c01a000 {
compatible = "mediatek,mt8195-vdosys";
reg = <0 0x1c01a000 0 0x1000>, <0 0x1c100000 0 0x1000>;
reg-names = "vdosys0_config", "vdosys1_config";
iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
mediatek,larb = <&larb0>;
fake-engine = <&larb0 M4U_PORT_L0_DISP_FAKE0>,
<&larb1 M4U_PORT_L1_DISP_FAKE0>;
clocks = <&topckgen CLK_TOP_VPP_SEL>,
<&topckgen CLK_TOP_CFG_26M_AUD>,
<&topckgen CLK_TOP_CFG_VDO0>,
<&topckgen CLK_TOP_CFG_VDO1>,
<&topckgen CLK_TOP_ETHDR_SEL>,
<&vdosys0 CLK_VDO0_DISP_MUTEX0>,
<&vdosys1 CLK_VDO1_DISP_MUTEX>;
clock-num = <7>;
clock-relation = <255>,<255>,<0>,<1>,<1>,
<0>,<1>;
operating-points-v2 = <&opp_table_vdo>;
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0)
&mmqos SLAVE_COMMON(0)>;
interconnect-names =
"disp_hrt_qos";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
/* define threads, see mt8195-gce.h */
mediatek,mailbox-gce = <&gce_mbox_d>;
mboxes = <&gce_mbox_d 0 0 CMDQ_THR_PRIO_4>,
<&gce_mbox_d 1 0 CMDQ_THR_PRIO_4>,
<&gce_mbox_d 2 0 CMDQ_THR_PRIO_4>,
<&gce_mbox_d 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
<&gce_mbox_d 5 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
<&gce_mbox_d 4 0 CMDQ_THR_PRIO_4>,
<&gce_mbox_d 6 0 CMDQ_THR_PRIO_3>;
gce-client-names = "CLIENT_CFG0",
"CLIENT_CFG1",
"CLIENT_CFG2",
"CLIENT_TRIG_LOOP0",
"CLIENT_TRIG_LOOP1",
"CLIENT_SUB_CFG0",
"CLIENT_DSI_CFG0",
"CLIENT_SEC_CFG0",
"CLIENT_SEC_CFG1";
/* define subsys, see mt8195-gce.h */
/* gce-subsys = <&gce_mbox 0x1C000000 SUBSYS_1C00XXXX>, */
/* <&gce_mbox 0x1C010000 SUBSYS_1C01XXXX>, */
/* <&gce_mbox 0x1C100000 SUBSYS_1c10XXXX>, */
/* <&gce_mbox 0x1C110000 SUBSYS_1c11XXXX>; */
/* define events, see mt6885-gce.h */
gce-event-names = "disp_mutex0_eof",
"disp_mutex1_eof",
"disp_token_stream_dirty0",
"disp_wait_dsi0_te",
"disp_wait_dsi1_te",
"disp_token_stream_eof0",
"disp_dsi0_eof",
"disp_dsi1_eof",
"disp_token_esd_eof0",
"disp_rdma0_eof0",
"disp_wdma0_eof0",
"disp_token_stream_block0",
"disp_token_cabc_eof0",
"disp_wdma0_eof2",
"disp_wait_dp_intf0_te",
"disp_dp_intf0_eof",
"disp_mutex2_eof",
"disp_dpi1_eof",
"disp_dp_intf1_eof";
gce-events = <&gce_mbox_d CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>,
<&gce_mbox_d CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>,
<&gce_mbox_d CMDQ_SYNC_TOKEN_CONFIG_DIRTY>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM>,
<&gce_mbox_d CMDQ_SYNC_TOKEN_STREAM_EOF>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DSI0_FRAME_DONE>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DSI1_FRAME_DONE>,
<&gce_mbox_d CMDQ_SYNC_TOKEN_ESD_EOF>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE>,
<&gce_mbox_d CMDQ_SYNC_TOKEN_STREAM_BLOCK>,
<&gce_mbox_d CMDQ_SYNC_TOKEN_CABC_EOF>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DP_INTF0_SOF>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE>,
<&gce_mbox_d CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE>,
<&gce_mbox_d CMDQ_EVENT_VDO1_DPI1_FRAME_DONE>,
<&gce_mbox_d CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE>;
helper-name = "MTK_DRM_OPT_STAGE",
"MTK_DRM_OPT_USE_CMDQ",
"MTK_DRM_OPT_USE_M4U",
"MTK_DRM_OPT_SODI_SUPPORT",
"MTK_DRM_OPT_IDLE_MGR",
"MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE",
"MTK_DRM_OPT_IDLEMGR_BY_REPAINT",
"MTK_DRM_OPT_IDLEMGR_ENTER_ULPS",
"MTK_DRM_OPT_IDLEMGR_KEEP_LP11",
"MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING",
"MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ",
"MTK_DRM_OPT_MET_LOG",
"MTK_DRM_OPT_USE_PQ",
"MTK_DRM_OPT_ESD_CHECK_RECOVERY",
"MTK_DRM_OPT_ESD_CHECK_SWITCH",
"MTK_DRM_OPT_PRESENT_FENCE",
"MTK_DRM_OPT_RDMA_UNDERFLOW_AEE",
"MTK_DRM_OPT_DSI_UNDERRUN_AEE",
"MTK_DRM_OPT_HRT",
"MTK_DRM_OPT_HRT_MODE",
"MTK_DRM_OPT_DELAYED_TRIGGER",
"MTK_DRM_OPT_OVL_EXT_LAYER",
"MTK_DRM_OPT_AOD",
"MTK_DRM_OPT_RPO",
"MTK_DRM_OPT_DUAL_PIPE",
"MTK_DRM_OPT_DC_BY_HRT",
"MTK_DRM_OPT_OVL_WCG",
"MTK_DRM_OPT_OVL_SBCH",
"MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK",
"MTK_DRM_OPT_MET",
"MTK_DRM_OPT_REG_PARSER_RAW_DUMP",
"MTK_DRM_OPT_VP_PQ",
"MTK_DRM_OPT_GAME_PQ",
"MTK_DRM_OPT_MMPATH",
"MTK_DRM_OPT_HBM",
"MTK_DRM_OPT_LAYER_REC",
"MTK_DRM_OPT_CLEAR_LAYER",
"MTK_DRM_OPT_VDS_PATH_SWITCH";
helper-value = <0>, /*MTK_DRM_OPT_STAGE*/
<1>, /*MTK_DRM_OPT_USE_CMDQ*/
<1>, /*MTK_DRM_OPT_USE_M4U*/
<0>, /*MTK_DRM_OPT_SODI_SUPPORT*/
<1>, /*MTK_DRM_OPT_IDLE_MGR*/
<0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/
<0>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/
<0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/
<0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/
<0>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/
<1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/
<0>, /*MTK_DRM_OPT_MET_LOG*/
<1>, /*MTK_DRM_OPT_USE_PQ*/
<1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/
<1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/
<1>, /*MTK_DRM_OPT_PRESENT_FENCE*/
<0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/
<0>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/
<1>, /*MTK_DRM_OPT_HRT*/
<1>, /*MTK_DRM_OPT_HRT_MODE*/
<0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/
<1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/
<0>, /*MTK_DRM_OPT_AOD*/
<0>, /*MTK_DRM_OPT_RPO*/
<0>, /*MTK_DRM_OPT_DUAL_PIPE*/
<0>, /*MTK_DRM_OPT_DC_BY_HRT*/
<1>, /*MTK_DRM_OPT_OVL_WCG*/
<0>, /*MTK_DRM_OPT_OVL_SBCH*/
<1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/
<0>, /*MTK_DRM_OPT_MET*/
<0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/
<0>, /*MTK_DRM_OPT_VP_PQ*/
<0>, /*MTK_DRM_OPT_GAME_PQ*/
<0>, /*MTK_DRM_OPT_MMPATH*/
<0>, /*MTK_DRM_OPT_HBM*/
<0>, /*MTK_DRM_OPT_LAYER_REC*/
<1>, /*MTK_DRM_OPT_CLEAR_LAYER*/
<0>; /*MTK_DRM_OPT_VDS_PATH_SWITCH*/
};
smi_common0: smi@1c01b000 {
compatible = "mediatek,mt8195-smi-common";
mediatek,common-id = <0>;
reg = <0 0x1c01b000 0 0x1000>;
clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
<&vdosys0 CLK_VDO0_SMI_COMMON>,
<&vdosys0 CLK_VDO0_SMI_EMI>,
<&vdosys0 CLK_VDO0_SMI_GALS>;
clock-names = "apb", "smi", "gals0", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
iommu0: mm-iommu@1c01f000 {
compatible = "mediatek,mt8195-iommu-vdo";
reg = <0 0x1c01f000 0 0x1000>;
mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
&larb10 &larb11 &larb13 &larb17
&larb19 &larb21 &larb24 &larb25
&larb28>;
interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>,
<&vdosys0 CLK_VDO0_SMI_RSI>;
clock-names = "bclk", "rsi";
#iommu-cells = <1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
};
sec_iommu0: vdo_sec_iommu {
compatible = "mediatek,secure_m4u";
main-bank = <&iommu0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
};
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
#clock-cells = <1>;
};
larb2: larb@1c102000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1c102000 0 0x1000>;
mediatek,larb-id = <2>;
mediatek,smi = <&smi_common0>;
clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
<&vdosys1 CLK_VDO1_SMI_LARB2>,
<&vdosys1 CLK_VDO1_GALS>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
larb3: larb@1c103000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1c103000 0 0x1000>;
mediatek,larb-id = <3>;
mediatek,smi = <&smi_common1>;
clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
<&vdosys1 CLK_VDO1_SMI_LARB3>,
<&vdosys1 CLK_VDO1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
disp_pseudo_ovl0@1c104000 {
compatible = "mediatek,mt8195-disp-pseudo-ovl";
reg = <0 0x1c104000 0 0x1000>,
<0 0x1c105000 0 0x1000>,
<0 0x1c106000 0 0x1000>,
<0 0x1c107000 0 0x1000>,
<0 0x1c108000 0 0x1000>,
<0 0x1c109000 0 0x1000>,
<0 0x1c10A000 0 0x1000>,
<0 0x1c10B000 0 0x1000>,
<0 0x1c10C000 0 0x1000>,
<0 0x1c10D000 0 0x1000>,
<0 0x1c10E000 0 0x1000>,
<0 0x1c10F000 0 0x1000>;
reg-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1","vdo1_mdp_rdma2",
"vdo1_mdp_rdma3","vdo1_mdp_rdma4",
"vdo1_mdp_rdma5","vdo1_mdp_rdma6",
"vdo1_mdp_rdma7","vdo1_merge0",
"vdo1_merge1","vdo1_merge2","vdo1_merge3";
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>,
<&vdosys1 CLK_VDO1_MDP_RDMA1>,
<&vdosys1 CLK_VDO1_MDP_RDMA2>,
<&vdosys1 CLK_VDO1_MDP_RDMA3>,
<&vdosys1 CLK_VDO1_MDP_RDMA4>,
<&vdosys1 CLK_VDO1_MDP_RDMA5>,
<&vdosys1 CLK_VDO1_MDP_RDMA6>,
<&vdosys1 CLK_VDO1_MDP_RDMA7>,
<&vdosys1 CLK_VDO1_VPP_MERGE0>,
<&vdosys1 CLK_VDO1_VPP_MERGE1>,
<&vdosys1 CLK_VDO1_VPP_MERGE2>,
<&vdosys1 CLK_VDO1_VPP_MERGE3>,
<&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>,
<&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>,
<&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>,
<&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
clock-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1",
"vdo1_mdp_rdma2","vdo1_mdp_rdma3",
"vdo1_mdp_rdma4","vdo1_mdp_rdma5",
"vdo1_mdp_rdma6","vdo1_mdp_rdma7",
"vdo1_merge0","vdo1_merge1",
"vdo1_merge2","vdo1_merge3",
"vdo1_merge0_async","vdo1_merge1_async",
"vdo1_merge2_async","vdo1_merge3_async";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA1)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA2)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA3)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA4)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA5)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA6)
&mmqos SLAVE_COMMON(0)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA7)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"mdp_rdma0",
"mdp_rdma1",
"mdp_rdma2",
"mdp_rdma3",
"mdp_rdma4",
"mdp_rdma5",
"mdp_rdma6",
"mdp_rdma7";
mediatek,larb = <&larb2>;
mediatek,smi-id = <0>;
iommus = <&iommu0 M4U_PORT_L2_MDP_RDMA0>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma0*/
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma1*/
<GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma2*/
<GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma3*/
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma4*/
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma5*/
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma6*/
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma7*/
<GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>, /*merge0*/
<GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>, /*merge1*/
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>, /*merge2*/
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; /*merge3*/
};
disp_merge5: disp_vpp_merge5@1c110000 {
compatible = "mediatek,mt8195-disp-merge";
reg = <0 0x1c110000 0 0x1000>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
clock-names = "merge5","merge5_async";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
disp_dpi0: disp_dpi0@1c111000 {
compatible = "mediatek,mt8195-dpi";
reg = <0 0x1c111000 0 0x1000>;
interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
disp_dpi1: disp_dpi1@1c112000 {
compatible = "mediatek,mt8195-dpi";
reg = <0 0x1c112000 0 0x1000>;
mediatek,vdosys1-dpi = <&vdosys1 0x0>;
interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&vdosys1 CLK_VDO1_DPI1>,
<&vdosys1 CLK_VDO1_DPI1_MM>;
clock-names = "pixel", "engine";
status = "disabled";
};
dp_intf1: dp_intf1@1c113000 {
compatible = "mediatek,mt8195-dp_intf", "mediatek,mt8188-dp_intf";
reg = <0 0x1c113000 0 0x1000>;
interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
<&vdosys1 CLK_VDO1_DPINTF>,
<&topckgen CLK_TOP_DP_SEL>,
<&topckgen CLK_TOP_TVDPLL2_D2>,
<&topckgen CLK_TOP_TVDPLL2_D4>,
<&topckgen CLK_TOP_TVDPLL2_D8>,
<&topckgen CLK_TOP_TVDPLL2_D16>,
<&topckgen CLK_TOP_TVDPLL2>;
clock-names = "engine",
"ck_cg",
"pixel",
"TVDPLL_D2",
"TVDPLL_D4",
"TVDPLL_D8",
"TVDPLL_D16",
"pll";
status = "disabled";
};
disp_ethdr@1c114000 {
compatible = "mediatek,mt8195-disp-ethdr";
reg = <0 0x1c114000 0 0x1000>,
<0 0x1c115000 0 0x1000>,
<0 0x1c117000 0 0x1000>,
<0 0x1c119000 0 0x1000>,
<0 0x1c11A000 0 0x1000>,
<0 0x1c11B000 0 0x1000>,
<0 0x1c11C000 0 0x1000>;
reg-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
"hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
"hdr_adl_ds";
clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
<&vdosys1 CLK_VDO1_26M_SLOW>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>;
clock-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
"hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
"hdr_adl_ds","hdr_vdo_fe0_async",
"hdr_vdo_fe1_async","hdr_gfx_fe0_async",
"hdr_gfx_fe1_async","hdr_vdo_be_async";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
mediatek,larb = <&larb3>;
mediatek,smi-id = <1>;
iommus = <&iommu1 M4U_PORT_L3_HDR_DS>,
<&iommu1 M4U_PORT_L3_HDR_ADL>;
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*disp mixer*/
};
hdmi0: hdmi@1c300000 {
compatible = "mediatek,mt8195-hdmi";
reg = <0 0x1c300000 0 0x1000>;
power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D4>,
<&topckgen CLK_TOP_MSDCPLL_D2>,
<&topckgen CLK_TOP_HDMI_APB_SEL>,
<&topckgen CLK_TOP_UNIVPLL_D4_D8>,
<&topckgen CLK_TOP_HDCP_SEL>,
<&topckgen CLK_TOP_HDCP_24M_SEL>,
<&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
clock-names = "univpll_d6_d4",
"msdcpll_d2",
"hdmi_apb_sel",
"univpll_d4_d8",
"hdcp_sel",
"hdcp24_sel",
"split_hdmi";
interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pin>;
phys = <&hdmi_phy>;
phy-names = "hdmi";
cec = <&cec>;
ddc-i2c-bus = <&hdmiddc0>;
status = "disabled";
};
hdmirx0: hdmirx@1c400000 {
compatible = "mediatek,mt8195-hdmirx";
nvmem-cells = <&hdmirx_efuse &hdmirx_rterm>;
nvmem-cell-names = "phy-hdmirx","phy-rterm";
power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_RX>;
clocks = <&topckgen CLK_TOP_HDMI_APB_SEL>,
<&topckgen CLK_TOP_MSDCPLL_D2>,
<&topckgen CLK_TOP_HD20_HDCP_C_SEL>,
<&topckgen CLK_TOP_MSDCPLL_D4>,
<&topckgen CLK_TOP_HDMI_XTAL_SEL>;
clock-names = "hdmiclksel",
"hdmiclk208m",
"hdcpclksel",
"hdcpclk104m",
"hdmisel";
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
reg = <0 0x1c400000 0 0x1000>, /* rx */
<0 0x1c300000 0 0x1000>, /* tx */
<0 0x11d5f000 0 0x1000>, /* vdout */
<0 0x11d60000 0 0x3000>, /* phy */
<0 0x10014800 0 0x0400>, /* scdc */
<0 0x10014400 0 0x0400>, /* edid */
<0 0x1000c000 0 0x1000>, /* apmixedsys */
<0 0x10000000 0 0x1000>, /* topckgen */
<0 0x10007000 0 0x1000>; /* toprgu */
interrupts = <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
edp_tx: edp_tx@1c500000 {
compatible = "mediatek,mt8195-edp-tx";
reg = <0 0x1c500000 0 0x8000>;
nvmem-cells = <&edp_calibration>;
nvmem-cell-names = "edp_calibration_data";
power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
panel1: panel@1 {
compatible = "panel-edp";
status = "disabled";
};
dp_tx: dp_tx@1c600000 {
compatible = "mediatek,mt8195-dp-tx";
reg = <0 0x1c600000 0 0x8000>;
nvmem-cells = <&dp_calibration>;
nvmem-cell-names = "dp_calibration_data";
power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
aliases {
ovl0 = &disp_ovl0;
ovl1 = &disp_ovl1;
wdma0 = &disp_wdma0;
wdma1 = &disp_wdma1;
rdma0 = &disp_rdma0;
rdma1 = &disp_rdma1;
color0 = &disp_color0;
color1 = &disp_color1;
ccorr0 = &disp_ccorr0;
ccorr1 = &disp_ccorr1;
aal0 = &disp_aal0;
aal1 = &disp_aal1;
gamma0 = &disp_gamma0;
gamma1 = &disp_gamma1;
dither0 = &disp_dither0;
dither1 = &disp_dither1;
dsi0 = &disp_dsi0;
dsi1 = &disp_dsi1;
merge0 = &disp_merge0;
merge5 = &disp_merge5;
dpi0 = &disp_dpi0;
dpi1 = &disp_dpi1;
dp_intf0 = &dp_intf0;
dp_intf1 = &dp_intf1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
mmc0 = &mmc0;
mmc1 = &mmc1;
};
apuspm: apusys-power-controller {
compatible = "mediatek,apusys-power-controller";
mediatek,scpsys = <&scpsys>;
mediatek,apu_rpc = <&apu_top>;
mediatek,apu_conn = <&apu_conn>;
mediatek,apu_conn1 = <&apu_conn1>;
mediatek,apu_vcore = <&apu_vcore>;
mediatek,apu_acc = <&apu_acc>;
mediatek,apu_ao_ctrl = <&apu_ao_ctrl>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domain of the APUSYS */
apusys_top@MT8195_POWER_DOMAIN_APUSYS_TOP {
reg = <MT8195_POWER_DOMAIN_APUSYS_TOP>;
#power-domain-cells = <0>;
clocks = <&apusys_pll CLK_APUSYS_PLL_APUPLL>,
<&apusys_pll CLK_APUSYS_PLL_NPUPLL>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL1>,
<&apusys_pll CLK_APUSYS_PLL_APUPLL2>;
clock-names = "clk_apupll_apupll",
"clk_apupll_npupll",
"clk_apupll_apupll1",
"clk_apupll_apupll2";
};
apusys_vpu0@MT8195_POWER_DOMAIN_APUSYS_VPU0 {
reg = <MT8195_POWER_DOMAIN_APUSYS_VPU0>;
#power-domain-cells = <0>;
};
apusys_vpu1@MT8195_POWER_DOMAIN_APUSYS_VPU1 {
reg = <MT8195_POWER_DOMAIN_APUSYS_VPU1>;
power-domain-cells = <0>;
};
apusys_dla0@MT8195_POWER_DOMAIN_APUSYS_MDLA0 {
reg = <MT8195_POWER_DOMAIN_APUSYS_MDLA0>;
#power-domain-cells = <0>;
};
apusys_dla1@MT8195_POWER_DOMAIN_APUSYS_MDLA1 {
reg = <MT8195_POWER_DOMAIN_APUSYS_MDLA1>;
#power-domain-cells = <0>;
};
};
atf_logger {
compatible = "mediatek,atf_logger";
};
/*
* dsu ecc irq (nFAULTIRQ[0]) must be at the end of
* the list, due to we shouldn't force set affinity
* in the driver.
*/
cache_parity {
compatible = "mediatek,cache_parity";
version = <2>;
err_level = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
};
chosen: chosen {
bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram androidboot.hardware=mt8195 earlycon=uart8250,mmio32,0x11001100 8250.nr_uarts=4 vmalloc=496M swiotlb=noforce firmware_class.path=/vendor/firmware page_owner=on cgroup.memory=nosocket,nokmem maxcpus=8 loop.max_part=7";
kaslr-seed = <0 0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@000 {
device_type = "cpu";
compatible = "arm,cortex-a55", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
#cooling-cells = <2>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55", "arm,armv8";
reg = <0x100>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
#cooling-cells = <2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55", "arm,armv8";
reg = <0x200>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
#cooling-cells = <2>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55", "arm,armv8";
reg = <0x300>;
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
#cooling-cells = <2>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a78", "arm,armv8";
reg = <0x400>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
#cooling-cells = <2>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a78", "arm,armv8";
reg = <0x500>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
#cooling-cells = <2>;
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a78", "arm,armv8";
reg = <0x600>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
#cooling-cells = <2>;
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a78", "arm,armv8";
reg = <0x700>;
enable-method = "psci";
performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
idle-states {
entry-method = "arm,psci";
cpuoff_l: cpuoff_l {
compatible = "mediatek,idle-state", "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <95>;
min-residency-us = <580>;
};
cpuoff_b: cpuoff_b {
compatible = "mediatek,idle-state", "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
entry-latency-us = <45>;
exit-latency-us = <140>;
min-residency-us = <740>;
};
clusteroff_l: clusteroff_l {
compatible = "mediatek,idle-state", "arm,idle-state";
arm,psci-suspend-param = <0x01010002>;
local-timer-stop;
entry-latency-us = <55>;
exit-latency-us = <155>;
min-residency-us = <840>;
};
clusteroff_b: clusteroff_b {
compatible = "mediatek,idle-state", "arm,idle-state";
arm,psci-suspend-param = <0x01010002>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <200>;
min-residency-us = <1000>;
};
mcusysoff: mcusysoff {
compatible = "mediatek,idle-state", "arm,idle-state";
arm,psci-suspend-param = <0x02010003>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2600>;
};
};
};
clocks {
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
};
cmdq-bw-mon {
compatible = "mediatek,cmdq-bw-mon";
mboxes = <&gce_mbox_d 22 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
smi_mon = <&smi_common1>, <&smi_common2>;
bw_mon_gpr = /bits/ 8 <GCE_GPR_R13>;
};
cmdq_test: cmdq_test {
compatible = "mediatek,cmdq-test";
mediatek,gce = <&gce_mbox>;
mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
mboxes = <&gce_mbox 23 0 CMDQ_THR_PRIO_1>,
<&gce_mbox_d 23 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
};
consys_reset: consys_reset {
compatible = "mediatek,consys-reset";
};
dfd {
compatible = "mediatek,dfd";
mediatek,enabled = <1>;
mediatek,chain_length = <0xbe29>;
mediatek,rg_dfd_timeout = <0xc8>;
mediatek,check_dfd_support = <1>;
mediatek,dfd_infra_base = <0x390>;
mediatek,dfd_latch_offset = <0x48>;
};
disp_pseudo_ovl_l2 {
compatible = "mediatek,mt8195-pseudo-ovl-larb";
mediatek,larb-id = <2>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu0 M4U_PORT_L2_MDP_RDMA0>,
<&iommu0 M4U_PORT_L2_MDP_RDMA2>,
<&iommu0 M4U_PORT_L2_MDP_RDMA4>,
<&iommu0 M4U_PORT_L2_MDP_RDMA6>;
};
disp_pseudo_ovl_l3 {
compatible = "mediatek,mt8195-pseudo-ovl-larb";
mediatek,larb-id = <3>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu1 M4U_PORT_L3_MDP_RDMA1>,
<&iommu1 M4U_PORT_L3_MDP_RDMA3>,
<&iommu1 M4U_PORT_L3_MDP_RDMA5>,
<&iommu1 M4U_PORT_L3_MDP_RDMA7>;
};
dram_ctrl {
compatible = "mediatek,dram-qosctrl";
required-opps = <&dvfsrc_freq_opp0>,
<&dvfsrc_freq_opp1>;
};
dsu-pmu {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
edma: edma {
compatible = "mtk,edma";
sub_nr = <2>;
mediatek,edma-sub = <&edma0>, <&edma1>;
};
emiisu {
compatible = "mediatek,mt8195-emiisu",
"mediatek,common-emiisu";
ctrl_intf = <0>;
};
firmware: firmware {
android: android {
compatible = "android,firmware";
fstab: fstab {
compatible = "android,fstab";
};
};
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
ged: ged {
compatible = "mediatek,ged";
gpufreq-supply = <&gpufreq>;
};
gpio_key: gpio_key {
compatible = "gpio-keys";
};
gpufreq: gpufreq {
compatible = "mediatek,gpufreq";
nvmem-cells = <&gpu_segment_table>;
nvmem-cell-names = "segment_table";
clocks =
<&topckgen CLK_TOP_MFG_FAST_SEL>,
<&apmixedsys CLK_APMIXED_MFGPLL>,
<&topckgen CLK_TOP_MFGPLL_OPP>,
<&topckgen CLK_TOP_MFG_SEL>,
<&mfgcfg CLK_MFG_BG3D>;
clock-names =
"clk_mux", /* switch main/sub */
"clk_pll_src",
"clk_main_parent", /* main pll freq */
"clk_sub_parent", /* default 356.5 MHz */
"subsys_bg3d";
power-domains =
<&spm MT8195_POWER_DOMAIN_MFG2>,
<&spm MT8195_POWER_DOMAIN_MFG3>,
<&spm MT8195_POWER_DOMAIN_MFG4>,
<&spm MT8195_POWER_DOMAIN_MFG5>,
<&spm MT8195_POWER_DOMAIN_MFG6>;
};
gpu_mali_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <880000000>;
opp-microvolt = <750000>;
};
opp01 {
opp-hz = /bits/ 64 <850000000>;
opp-microvolt = <737500>;
};
opp02 {
opp-hz = /bits/ 64 <820000000>;
opp-microvolt = <725000>;
};
opp03 {
opp-hz = /bits/ 64 <790000000>;
opp-microvolt = <712500>;
};
opp04 {
opp-hz = /bits/ 64 <760000000>;
opp-microvolt = <700000>;
};
opp05 {
opp-hz = /bits/ 64 <730000000>;
opp-microvolt = <687500>;
};
opp06 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <675000>;
};
opp07 {
opp-hz = /bits/ 64 <670000000>;
opp-microvolt = <662500>;
};
opp08 {
opp-hz = /bits/ 64 <640000000>;
opp-microvolt = <650000>;
};
opp09 {
opp-hz = /bits/ 64 <598000000>;
opp-microvolt = <637500>;
};
opp10 {
opp-hz = /bits/ 64 <556000000>;
opp-microvolt = <625000>;
};
opp11 {
opp-hz = /bits/ 64 <515000000>;
opp-microvolt = <612500>;
};
opp12 {
opp-hz = /bits/ 64 <473000000>;
opp-microvolt = <600000>;
};
opp13 {
opp-hz = /bits/ 64 <431000000>;
opp-microvolt = <587500>;
};
opp14 {
opp-hz = /bits/ 64 <410000000>;
opp-microvolt = <581250>;
};
opp15 {
opp-hz = /bits/ 64 <390000000>;
opp-microvolt = <575000>;
};
};
hcp: hcp@0 {
compatible = "mediatek,hcp";
ion-supply = <&ion>;
iommus = <&iommu0 M4U_PORT_L9_IMG_IMGI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_IMGBI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_IMGCI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TNCSTI_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TNCSTI_T4_A>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TIMGO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T2_A>,
<&iommu0 M4U_PORT_L9_IMG_IMGI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_IMGBI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_IMGCI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T5_A>,
<&iommu0 M4U_PORT_L9_IMG_SMTI_T1_B>,
<&iommu0 M4U_PORT_L9_IMG_TNCSO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_TNCSTO_T1_A>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T2_B>,
<&iommu0 M4U_PORT_L9_IMG_YUVO_T5_B>,
<&iommu0 M4U_PORT_L9_IMG_SMTO_T1_B>,
<&iommu0 M4U_PORT_L10_IMG_IMGI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMGCI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_DEPI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_DMGI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_VIPI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_TNRWI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_RECI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_SMTI_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_SMTI_D6_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGI_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGBI_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGCI_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_PIMGI_P1_B>,
<&iommu0 M4U_PORT_L10_IMG_PIMGBI_P1_B>,
<&iommu0 M4U_PORT_L10_IMG_PIMGCI_P1_B>,
<&iommu0 M4U_PORT_L10_IMG_IMG3O_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMG4O_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMG3CO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_FEO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_IMG2O_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_TNRWO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_SMTO_D1_A>,
<&iommu0 M4U_PORT_L10_IMG_WROT_P1_A>,
<&iommu0 M4U_PORT_L10_IMG_WROT_P1_B>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_CQ0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_EIS_CQ1_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_CQ0_A>,
<&iommu0 M4U_PORT_L11_IMG_WPE_TNR_CQ1_A>;
};
hdmiddc0: ddc_i2c {
compatible = "mediatek,mt8195-hdmi-ddc";
clocks = <&clk26m>;
clock-names = "ddc-i2c";
};
ice: ice_debug {
compatible = "mediatek,mt8195-ice_debug", "mediatek,mt2701-ice_debug";
clocks = <&infracfg_ao CLK_INFRA_AO_DEBUGSYS>;
clock-names = "ice_dbg";
};
ion: ion {
compatible = "mediatek,ion";
iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
};
ircut: ircut {
compatible = "mediatek,icr";
};
leakage {
compatible = "mediatek,mtk-static-power";
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
domain = "LL", "L", "MCU", "GPU", "VCORE", "VPU","VSRAM_PROC12",
"VSRAM_PROC11", "VSRAM_OTHERS", "MDLA", "VSRAM_GPU",
"VSRAM_VPU_MDLA", "VCORE_OFF";
LL = <0x0224 0xff 900 30 4 0>;
L = <0x0224 0xff00 900 30 4 0>;
MCU = <0x0220 0xff000000 900 30 1 0>;
GPU = <0x021c 0xff000000 800 30 1 0>;
VCORE = <0x021c 0xff0000 750 30 1 0>;
VPU = <0x0220 0xff00 775 30 1 0>;
MDLA = <0x0220 0xff 800 30 1 0>;
VSRAM_PROC12 = <0x0228 0xff000000 900 30 1 0>;
VSRAM_PROC11 = <0x0228 0xff0000 900 30 1 0>;
VSRAM_OTHERS = <0x0224 0xff000000 750 30 1 0>;
VSRAM_GPU = <0x0228 0xff00 800 30 1 0>;
VSRAM_VPU_MDLA = <0x0228 0xff 850 30 1 0>;
VCORE_OFF = <0x0224 0xff0000 550 30 1 0>;
};
mdp_larb4 {
compatible = "mediatek,mdp-larb";
mediatek,larb-id = <4>;
iommus = <&iommu1 M4U_PORT_L4_MDP_RDMA>,
<&iommu1 M4U_PORT_L4_MDP_WROT>;
dma_mask_bit = <34>;
};
mdp_larb5 {
compatible = "mediatek,mdp-larb";
mediatek,larb-id = <5>;
iommus = <&iommu0 M4U_PORT_L5_SVPP1_MDP_RDMA>,
<&iommu0 M4U_PORT_L5_SVPP2_MDP_RDMA>,
<&iommu0 M4U_PORT_L5_SVPP1_MDP_WROT>,
<&iommu0 M4U_PORT_L5_SVPP2_MDP_WROT>;
dma_mask_bit = <34>;
};
mdp_larb6 {
compatible = "mediatek,mdp-larb";
mediatek,larb-id = <6>;
iommus = <&iommu1 M4U_PORT_L6_SVPP3_MDP_RDMA>,
<&iommu1 M4U_PORT_L6_SVPP3_MDP_WROT>;
dma_mask_bit = <34>;
};
memory {
device_type = "memory";
reg = <0 0x40000000 0 0x3e605000>;
};
memory_ssmr_features: memory-ssmr-features {
compatible = "mediatek,memory-ssmr-features";
svp-size = <0 0x10000000>;
prot-sharedmem-size = <0 0x8000000>;
};
mmdvfs {
compatible = "mediatek,mmdvfs";
operating-points-v2 = <&opp_table_vdo>;
mediatek,support-mux = "vdo", "cam",
"img", "warp", "ethdr",
"ipe","venc", "vdec",
"vpp", "ccu";
mediatek,mux-vdo = "TOP_MAINPLL_D5_D2",
"TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_TVDPLL1_CK";
mediatek,mux-cam = "TOP_MAINPLL_D4_D2",
"TOP_MMPLL_D7", "TOP_UNIVPLL_D6",
"TOP_UNIVPLL_D5";
mediatek,mux-img = "TOP_UNIVPLL_D5_D2",
"TOP_MMPLL_D4_D2", "TOP_MMPLL_D6",
"TOP_IMGPLL_CK";
mediatek,mux-warp = "TOP_MAINPLL_D4_D2",
"TOP_MAINPLL_D6", "TOP_MAINPLL_D5",
"TOP_UNIVPLL_D4";
mediatek,mux-ethdr = "TOP_MMPLL_D5_D4",
"TOP_UNIVPLL_D6_D2", "TOP_MMPLL_D7",
"TOP_UNIVPLL_D6";
mediatek,mux-ipe = "TOP_MAINPLL_D4_D2",
"TOP_MAINPLL_D6", "TOP_MMPLL_D6",
"TOP_MAINPLL_D4";
mediatek,mux-venc = "TOP_UNIVPLL_D5_D2",
"TOP_MMPLL_D4_D2", "TOP_MMPLL_D6",
"TOP_UNIVPLL_D4";
mediatek,mux-vdec = "TOP_MAINPLL_D5_D2",
"TOP_UNIVPLL_D4_D2", "TOP_MMPLL_D6",
"TOP_VDECPLL_CK";
mediatek,mux-vpp = "TOP_MAINPLL_D5_D2",
"TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6",
"TOP_TVDPLL1_CK";
mediatek,mux-ccu = "TOP_MAINPLL_D4_D2",
"TOP_UNIVPLL_D7", "TOP_UNIVPLL_D6",
"TOP_UNIVPLL_D6";
dvfsrc-vcore-supply = <&dvfsrc_vcore>;
mediatek,action = <1>;
clocks = <&topckgen CLK_TOP_VPP_SEL>, /* 0 */
<&topckgen CLK_TOP_CAM_SEL>, /* 1 */
<&topckgen CLK_TOP_IMG_SEL>, /* 2 */
<&topckgen CLK_TOP_WPE_VPP_SEL>, /* 3 */
<&topckgen CLK_TOP_ETHDR_SEL>, /* 4 */
<&topckgen CLK_TOP_IPE_SEL>, /* 5 */
<&topckgen CLK_TOP_VENC_SEL>, /* 6 */
<&topckgen CLK_TOP_VDEC_SEL>, /* 7 */
<&topckgen CLK_TOP_VPP_SEL>, /* 8 */
<&topckgen CLK_TOP_CCU_SEL>, /* 9 */
<&topckgen CLK_TOP_MAINPLL_D5_D2>, /* 10 */
<&topckgen CLK_TOP_UNIVPLL_D4_D2>, /* 11 */
<&topckgen CLK_TOP_UNIVPLL_D6>, /* 12 */
<&topckgen CLK_TOP_TVDPLL1>, /* 13 */
<&topckgen CLK_TOP_MAINPLL_D4_D2>, /* 14 */
<&topckgen CLK_TOP_MMPLL_D7>, /* 15 */
<&topckgen CLK_TOP_UNIVPLL_D5>, /* 16 */
<&topckgen CLK_TOP_UNIVPLL_D5_D2>, /* 17 */
<&topckgen CLK_TOP_MMPLL_D4_D2>, /* 18 */
<&topckgen CLK_TOP_MMPLL_D6>, /* 19 */
<&topckgen CLK_TOP_IMGPLL>, /* 20 */
<&topckgen CLK_TOP_MAINPLL_D6>, /* 21 */
<&topckgen CLK_TOP_MAINPLL_D5>, /* 22 */
<&topckgen CLK_TOP_UNIVPLL_D4>, /* 23 */
<&topckgen CLK_TOP_MMPLL_D5_D4>, /* 24 */
<&topckgen CLK_TOP_UNIVPLL_D6_D2>, /* 25 */
<&topckgen CLK_TOP_MAINPLL_D4>, /* 26 */
<&topckgen CLK_TOP_VDECPLL>, /* 27 */
<&topckgen CLK_TOP_UNIVPLL_D7>, /* 28 */
<&apmixedsys CLK_APMIXED_MMPLL>;
clock-names = "vdo", /* 0 */
"cam", /* 1 */
"img", /* 2 */
"warp", /* 3 */
"ethdr", /* 4 */
"ipe", /* 5 */
"venc", /* 6 */
"vdec", /* 7 */
"vpp", /* 8 */
"ccu", /* 9 */
"TOP_MAINPLL_D5_D2", /* 10 */
"TOP_UNIVPLL_D4_D2", /* 11 */
"TOP_UNIVPLL_D6", /* 12 */
"TOP_TVDPLL1_CK", /* 13 */
"TOP_MAINPLL_D4_D2", /* 14 */
"TOP_MMPLL_D7", /* 15 */
"TOP_UNIVPLL_D5", /* 16 */
"TOP_UNIVPLL_D5_D2", /* 17 */
"TOP_MMPLL_D4_D2", /* 18 */
"TOP_MMPLL_D6", /* 19 */
"TOP_IMGPLL_CK", /* 20 */
"TOP_MAINPLL_D6", /* 21 */
"TOP_MAINPLL_D5", /* 22 */
"TOP_UNIVPLL_D4", /* 23 */
"TOP_MMPLL_D5_D4", /* 24 */
"TOP_UNIVPLL_D6_D2", /* 25 */
"TOP_MAINPLL_D4", /* 26 */
"TOP_VDECPLL_CK", /* 27 */
"TOP_UNIVPLL_D7", /* 28 */
"clk_mmpll_ck";
};
mmqos: interconnect {
compatible = "mediatek,mt8195-mmqos";
#interconnect-cells = <1>;
mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4
&larb5 &larb6 &larb7 &larb8 &larb9 &larb10 &larb11
&larb12 &larb13 &larb14 &larb16 &larb17
&larb18 &larb19 &larb20 &larb21 &larb22
&larb23 &larb24 &larb25 &larb26 &larb27
&larb28>;
mediatek,commons = <&smi_common0>, <&smi_common1>;
clocks = <&topckgen CLK_TOP_VPP_SEL>;
clock-names = "mm";
interconnects = <&ddr_emi MT8195_MASTER_MMSYS
&ddr_emi MT8195_SLAVE_DDR_EMI>,
<&ddr_emi MT8195_MASTER_HRT_MMSYS
&ddr_emi MT8195_SLAVE_HRT_DDR_EMI>;
interconnect-names = "icc-bw", "icc-hrt-bw";
};
mtee {
compatible = "mediatek,mtee";
};
mtk_composite_v4l2_2: mtk_composite_v4l2_2 {
compatible = "mediatek,mtk_composite_v4l2_2";
};
mtkfb: mtkfb {
compatible = "mediatek,mtkfb";
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,priority = <0x0>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <3>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x0>;
};
queue1 {
snps,weight = <0x11>;
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue2 {
snps,weight = <0x12>;
snps,dcb-algorithm;
snps,priority = <0x2>;
};
};
odm: odm {
compatible = "simple-bus";
/* reserved for overlay by odm */
};
opp_table_cam: opp-table-cam {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <273000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <392000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <499000000>;
opp-microvolt = <750000>;
};
};
opp_table_ccu: opp-table-ccu {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <273000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <356000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <750000>;
};
};
opp_table_ethdr: opp-table-ethdr {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <137000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <208000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <392000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <750000>;
};
};
opp_table_img: opp-table-img {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <249000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <343000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <458000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <750000>;
};
};
opp_table_ipe: opp-table-ipe {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <273000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <364000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <458000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <546000000>;
opp-microvolt = <750000>;
};
};
opp_table_vdec: opp-table-vdec {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <218000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <458000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <680000000>;
opp-microvolt = <750000>;
};
};
opp_table_vdo: opp-table-vdo {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <218000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <594000000>;
opp-microvolt = <750000>;
};
};
opp_table_venc: opp-table-venc {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <343000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <458000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <750000>;
};
};
opp_table_vpp: opp-table-vpp {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <218000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <416000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <594000000>;
opp-microvolt = <750000>;
};
};
opp_table_warp: opp-table-warp {
compatible = "operating-points-v2";
opp-0 {
opp-hz = /bits/ 64 <273000000>;
opp-microvolt = <550000>;
};
opp-1 {
opp-hz = /bits/ 64 <364000000>;
opp-microvolt = <600000>;
};
opp-2 {
opp-hz = /bits/ 64 <436000000>;
opp-microvolt = <650000>;
};
opp-3 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <750000>;
};
};
pda2: pda2 {
compatible = "mediatek,camera-pda2";
iommus = <&iommu1 M4U_PORT_L14_CAM_PDAI_1>,
<&iommu1 M4U_PORT_L14_CAM_PDAO>;
};
pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
compatible = "mediatek,pmic_clock_buffer";
mediatek,clkbuf-quantity = <7>;
mediatek,clkbuf-config = <2 1 1 2 0 0 1>;
mediatek,clkbuf-output-impedance = <6 4 6 4 0 0 6>;
mediatek,clkbuf-controls-for-desense = <0 4 0 4 0 0 0>;
mediatek,clkbuf-driving-current = <1 1 1 1 1 1 1>;
mediatek,bblpm-support = "enable";
pwrap-dcxo-en = <0x190 0 0x190 1 0x190 0>;
pwrap-dcxo-cfg = <0x194 0x1A4>;
spm-pwr-status = <0x160 0 0x160 1>;
pwrap = <&pwrap>;
sleep = <&sleep>;
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
};
pmu-a78 {
compatible = "arm,cortex-a78-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
pwmleds: pwmleds {
compatible = "mediatek,pwm-leds";
status = "disabled";
backlight {
label = "lcd-backlight";
pwms = <&disp_pwm0 0 500000>;
max-brightness = <255>;
pwm-names = "lcd-backlight";
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
reserve-memory-mcupm_share {
compatible = "mediatek,reserve-memory-mcupm_share";
no-map;
status = "okay";
size = <0 0x610000>; /* 6M + 64K */
alignment = <0 0x10000>;
alloc-ranges = <0 0x40000000 0 0x60000000>;
};
imgsys-reserve-memory {
compatible = "mediatek,imgsys-reserve-memory";
no-map;
size = <0 0xa560000>;
alignment = <0 0x1000000>;
alloc-ranges = <0 0x40000000 0 0x80000000>;
};
adsp_mem_reserved: adsp_mem_region {
compatible = "mediatek,adsp-reserved-memory";
no-map;
reg = <0 0x50000000 0 0x1a00000>;
};
reserve-memory-sspm_share {
compatible = "mediatek,reserve-memory-sspm_share";
no-map;
status = "okay";
size = <0 0x910000>; /* 9M + 64K */
alignment = <0 0x10000>;
alloc-ranges = <0 0x40000000 0 0x60000000>;
};
reserve-memory-scp_share {
compatible = "mediatek,reserve-memory-scp_share";
no-map;
size = <0 0x00300000>; /*3 MB share mem size */
alignment = <0 0x1000000>;
alloc-ranges = <0 0x50000000 0 0x40000000>;
};
ssmr_cma_mem: ssmr-reserved-cma_memory {
compatible = "shared-dma-pool";
reusable;
size = <0 0x10000000>;
alignment = <0 0x1000000>;
alloc-range = <0 0x80000000 2 0x40000000>;
};
};
sound: sound {
compatible = "mediatek,mt8195-sound";
mediatek,platform = <&afe>;
mediatek,adsp-platform = <&adsp_pcm>;
status = "disabled";
};
ssmr {
compatible = "mediatek,trusted_mem";
memory-region = <&ssmr_cma_mem>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
snps,rd_osr_lmt = <0x7>;
snps,blen = <0 0 0 0 16 8 4>;
};
thermal_zones: thermal-zones {
soc_max {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <1000>; /* milliseconds */
thermal-sensors = <&lvts 0>;
sustainable-power = <1500>;
trips {
threshold: trip-point@0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: target@1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_max_crit: soc_max_crit@0 {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map2 {
trip = <&target>;
cooling-device = <&vpu_core0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&vpu_core1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map3 {
trip = <&target>;
cooling-device = <&mtk_mdla
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
cpu_big1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 1>;
};
cpu_big2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 2>;
};
cpu_big3 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 3>;
};
cpu_big4 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 4>;
};
cpu_little1{
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 5>;
};
cpu_little2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 6>;
};
cpu_little3 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 7>;
};
cpu_little4 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 8>;
};
vpu1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 9>;
};
vpu2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 10>;
};
gpu1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 11>;
};
gpu2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 12>;
};
vdec {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 13>;
};
img {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 14>;
};
infra {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 15>;
};
cam1 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 16>;
};
cam2 {
polling-delay = <0>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&lvts 17>;
};
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clock-frequency = <13000000>;
};
typec_mux_switch: typec_mux_switch {
compatible = "mediatek,typec_mux_switch";
status = "okay";
};
venc_l19 {
compatible = "mediatek,mt8195-venc-larb";
mediatek,larb-id = <19>;
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
iommus = <&iommu0 M4U_PORT_L19_VENC_RCPU>,
<&iommu0 M4U_PORT_L19_VENC_REC>,
<&iommu0 M4U_PORT_L19_VENC_BSDMA>,
<&iommu0 M4U_PORT_L19_VENC_SV_COMV>,
<&iommu0 M4U_PORT_L19_VENC_RD_COMV>,
<&iommu0 M4U_PORT_L19_VENC_NBM_RDMA>,
<&iommu0 M4U_PORT_L19_VENC_NBM_RDMA_LITE>,
<&iommu0 M4U_PORT_L19_VENC_SUB_W_LUMA>,
<&iommu0 M4U_PORT_L19_VENC_FCS_NBM_RDMA>,
<&iommu0 M4U_PORT_L19_VENC_NBM_WDMA>,
<&iommu0 M4U_PORT_L19_VENC_NBM_WDMA_LITE>,
<&iommu0 M4U_PORT_L19_VENC_FCS_NBM_WDMA>,
<&iommu0 M4U_PORT_L19_VENC_CUR_LUMA>,
<&iommu0 M4U_PORT_L19_VENC_CUR_CHROMA>,
<&iommu0 M4U_PORT_L19_VENC_REF_LUMA>,
<&iommu0 M4U_PORT_L19_VENC_REF_CHROMA>,
<&iommu0 M4U_PORT_L19_VENC_SUB_R_CHROMA>;
};
venc_l20 {
compatible = "mediatek,mt8195-venc-larb";
mediatek,larb-id = <20>;
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
iommus = <&iommu1 M4U_PORT_L20_VENC_RCPU>,
<&iommu1 M4U_PORT_L20_VENC_REC>,
<&iommu1 M4U_PORT_L20_VENC_BSDMA>,
<&iommu1 M4U_PORT_L20_VENC_SV_COMV>,
<&iommu1 M4U_PORT_L20_VENC_RD_COMV>,
<&iommu1 M4U_PORT_L20_VENC_NBM_RDMA>,
<&iommu1 M4U_PORT_L20_VENC_NBM_RDMA_LITE>,
<&iommu1 M4U_PORT_L20_VENC_SUB_W_LUMA>,
<&iommu1 M4U_PORT_L20_VENC_FCS_NBM_RDMA>,
<&iommu1 M4U_PORT_L20_VENC_NBM_WDMA>,
<&iommu1 M4U_PORT_L20_VENC_NBM_WDMA_LITE>,
<&iommu1 M4U_PORT_L20_VENC_FCS_NBM_WDMA>,
<&iommu1 M4U_PORT_L20_VENC_CUR_LUMA>,
<&iommu1 M4U_PORT_L20_VENC_CUR_CHROMA>,
<&iommu1 M4U_PORT_L20_VENC_REF_LUMA>,
<&iommu1 M4U_PORT_L20_VENC_REF_CHROMA>,
<&iommu1 M4U_PORT_L20_VENC_SUB_R_CHROMA>;
};
vdec_l21 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <21>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;/* core0 */
iommus = <&iommu0 M4U_PORT_L21_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_UFO_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_PP_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_PRED_WR_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_PPWRAP_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_TILE_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_VLD_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_VLD2_EXT>,
<&iommu0 M4U_PORT_L21_VDEC_AVC_MV_EXT>;
};
vdec_l22 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <22>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;/* core1 */
iommus = <&iommu1 M4U_PORT_L22_VDEC_MC_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_UFO_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_PP_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_PRED_RD_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_PRED_WR_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_PPWRAP_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_TILE_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_VLD_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_VLD2_EXT>,
<&iommu1 M4U_PORT_L22_VDEC_AVC_MV_EXT>;
};
vdec_l23 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <23>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;/* soc */
iommus = <&iommu1 M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
<&iommu1 M4U_PORT_L23_VDEC_RDMA_EXT>;
};
vdec_l24 {
compatible = "mediatek,mt8195-vcodec-larb";
mediatek,larb-id = <24>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;/* soc */
iommus = <&iommu0 M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT1_VLD_EXT>,/*LAT1*/
<&iommu0 M4U_PORT_L24_VDEC_LAT1_VLD2_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT1_TILE_EXT>,
<&iommu0 M4U_PORT_L24_VDEC_LAT1_WDMA_EXT>;
};
vdosys0_client {
compatible = "mediatek,mt8195-vdosys_client";
index = <0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
};
vdosys1_client {
compatible = "mediatek,mt8195-vdosys_client";
index = <1>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
vppsys0_client {
compatible = "mediatek,mt8195-vppsys0_client";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
vppsys1_client {
compatible = "mediatek,mt8195-vppsys1_client";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
clkitg: clkitg {
compatible = "simple-bus";
};
camera_fsync_ccu {
compatible = "mediatek,camera_fsync_ccu";
mediatek,ccu_rproc = <&ccu_rproc>;
};
ccu_rproc: ccu_rproc@17080000 {
compatible = "mediatek,ccu_rproc";
reg = <0 0x17080000 0 0x1000>;
interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_CCU_SEL>,
<&topckgen CLK_TOP_CAM_SEL>,
<&camsys CLK_CAM_MAIN_CAM>,
<&ccusys CLK_CCU_CCU0>,
<&ccusys CLK_CCU_AHB>;
clock-names = "CLK_TOP_CCU_SEL",
"CLK_TOP_CAM_SEL",
"CLK_CAM_MAIN_CAM",
"CLK_CCU_CCU0",
"CLK_CCU_AHB";
mediatek,ccu_rproc1 = <&ccu_rproc1>;
iommus = <&iommu1 M4U_PORT_L18_CAM_CCUO>,
<&iommu1 M4U_PORT_L18_CAM_CCUI>;
interconnects =
<&mmqos MASTER_LARB_PORT(M4U_PORT_L18_CAM_CCUO)
&mmqos SLAVE_COMMON(1)>,
<&mmqos MASTER_LARB_PORT(M4U_PORT_L18_CAM_CCUI)
&mmqos SLAVE_COMMON(1)>;
interconnect-names =
"l18_ccuo",
"l18_ccui";
};
ccu_rproc1: ccu_rproc1 {
compatible = "mediatek,ccu_rproc1";
iommus = <&iommu1 M4U_PORT_L18_CAM_CCUO2>,
<&iommu1 M4U_PORT_L18_CAM_CCUI2>;
};
};
&spmi {
grpid = <11>;
mt6315_6: mt6315@6 {
compatible = "mediatek,mt6315_6-regulator";
reg = <0x6 0 0xb 1>;
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2 4>;
regulator-always-on;
mtk,combined-regulator = <MT6315_VBUCK2
MT6315_VBUCK3
MT6315_VBUCK4>;
};
};
};
mt6315_7: mt6315@7 {
compatible = "mediatek,mt6315_7-regulator";
reg = <0x7 0 0xb 1>;
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2 4>;
mtk,combined-regulator = <MT6315_VBUCK2>;
};
};
};
};
#include "mediatek/mt8195-clkitg.dtsi"
#include "mediatek/trusty.dtsi"
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