34 lines
1 KiB
Text
34 lines
1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Chuan-Wen Chen <chuan-wen.chen@mediatek.com>
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*/
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&clkitg {
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status = "okay";
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bring-up {
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compatible = "mediatek,clk-bring-up";
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clocks =
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<&topckgen_clk CLK_TOP_AXI_SEL>,
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<&topckgen_clk CLK_TOP_AXIP_SEL>,
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<&topckgen_clk CLK_TOP_DPMAIF_MAIN_SEL>,
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<&topckgen_clk CLK_TOP_PWM_SEL>,
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<&topckgen_clk CLK_TOP_MCUPM_SEL>,
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<&topckgen_clk CLK_TOP_NFI1X_SEL>,
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<&infracfg_ao_clk CLK_IFRAO_CCIF5_MD>,
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<&infracfg_ao_clk CLK_IFRAO_CCIF4_AP>,
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<&infracfg_ao_clk CLK_IFRAO_RG_MEM_SUB_CK>,
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<&infracfg_ao_clk CLK_IFRAO_AES_TOP0>,
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<&infracfg_ao_clk CLK_IFRAOP_DCM_RG_FORCE>,
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<&nemi_reg_clk CLK_NEMI_REG_BUS_MON_MODE>,
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<&pericfg_ao_clk CLK_PERAOP_BTIF_BCLK>,
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<&vlp_cksys_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>,
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<&vlp_cksys_clk CLK_VLP_CK_PWM_VLP_SEL>,
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<&vlp_cksys_clk CLK_VLP_CK_AXI_VLP_SEL>,
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<&vlp_cksys_clk CLK_VLP_CK_DBGAO_26M_SEL>,
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<&vlp_cksys_clk CLK_VLP_CK_SRCK_SEL>,
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<&vlp_cksys_clk CLK_VLP_CK_SRAMRC_SEL>;
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};
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};
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