355 lines
7.6 KiB
Text
355 lines
7.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 MediaTek Inc.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/mt6835-pinfunc.h>
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#include "mediatek/mt6835_6377.dtsi"
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#include "mediatek/cust_mt6835_camera.dtsi"
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&mtk_leds {
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compatible = "mediatek,mtk-leds";
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backlight {
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led_mode = <6>;
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};
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};
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&pio {
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mtkfb_pins_lcm_led_en1: lcm_led_en1_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO150__FUNC_GPIO150>;
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slew-rate = <1>;
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output-high;
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};
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};
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mtkfb_pins_lcm_led_en0: lcm_led_en0_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO150__FUNC_GPIO150>;
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slew-rate = <1>;
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output-low;
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};
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};
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mtkfb_pins_lcm_rst_out1_gpio: lcm_rst_out1_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO86__FUNC_GPIO86>;
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slew-rate = <1>;
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output-high;
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};
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};
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mtkfb_pins_lcm_rst_out0_gpio: lcm_rst_out0_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO86__FUNC_GPIO86>;
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slew-rate = <1>;
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output-low;
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};
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};
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mtkfb_pins_lcm_dsi_te: lcm_dsi_te {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO85__FUNC_DSI_TE>;
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};
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};
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mtkfb_pins_lcm_cphy_out_gpio: lcm_cphy_out_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO133__FUNC_GPIO133>;
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slew-rate = <1>;
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output-high;
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};
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};
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};
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&mtkfb {
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pinctrl-names = "lcm_led_en1_gpio", "lcm_led_en0_gpio",
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"lcm_rst_out1_gpio", "lcm_rst_out0_gpio",
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"mode_te_te", "lcm_cphy_out_gpio";
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pinctrl-0 = <&mtkfb_pins_lcm_led_en1>;
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pinctrl-1 = <&mtkfb_pins_lcm_led_en0>;
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pinctrl-2 = <&mtkfb_pins_lcm_rst_out1_gpio>;
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pinctrl-3 = <&mtkfb_pins_lcm_rst_out0_gpio>;
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pinctrl-4 = <&mtkfb_pins_lcm_dsi_te>;
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pinctrl-5 = <&mtkfb_pins_lcm_cphy_out_gpio>;
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status = "okay";
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};
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&dispsys_config {
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pinctrl-names =
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"lcm_rst_out1_gpio", "lcm_rst_out0_gpio",
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"mode_te_te", "lcm_cphy_out_gpio";
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pinctrl-0 = <&mtkfb_pins_lcm_rst_out1_gpio>;
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pinctrl-1 = <&mtkfb_pins_lcm_rst_out0_gpio>;
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pinctrl-2 = <&mtkfb_pins_lcm_dsi_te>;
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pinctrl-3 = <&mtkfb_pins_lcm_cphy_out_gpio>;
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status = "okay";
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};
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&dsi0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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switch-fps = <0>;
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switch-mode = "vfp";
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panel1@0 {
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compatible = "jdi,nt36672e,vdo,120hz,hfp";
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reg = <0>;
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pm-enable-gpios = <&pio 150 0>;
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reset-gpios = <&pio 86 0>;
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cphy-sel-gpios = <&pio 133 0>;
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gate-ic = <4831>;
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pinctrl-names = "default";
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port {
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panel_in1: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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};
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panel2@1 {
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compatible = "jdi,nt36672e,vdo,60hz";
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reg = <1>;
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pm-enable-gpios = <&pio 150 0>;
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reset-gpios = <&pio 86 0>;
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cphy-sel-gpios = <&pio 133 0>;
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gate-ic = <4831>;
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pinctrl-names = "default";
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port {
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panel_in2: endpoint {
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remote-endpoint = <&dsi_out2>;
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};
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};
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};
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panel3@2 {
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compatible = "jdi,nt36672e,cphy,vdo,no,dsc";
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reg = <2>;
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pm-enable-gpios = <&pio 150 0>;
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reset-gpios = <&pio 86 0>;
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cphy-sel-gpios = <&pio 133 0>;
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gate-ic = <4831>;
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pinctrl-names = "default";
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port {
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panel_in3: endpoint {
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remote-endpoint = <&dsi_out3>;
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};
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};
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};
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ports {
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port {
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dsi_out: endpoint {
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remote-endpoint = <&panel_in1>;
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};
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dsi_out2: endpoint2 {
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remote-endpoint = <&panel_in2>;
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};
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dsi_out3: endpoint3 {
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remote-endpoint = <&panel_in3>;
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};
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};
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};
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};
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/* usb typec mux start */
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&pio {
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sel_up: sel_high {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
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output-high;
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};
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};
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sel_down: sel_low {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
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output-low;
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};
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};
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sw_enable: sw_enable {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO30__FUNC_GPIO30>;
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output-high;
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};
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};
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sw_disable: sw_disable {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO30__FUNC_GPIO30>;
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output-high;
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};
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};
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ps_enable: ps_enable {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO141__FUNC_GPIO141>;
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output-low;
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};
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};
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ps_disable: ps_disable {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO141__FUNC_GPIO141>;
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output-low;
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};
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};
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};
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&ps5169 {
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pinctrl-names = "enable", "disable";
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pinctrl-0 = <&ps_enable>;
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pinctrl-1 = <&ps_disable>;
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status = "okay";
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};
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&fusb304 {
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pinctrl-names = "sel_up", "sel_down",
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"enable", "disable";
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pinctrl-0 = <&sel_up>;
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pinctrl-1 = <&sel_down>;
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pinctrl-2 = <&sw_enable>;
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pinctrl-3 = <&sw_disable>;
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status = "okay";
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};
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&mt6375_typec {
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port {
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tcpc_typec_usb: endpoint@0 {
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remote-endpoint = <&ssusb_mux>;
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};
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};
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};
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&typec_mux_switch {
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orientation-switch;
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mode-switch;
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accessory;
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port {
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ssusb_mux: endpoint@0 {
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remote-endpoint = <&tcpc_typec_usb>;
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};
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};
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};
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/* usb typec mux end*/
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/* GPS GPIO standardization start */
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&pio {
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gps_pins_default: gps_default {
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};
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gps_l1_lna_pins_ol: gps_l1_lna@0 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO123__FUNC_GPIO123>;
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output-low;
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};
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};
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gps_l1_lna_pins_dsp_ctrl: gps_l1_lna@1 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO123__FUNC_GPS_L1_ELNA_EN>;
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};
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};
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gps_l1_lna_pins_oh: gps_l1_lna@2 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO123__FUNC_GPIO123>;
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output-high;
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};
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};
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gps_l5_lna_pins_ol: gps_l5_lna@0 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO124__FUNC_GPIO124>;
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output-low;
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};
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};
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gps_l5_lna_pins_dsp_ctrl: gps_l5_lna@1 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO124__FUNC_GPS_L5_ELNA_EN>;
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};
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};
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gps_l5_lna_pins_oh: gps_l5_lna@2 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO124__FUNC_GPIO124>;
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output-high;
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};
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};
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};
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&gps {
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pinctrl-names = "default",
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"gps_l1_lna_disable",
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"gps_l1_lna_dsp_ctrl",
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"gps_l1_lna_enable",
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"gps_l5_lna_disable",
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"gps_l5_lna_dsp_ctrl",
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"gps_l5_lna_enable";
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pinctrl-0 = <&gps_pins_default>;
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pinctrl-1 = <&gps_l1_lna_pins_ol>;
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pinctrl-2 = <&gps_l1_lna_pins_dsp_ctrl>;
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pinctrl-3 = <&gps_l1_lna_pins_oh>;
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pinctrl-4 = <&gps_l5_lna_pins_ol>;
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pinctrl-5 = <&gps_l5_lna_pins_dsp_ctrl>;
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pinctrl-6 = <&gps_l5_lna_pins_oh>;
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status = "okay";
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};
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/* GPS GPIO standardization end */
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&i2c6 {
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spk: speaker_amp@5c {
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compatible = "richtek,rt5512";
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#sound-dai-cells = <0>;
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reg = <0x5c>;
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status = "okay";
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sound-name-prefix = "Left";
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};
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};
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&sound {
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mediatek,spk-i2s = <3 0>;
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mediatek,speaker-codec {
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sound-dai = <&spk>;
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};
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};
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&scp {
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reg = <0 0x1c400000 0 0x100000>, /* tcm */
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<0 0x1c724000 0 0x1000>, /* cfg */
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<0 0x1c721000 0 0x1000>, /* clk*/
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<0 0x1c730000 0 0x1000>, /* cfg core0 */
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<0 0x1c740000 0 0x1000>, /* cfg core1 */
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<0 0x1c752000 0 0x1000>, /* bus tracker */
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<0 0x1c760000 0 0x40000>, /* llc */
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<0 0x1c7a5000 0 0x4>, /* cfg_sec */
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<0 0x1c7fb000 0 0x100>, /* mbox0 base */
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<0 0x1c7fb100 0 0x4>, /* mbox0 set */
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<0 0x1c7fb10c 0 0x4>, /* mbox0 clr */
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<0 0x1c7a5020 0 0x4>, /* mbox0 init */
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<0 0x1c7fc000 0 0x100>, /* mbox1 base */
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<0 0x1c7fc100 0 0x4>, /* mbox1 set */
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<0 0x1c7fc10c 0 0x4>, /* mbox1 clr */
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<0 0x1c7a5024 0 0x4>, /* mbox1 init */
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<0 0x1c7fd000 0 0x100>, /* mbox2 base */
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<0 0x1c7fd100 0 0x4>, /* mbox2 set */
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<0 0x1c7fd10c 0 0x4>, /* mbox2 clr */
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<0 0x1c7a5028 0 0x4>, /* mbox2 init */
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<0 0x1c7fe000 0 0x100>, /* mbox3 base */
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<0 0x1c7fe100 0 0x4>, /* mbox3 set */
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<0 0x1c7fe10c 0 0x4>, /* mbox3 clr */
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<0 0x1c7a502c 0 0x4>, /* mbox3 init */
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<0 0x1c7ff000 0 0x100>, /* mbox4 base */
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<0 0x1c7ff100 0 0x4>, /* mbox4 set */
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<0 0x1c7ff10c 0 0x4>, /* mbox4 clr */
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<0 0x1c7a5030 0 0x4>; /* mbox4 init */
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scp-sramsize = <0x100000>;
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secure-dump-size = <0x500000>;
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memorydump = <0x100000>, /* l2tcm */
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<0x03c000>, /* l1c */
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<0x003c00>, /* regdump */
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<0x000400>, /* trace buffer */
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<0x300000>; /* dram */
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};
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/*End of this file, DO NOT ADD ANYTHING HERE*/
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#include "mediatek/cust_mt6835_camera_6377_v4l2.dtsi"
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#include "mediatek/cust_mt6835_touch_6377_1080x2400.dtsi"
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#include "mediatek/cust_evb6835.dtsi"
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