kernel-brax3-ubuntu-touch/arch/arm64/boot/dts/mediatek/cust_mt6985_connfem.dtsi
erascape f319b992b1 kernel-5.15: Initial import brax3 UT kernel
* halium configs enabled

Signed-off-by: erascape <erascape@proton.me>
2025-09-23 15:17:10 +00:00

108 lines
3.5 KiB
Text

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2020 MediaTek Inc.
*/
/* Connsys FEM Start */
&connfem {
/* FEM ID */
nofem: nofem {
vid = <0>;
pid = <0>;
};
wlan7207h: wlan7207h {
vid = <2>;
pid = <4>;
};
qm42639: qm42639 {
vid = <3>;
pid = <3>;
};
qm45639: qm45639 {
vid = <3>;
pid = <4>;
};
qm42195: qm42195 {
vid = <3>;
pid = <1>;
};
qm45197: qm45197 {
vid = <3>;
pid = <2>;
};
wlan7305h: wlan7305h {
vid = <2>;
pid = <8>;
};
wlan7209c: wlan7209c {
vid = <2>;
pid = <9>;
};
/* pin mapping for combo chip */
wlan7207h_nofem {
mapping = <0x17 0x22 0>, /* ANTSEL 0x17 <-> PIN #0x22: 2G BT0 LNAEN */
<0x18 0x24 0>; /* ANTSEL 0x18 <-> PIN #0x24: 2G BT0 BTEN */
};
qm42639_qm45639 {
mapping = <0x0 0x3 0>, /* ANTSEL 0x00 <-> PIN #0x3: 2G WF0 PAEN */
<0x01 0x02 0>, /* ANTSEL 0x01 <-> PIN #0x2: 2G WF0 LNAEN */
<0x02 0x04 0>, /* ANTSEL 0x02 <-> PIN #0x4: 2G WF0 BTEN */
<0x03 0x0e 0>, /* ANTSEL 0x03 <-> PIN #0xE: 2G WF0 SEL4 */
<0x04 0x83 0>, /* ANTSEL 0x04 <-> PIN #0x3: 2G WF1 PAEN */
<0x05 0x82 0>, /* ANTSEL 0x05 <-> PIN #0x2: 2G WF1 LNAEN */
<0x06 0x84 0>, /* ANTSEL 0x06 <-> PIN #0x4: 2G WF1 BTEN */
<0x07 0x8e 0>, /* ANTSEL 0x07 <-> PIN #0xE: 2G WF1 SEL4 */
<0x12 0x4a 0>, /* ANTSEL 0x12 <-> PIN #0xA: 5G WF0 PAEN */
<0x13 0x4b 0>, /* ANTSEL 0x13 <-> PIN #0xB: 5G WF0 LNAEN */
<0x14 0x4c 0>, /* ANTSEL 0x14 <-> PIN #0xC: 5G WF0 SEL3 */
<0x15 0x41 0>, /* ANTSEL 0x15 <-> PIN #0x1: 5G WF0 SEL4 */
<0x0e 0xca 0>, /* ANTSEL 0x0E <-> PIN #0xA: 5G WF1 PAEN */
<0x0f 0xcb 0>, /* ANTSEL 0x0F <-> PIN #0xB: 5G WF1 LNAEN */
<0x10 0xcc 0>, /* ANTSEL 0x10 <-> PIN #0xC: 5G WF1 SEL3 */
<0x11 0xc1 0>; /* ANTSEL 0x11 <-> PIN #0x1: 5G WF1 SEL4 */
};
qm42195_qm45197 {
mapping = <0x0 0x3 0>, /* ANTSEL 0x00 <-> PIN #0x3: 2G WF0 PAEN */
<0x01 0x02 0>, /* ANTSEL 0x01 <-> PIN #0x2: 2G WF0 LNAEN */
<0x02 0x04 0>, /* ANTSEL 0x02 <-> PIN #0x4: 2G WF0 BTEN */
<0x04 0x83 0>, /* ANTSEL 0x04 <-> PIN #0x3: 2G WF1 PAEN */
<0x05 0x82 0>, /* ANTSEL 0x05 <-> PIN #0x2: 2G WF1 LNAEN */
<0x06 0x84 0>, /* ANTSEL 0x06 <-> PIN #0x4: 2G WF1 BTEN */
<0x12 0x4a 0>, /* ANTSEL 0x12 <-> PIN #0xA: 5G WF0 PAEN */
<0x13 0x4b 0>, /* ANTSEL 0x13 <-> PIN #0xB: 5G WF0 LNAEN */
<0x14 0x4c 0>, /* ANTSEL 0x14 <-> PIN #0xC: 5G WF0 SEL3 */
<0x0e 0xca 0>, /* ANTSEL 0x0E <-> PIN #0xA: 5G WF1 PAEN */
<0x0f 0xcb 0>, /* ANTSEL 0x0F <-> PIN #0xB: 5G WF1 LNAEN */
<0x10 0xcc 0>; /* ANTSEL 0x10 <-> PIN #0xC: 5G WF1 SEL3 */
};
wlan7305h_wlan7209c {
mapping = <0x0 0x3 0>, /* ANTSEL 0x00 <-> PIN #0x3: 2G WF0 C0 */
<0x01 0x02 0>, /* ANTSEL 0x01 <-> PIN #0x2: 2G WF0 C1 */
<0x02 0x04 0>, /* ANTSEL 0x02 <-> PIN #0x4: 2G WF0 C2 */
<0x03 0x0e 0>, /* ANTSEL 0x03 <-> PIN #0xE: 2G WF0 C3 */
<0x04 0x83 0>, /* ANTSEL 0x04 <-> PIN #0x3: 2G WF1 C0 */
<0x05 0x82 0>, /* ANTSEL 0x05 <-> PIN #0x2: 2G WF1 C1 */
<0x06 0x84 0>, /* ANTSEL 0x06 <-> PIN #0x4: 2G WF1 C2 */
<0x07 0x8e 0>, /* ANTSEL 0x07 <-> PIN #0xE: 2G WF1 C3 */
<0x12 0x4a 0>, /* ANTSEL 0x12 <-> PIN #0xA: 5G WF0 C0 */
<0x13 0x4b 0>, /* ANTSEL 0x13 <-> PIN #0xB: 5G WF0 C1 */
<0x14 0x4c 0>, /* ANTSEL 0x14 <-> PIN #0xC: 5G WF0 C2 */
<0x15 0x41 0>, /* ANTSEL 0x15 <-> PIN #0x1: 5G WF0 C3 */
<0x0e 0xca 0>, /* ANTSEL 0x0E <-> PIN #0xA: 5G WF1 C0 */
<0x0f 0xcb 0>, /* ANTSEL 0x0F <-> PIN #0xB: 5G WF1 C1 */
<0x10 0xcc 0>, /* ANTSEL 0x10 <-> PIN #0xC: 5G WF1 C2 */
<0x11 0xc1 0>; /* ANTSEL 0x11 <-> PIN #0x1: 5G WF1 C3 */
};
};
/* Connsys FEM End */