kernel-brax3-ubuntu-touch/arch/arm64/boot/dts/mediatek/cust_mt6886_connfem.dtsi
erascape f319b992b1 kernel-5.15: Initial import brax3 UT kernel
* halium configs enabled

Signed-off-by: erascape <erascape@proton.me>
2025-09-23 15:17:10 +00:00

138 lines
3.6 KiB
Text

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2020 MediaTek Inc.
*/
/* Connsys FEM Start */
&connfem {
/* PINCTRL States*/
pinctrl-names = "wlan7207h_wlan7207c", /* pinctrl-0 */
"qm42195_qm45197"; /* pinctrl-1 */
pinctrl-0 = <&wlan7207h_wf0>, <&wlan7207h_wf1>,
<&wlan7207c_wf0>, <&wlan7207c_wf1>;
pinctrl-1 = <&qm42195_wf0>, <&qm42195_wf1>,
<&qm45197_wf0>, <&qm45197_wf1>;
/* FEM ID */
nofem: nofem {
vid = <0>;
pid = <0>;
};
wlan7207h: wlan7207h {
vid = <2>;
pid = <4>;
};
wlan7207c: wlan7207c {
vid = <2>;
pid = <7>;
};
qm42195: qm42195 {
vid = <3>;
pid = <1>;
};
qm45197: qm45197 {
vid = <3>;
pid = <2>;
};
};
/* ANTSEL PINMUX and FEM Func Mapping */
&pio {
wlan7207h_wf0: wlan7207h_wf0 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO182__FUNC_ANT_SEL0>,
<PINMUX_GPIO183__FUNC_ANT_SEL1>,
<PINMUX_GPIO184__FUNC_ANT_SEL2>,
<PINMUX_GPIO185__FUNC_ANT_SEL3>;
mapping = <0 3 0>, /* ANTSEL 0 <-> PIN #3: C0 */
<1 2 0>, /* ANTSEL 1 <-> PIN #2: C1 */
<2 4 0>, /* ANTSEL 2 <-> PIN #4: C2 */
<3 11 0>; /* ANTSEL 3 <-> VCTRL */
};
};
wlan7207h_wf1: wlan7207h_wf1 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO13__FUNC_ANT_SEL8>,
<PINMUX_GPIO14__FUNC_ANT_SEL9>,
<PINMUX_GPIO15__FUNC_ANT_SEL10>;
mapping = <8 0x83 0>, /* ANTSEL 8 <-> PIN #3: C0 */
<9 0x82 0>, /* ANTSEL 9 <-> PIN #2: C1 */
<10 0x84 0>; /* ANTSEL 10 <-> PIN #4: C2 */
};
};
wlan7207c_wf0: wlan7207c_wf0 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO186__FUNC_ANT_SEL4>,
<PINMUX_GPIO160__FUNC_ANT_SEL20>,
<PINMUX_GPIO188__FUNC_ANT_SEL6>,
<PINMUX_GPIO189__FUNC_ANT_SEL7>;
mapping = <4 0x4A 0>, /* ANTSEL 4 <-> PIN #10: C0 */
<20 0x4B 0>, /* ANTSEL 20 <-> PIN #11: C1 */
<6 0x4C 0>, /* ANTSEL 6 <-> PIN #12: C2 */
<7 0x41 0>; /* ANTSEL 7 <-> PIN #1: C3 */
};
};
wlan7207c_wf1: wlan7207c_wf1 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO147__FUNC_ANT_SEL18>,
<PINMUX_GPIO161__FUNC_ANT_SEL21>,
<PINMUX_GPIO159__FUNC_ANT_SEL19>,
<PINMUX_GPIO187__FUNC_ANT_SEL5>;
mapping = <18 0xCA 0>, /* ANTSEL 18 <-> PIN #10: C0 */
<21 0xCB 0>, /* ANTSEL 21 <-> PIN #11: C1 */
<19 0xCC 0>, /* ANTSEL 19 <-> PIN #12: C2 */
<5 0xC1 0>; /* ANTSEL 5 <-> PIN #1: C3 */
};
};
qm42195_wf0: qm42195_wf0 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO182__FUNC_ANT_SEL0>,
<PINMUX_GPIO183__FUNC_ANT_SEL1>,
<PINMUX_GPIO184__FUNC_ANT_SEL2>,
<PINMUX_GPIO185__FUNC_ANT_SEL3>;
mapping = <0 3 0>, /* ANTSEL 0 <-> PIN #3: PAEN */
<1 2 0>, /* ANTSEL 1 <-> PIN #2: LNAEN */
<2 4 0>, /* ANTSEL 2 <-> PIN #4: BTEN */
<3 11 0>; /* ANTSEL 3 <-> VCTRL */
};
};
qm42195_wf1: qm42195_wf1 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO13__FUNC_ANT_SEL8>,
<PINMUX_GPIO14__FUNC_ANT_SEL9>,
<PINMUX_GPIO15__FUNC_ANT_SEL10>;
mapping = <8 0x83 0>, /* ANTSEL 8 <-> PIN #3: PAEN */
<9 0x82 0>, /* ANTSEL 9 <-> PIN #2: LNAEN */
<10 0x84 0>; /* ANTSEL 10 <-> PIN #4: BTEN */
};
};
qm45197_wf0: qm45197_wf0 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO186__FUNC_ANT_SEL4>,
<PINMUX_GPIO160__FUNC_ANT_SEL20>,
<PINMUX_GPIO188__FUNC_ANT_SEL6>;
mapping = <4 0x4A 0>, /* ANTSEL 4 <-> PIN #10: PAEN */
<20 0x4B 0>, /* ANTSEL 20 <-> PIN #11: LNAEN */
<6 0x4C 0>; /* ANTSEL 6 <-> PIN #12: SEL3 */
};
};
qm45197_wf1: qm45197_wf1 {
pins_cmd_dat {
pinmux = <PINMUX_GPIO147__FUNC_ANT_SEL18>,
<PINMUX_GPIO161__FUNC_ANT_SEL21>,
<PINMUX_GPIO159__FUNC_ANT_SEL19>;
mapping = <18 0xCA 0>, /* ANTSEL 18 <-> PIN #10: PAEN */
<21 0xCB 0>, /* ANTSEL 21 <-> PIN #11: LNAEN */
<19 0xCC 0>; /* ANTSEL 19 <-> PIN #12: SEL3 */
};
};
};
/* Connsys FEM End */