/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2021 MediaTek Inc.
 */

#ifndef __MFD_MT6363_CORE_H__
#define __MFD_MT6363_CORE_H__

#define MT6363_REG_WIDTH 8

enum mt6363_irq_top_status_shift {
	MT6363_BUCK_TOP = 0,
	MT6363_LDO_TOP,
	MT6363_PSC_TOP,
	MT6363_MISC_TOP,
	MT6363_HK_TOP,
	MT6363_SCK_TOP,
	MT6363_BM_TOP,
	MT6363_AUD_TOP,
};

enum mt6363_irq_numbers {
	MT6363_IRQ_VS2_OC = 0,
	MT6363_IRQ_VBUCK1_OC,
	MT6363_IRQ_VBUCK2_OC,
	MT6363_IRQ_VBUCK3_OC,
	MT6363_IRQ_VBUCK4_OC,
	MT6363_IRQ_VBUCK5_OC,
	MT6363_IRQ_VBUCK6_OC,
	MT6363_IRQ_VBUCK7_OC,
	MT6363_IRQ_VS1_OC,
	MT6363_IRQ_VS3_OC,
	MT6363_IRQ_VCN15_OC = 16,
	MT6363_IRQ_VCN13_OC,
	MT6363_IRQ_VRF09_OC,
	MT6363_IRQ_VRF12_OC,
	MT6363_IRQ_VRF13_OC,
	MT6363_IRQ_VRF18_OC,
	MT6363_IRQ_VRFIO18_OC,
	MT6363_IRQ_VSRAM_DIGRF_OC,
	MT6363_IRQ_VSRAM_MDFE_OC,
	MT6363_IRQ_VSRAM_MODEM_OC,
	MT6363_IRQ_VTREF18_OC,
	MT6363_IRQ_VSRAM_CPUB_OC,
	MT6363_IRQ_VSRAM_CPUM_OC,
	MT6363_IRQ_VSRAM_CPUL_OC,
	MT6363_IRQ_VSRAM_APU_OC,
	MT6363_IRQ_VAUX18_OC,
	MT6363_IRQ_VEMC_OC,
	MT6363_IRQ_VUFS12_OC,
	MT6363_IRQ_VUFS18_OC,
	MT6363_IRQ_VIO18_OC,
	MT6363_IRQ_VIO075_OC,
	MT6363_IRQ_VA12_1_OC,
	MT6363_IRQ_VA12_2_OC,
	MT6363_IRQ_VA15_OC,
	MT6363_IRQ_VM18_OC,
	MT6363_IRQ_PWRKEY = 48,
	MT6363_IRQ_HOMEKEY,
	MT6363_IRQ_HOMEKEY_2,
	MT6363_IRQ_PWRKEY_R,
	MT6363_IRQ_HOMEKEY_R,
	MT6363_IRQ_HOMEKEY_2_R,
	MT6363_IRQ_NI_LVSYS_INT_FALLING,
	MT6363_IRQ_NI_LVSYS_INT_RISING,
	MT6363_IRQ_CHRDET_LEVEL,
	MT6363_IRQ_CHRDET_EDGE,
	MT6363_IRQ_RCS0 = 64,
	MT6363_IRQ_SPMI_CMD_ALERT,
	MT6363_IRQ_BM_PROTREG = 70,
	MT6363_IRQ_BUCK_PROTREG = 72,
	MT6363_IRQ_LDO_PROTREG,
	MT6363_IRQ_PSC_PROTREG,
	MT6363_IRQ_PLT_PROTREG,
	MT6363_IRQ_HK_PROTREG,
	MT6363_IRQ_TOP_PROTREG = 79,
	MT6363_IRQ_BAT_H,
	MT6363_IRQ_BAT_L,
	MT6363_IRQ_BAT2_H,
	MT6363_IRQ_BAT2_L,
	MT6363_IRQ_BAT_TEMP_H,
	MT6363_IRQ_BAT_TEMP_L,
	MT6363_IRQ_THR_H,
	MT6363_IRQ_THR_L,
	MT6363_IRQ_AUXADC_IMP,
	MT6363_IRQ_NAG_C_DLTV,
	MT6363_IRQ_FG_BAT_H = 88,
	MT6363_IRQ_FG_BAT_L,
	MT6363_IRQ_FG_CUR_H,
	MT6363_IRQ_FG_CUR_L,
	MT6363_IRQ_FG_ZCV,
	MT6363_IRQ_FG_N_CHARGE_L = 95,
	MT6363_IRQ_FG_IAVG_H,
	MT6363_IRQ_FG_IAVG_L,
	MT6363_IRQ_FG_DISCHARGE = 99,
	MT6363_IRQ_FG_CHARGE,
	MT6363_IRQ_BATON_LV = 104,
	MT6363_IRQ_BATON_BAT_IN = 106,
	MT6363_IRQ_BATON_BAT_OUT,
	MT6363_IRQ_NR = 108,
};

#define MT6363_IRQ_BUCK_BASE MT6363_IRQ_VS2_OC
#define MT6363_IRQ_LDO_BASE MT6363_IRQ_VCN15_OC
#define MT6363_IRQ_PSC_BASE MT6363_IRQ_PWRKEY
#define MT6363_IRQ_MISC_BASE MT6363_IRQ_RCS0
#define MT6363_IRQ_HK_BASE MT6363_IRQ_BAT_H
#define MT6363_IRQ_BM_BASE MT6363_IRQ_FG_BAT_H

#define MT6363_IRQ_BUCK_BITS \
	(MT6363_IRQ_VS3_OC - MT6363_IRQ_BUCK_BASE + 1)
#define MT6363_IRQ_LDO_BITS \
	(MT6363_IRQ_VM18_OC - MT6363_IRQ_LDO_BASE + 1)
#define MT6363_IRQ_PSC_BITS \
	(MT6363_IRQ_CHRDET_EDGE - MT6363_IRQ_PSC_BASE + 1)
#define MT6363_IRQ_MISC_BITS \
	(MT6363_IRQ_TOP_PROTREG - MT6363_IRQ_MISC_BASE + 1)
#define MT6363_IRQ_HK_BITS \
	(MT6363_IRQ_NAG_C_DLTV - MT6363_IRQ_HK_BASE + 1)
#define MT6363_IRQ_BM_BITS \
	(MT6363_IRQ_BATON_BAT_OUT - MT6363_IRQ_BM_BASE + 1)

#define MT6363_TOP_GEN(sp) \
{ \
	.hwirq_base = MT6363_IRQ_##sp##_BASE, \
	.num_int_regs =	((MT6363_IRQ_##sp##_BITS - 1) / MT6363_REG_WIDTH) + 1, \
	.en_reg = MT6363_##sp##_TOP_INT_CON0, \
	.en_reg_shift = 0x3, \
	.sta_reg = MT6363_##sp##_TOP_INT_STATUS0, \
	.sta_reg_shift = 0x1, \
	.top_offset = MT6363_##sp##_TOP, \
}

#endif /* __MFD_MT6363_CORE_H__ */