/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ /* * Copyright (c) 2021 MediaTek Inc. * */ #ifndef _DT_BINDINGS_GCE_MT6835_H #define _DT_BINDINGS_GCE_MT6835_H /* assign timeout 0 also means default */ #define CMDQ_NO_TIMEOUT 0xffffffff #define CMDQ_TIMEOUT_DEFAULT 1000 /* GCE thread priority */ #define CMDQ_THR_PRIO_LOWEST 0 #define CMDQ_THR_PRIO_1 1 #define CMDQ_THR_PRIO_2 2 #define CMDQ_THR_PRIO_3 3 #define CMDQ_THR_PRIO_4 4 #define CMDQ_THR_PRIO_5 5 #define CMDQ_THR_PRIO_6 6 #define CMDQ_THR_PRIO_HIGHEST 7 /* CPR count in 32bit register */ #define GCE_CPR_COUNT 1312 /* GCE subsys table */ #define SUBSYS_1300XXXX 0 #define SUBSYS_1400XXXX 1 #define SUBSYS_1401XXXX 2 #define SUBSYS_1402XXXX 3 #define SUBSYS_1502XXXX 4 #define SUBSYS_1880XXXX 5 #define SUBSYS_1881XXXX 6 #define SUBSYS_1882XXXX 7 #define SUBSYS_1883XXXX 8 #define SUBSYS_1884XXXX 9 #define SUBSYS_1000XXXX 10 #define SUBSYS_1001XXXX 11 #define SUBSYS_1002XXXX 12 #define SUBSYS_1003XXXX 13 #define SUBSYS_1004XXXX 14 #define SUBSYS_1005XXXX 15 #define SUBSYS_1020XXXX 16 #define SUBSYS_1028XXXX 17 #define SUBSYS_1700XXXX 18 #define SUBSYS_1701XXXX 19 #define SUBSYS_1702XXXX 20 #define SUBSYS_1703XXXX 21 #define SUBSYS_1800XXXX 22 #define SUBSYS_1801XXXX 23 #define SUBSYS_1802XXXX 24 #define SUBSYS_1804XXXX 25 #define SUBSYS_1805XXXX 26 #define SUBSYS_1808XXXX 27 #define SUBSYS_180aXXXX 28 #define SUBSYS_180bXXXX 29 #define SUBSYS_NO_SUPPORT 99 /* GCE General Purpose Register (GPR) support * Leave note for scenario usage here */ /* GCE: write mask */ #define GCE_GPR_R00 0x00 #define GCE_GPR_R01 0x01 #define GCE_GPR_R02 0x02 /* DISP */ #define GCE_GPR_R03 0x03 #define GCE_GPR_R04 0x04 #define GCE_GPR_R05 0x05 #define GCE_GPR_R06 0x06 #define GCE_GPR_R07 0x07 /* MML Pipe 0 */ #define GCE_GPR_R08 0x08 #define GCE_GPR_R09 0x09 /* MML Pipe 1 */ #define GCE_GPR_R10 0x0A #define GCE_GPR_R11 0x0B /* MDP Pipe 0 */ #define GCE_GPR_R12 0x0C #define GCE_GPR_R13 0x0D /* MDP Pipe 1 */ #define GCE_GPR_R14 0x0E #define GCE_GPR_R15 0x0F /* GCE-D hardware events */ #define CMDQ_EVENT_DISPSYS_DISP_OVL0_SOF 0 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_SOF 1 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_SOF 2 #define CMDQ_EVENT_DISPSYS_DISP_RSZ0_SOF 3 #define CMDQ_EVENT_DISPSYS_DISP_RDMA0_SOF 4 #define CMDQ_EVENT_DISPSYS_DISP_TDSHP0_SOF 5 #define CMDQ_EVENT_DISPSYS_DISP_C3D0_SOF 6 #define CMDQ_EVENT_DISPSYS_DISP_COLOR0_SOF 7 #define CMDQ_EVENT_DISPSYS_DISP_CCORR0_SOF 8 #define CMDQ_EVENT_DISPSYS_DISP_CCORR1_SOF 9 #define CMDQ_EVENT_DISPSYS_DISP_MDP_AAL0_SOF 10 #define CMDQ_EVENT_DISPSYS_DISP_AAL0_SOF 11 #define CMDQ_EVENT_DISPSYS_DSI0_TARGET_LINE_EVENT 12 #define CMDQ_EVENT_DISPSYS_DISP_POSTMASK0_SOF 13 #define CMDQ_EVENT_DISPSYS_DISP_DITHER0_SOF 14 #define CMDQ_EVENT_DISPSYS_DISP_CHIST0_SOF 15 #define CMDQ_EVENT_DISPSYS_DISP_CHIST1_SOF 16 #define CMDQ_EVENT_DISPSYS_DISP_CM0_SOF 17 #define CMDQ_EVENT_DISPSYS_DISP_SPR0_SOF 18 #define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE0_SOF 19 #define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE1_SOF 20 #define CMDQ_EVENT_DISPSYS_DISP_MERGE0_SOF 21 #define CMDQ_EVENT_DISPSYS_DISP_DSI0_SOF 22 #define CMDQ_EVENT_DISPSYS_DISP_WDMA0_SOF 23 #define CMDQ_EVENT_DISPSYS_DISP_UFBC_WDMA0_SOF 24 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_NWCG_SOF 25 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_NWCG_SOF 26 #define CMDQ_EVENT_DISPSYS_DISP_RDMA1_SOF 27 #define CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_SOF 28 #define CMDQ_EVENT_DISPSYS_DISP_DBI0_SOF 29 #define CMDQ_EVENT_DISPSYS_DISP_WDMA1_SOF 30 #define CMDQ_EVENT_DISPSYS_DISP_Y2R0_SOF 31 #define CMDQ_EVENT_DISPSYS_INLINEROT0_SOF 32 #define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC0_SOF 33 #define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC1_SOF 34 #define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC2_SOF 35 #define CMDQ_EVENT_DISPSYS_DISP_DLI_ASYNC3_SOF 36 #define CMDQ_EVENT_DISPSYS_DISP_DLO_ASYNC0_SOF 37 #define CMDQ_EVENT_DISPSYS_DISP_DLO_ASYNC1_SOF 38 #define CMDQ_EVENT_DISPSYS_DISP_DLO_ASYNC2_SOF 39 #define CMDQ_EVENT_DISPSYS_DISP_DLO_ASYNC3_SOF 40 #define CMDQ_EVENT_DISPSYS_DISP_PWM0_SOF 41 #define CMDQ_EVENT_DISPSYS_DUMMY_SOF_0 42 #define CMDQ_EVENT_DISPSYS_DUMMY_SOF_1 43 #define CMDQ_EVENT_DISPSYS_DUMMY_SOF_2 44 #define CMDQ_EVENT_DISPSYS_DSI0_FRAME_DONE 45 #define CMDQ_EVENT_DISPSYS_DP_INTF0_FRAME_DONE 46 #define CMDQ_EVENT_DISPSYS_DISP_DBI0_FRAME_DONE 47 #define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE0_FRAME_DONE 48 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_FRAME_DONE 49 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_FRAME_DONE 50 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_FRAME_DONE 51 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_NWCG_FRAME_DONE 52 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_NWCG_FRAME_DONE 53 #define CMDQ_EVENT_DISPSYS_DISP_WDMA0_FRAME_DONE 54 #define CMDQ_EVENT_DISPSYS_DISP_UFBC_WDMA0_FRAME_DONE 55 #define CMDQ_EVENT_DISPSYS_DISP_WDMA1_FRAME_DONE 56 #define CMDQ_EVENT_DISPSYS_DSI0_FRAME_DONE_2 57 #define CMDQ_EVENT_DISPSYS_DP_INTF0_FRAME_DONE_2 58 #define CMDQ_EVENT_DISPSYS_DISP_WDMA1_FRAME_DONE_2 59 #define CMDQ_EVENT_DISPSYS_DISP_WDMA0_FRAME_DONE_2 60 #define CMDQ_EVENT_DISPSYS_DISP_UFBC_WDMA0_FRAME_DONE_2 61 #define CMDQ_EVENT_DISPSYS_DISP_TDSHP0_FRAME_DONE 62 #define CMDQ_EVENT_DISPSYS_DISP_SPR0_FRAME_DONE 63 #define CMDQ_EVENT_DISPSYS_DISP_RSZ0_FRAME_DONE 64 #define CMDQ_EVENT_DISPSYS_DISP_RDMA1_FRAME_DONE 65 #define CMDQ_EVENT_DISPSYS_DISP_RDMA0_FRAME_DONE 66 #define CMDQ_EVENT_DISPSYS_DISP_POSTMASK0_FRAME_DONE 67 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_NWCG_FRAME_DONE_2 68 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_FRAME_DONE_2 69 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_FRAME_DONE_2 70 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_NWCG_FRAME_DONE_2 71 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_FRAME_DONE_2 72 #define CMDQ_EVENT_DISPSYS_DISP_MERGE0_FRAME_DONE 73 #define CMDQ_EVENT_DISPSYS_DISP_MDP_AAL0_FRAME_DONE 74 #define CMDQ_EVENT_DISPSYS_DISP_GAMMA0_FRAME_DONE 75 #define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE1_FRAME_DONE 76 #define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE0_FRAME_DONE_2 77 #define CMDQ_EVENT_DISPSYS_DISP_DBI0_FRAME_DONE_2 78 #define CMDQ_EVENT_DISPSYS_DISP_DITHER0_FRAME_DONE 79 #define CMDQ_EVENT_DISPSYS_DISP_COLOR0_FRAME_DONE 80 #define CMDQ_EVENT_DISPSYS_DISP_CM0_FRAME_DONE 81 #define CMDQ_EVENT_DISPSYS_DISP_CHIST1_FRAME_DONE 82 #define CMDQ_EVENT_DISPSYS_DISP_CHIST0_FRAME_DONE 83 #define CMDQ_EVENT_DISPSYS_DISP_CCORR1_FRAME_DONE 84 #define CMDQ_EVENT_DISPSYS_DISP_CCORR0_FRAME_DONE 85 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_0 86 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_1 87 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_2 88 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_3 89 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_4 90 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_5 91 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_6 92 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_7 93 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_8 94 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_9 95 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_10 96 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_11 97 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_12 98 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_13 99 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_14 100 #define CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_15 101 #define CMDQ_EVENT_DISPSYS_DSI0_TE_ENG_EVENT 102 #define CMDQ_EVENT_DISPSYS_DSI0_IRQ_ENG_EVENT 103 #define CMDQ_EVENT_DISPSYS_DSI0_DONE_ENG_EVENT 104 #define CMDQ_EVENT_DISPSYS_DP_VSYNC_START_ENG_EVENT 105 #define CMDQ_EVENT_DISPSYS_DP_VSYNC_END_ENG_EVENT 106 #define CMDQ_EVENT_DISPSYS_DP_VDE_START_ENG_EVENT 107 #define CMDQ_EVENT_DISPSYS_DP_VDE_END_ENG_EVENT 108 #define CMDQ_EVENT_DISPSYS_DP_TARGET_LINE_ENG_EVENT 109 #define CMDQ_EVENT_DISPSYS_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 110 #define CMDQ_EVENT_DISPSYS_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 111 #define CMDQ_EVENT_DISPSYS_DISP_RDMA1_TARGET_LINE_ENG_EVENT 112 #define CMDQ_EVENT_DISPSYS_DISP_RDMA0_TARGET_LINE_ENG_EVENT 113 #define CMDQ_EVENT_DISPSYS_DISP_POSTMASK0_RST_DONE_ENG 114 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_RST_DONE_ENG_EVENT 115 #define CMDQ_EVENT_DISPSYS_DISP_OVL1_2L_NWCG_RST_DONE_ENG_EVENT 116 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_RST_DONE_ENG_EVENT 117 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_RST_DONE_ENG_EVENT 118 #define CMDQ_EVENT_DISPSYS_DISP_OVL0_2L_NWCG_RST_DONE_ENG_EVENT 119 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_0 120 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_1 121 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_2 122 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_3 123 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_4 124 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_5 125 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_6 126 #define CMDQ_EVENT_DISPSYS_BUF_UNDERRUN_ENG_EVENT_70 127 #define CMDQ_EVENT_GCE_DSI0_TE_I 898 #define CMDQ_EVENT_GCE_DSI1_TE_I 899 /* GCE-M hardware events */ #define CMDQ_EVENT_VENC1_VENC_EVENT_0 0 #define CMDQ_EVENT_VENC1_VENC_EVENT_1 1 #define CMDQ_EVENT_VENC1_VENC_EVENT_2 2 #define CMDQ_EVENT_VENC1_VENC_EVENT_3 3 #define CMDQ_EVENT_VENC1_VENC_EVENT_4 4 #define CMDQ_EVENT_VENC1_VENC_EVENT_5 5 #define CMDQ_EVENT_VENC1_VENC_EVENT_6 6 #define CMDQ_EVENT_VENC1_VENC_EVENT_7 7 #define CMDQ_EVENT_VENC1_VENC_EVENT_8 8 #define CMDQ_EVENT_VENC1_VENC_EVENT_9 9 #define CMDQ_EVENT_VENC1_VENC_EVENT_10 10 #define CMDQ_EVENT_VENC1_VENC_EVENT_11 11 #define CMDQ_EVENT_VENC1_VENC_EVENT_12 12 #define CMDQ_EVENT_VENC1_VENC_EVENT_13 13 #define CMDQ_EVENT_VENC1_VENC_EVENT_14 14 #define CMDQ_EVENT_VENC1_VENC_EVENT_15 15 #define CMDQ_EVENT_VENC1_VENC_EVENT_16 16 #define CMDQ_EVENT_VENC1_VENC_EVENT_17 17 #define CMDQ_EVENT_VENC1_VENC_EVENT_18 18 #define CMDQ_EVENT_VENC1_VENC_EVENT_19 19 #define CMDQ_EVENT_VENC1_VENC_EVENT_20 20 #define CMDQ_EVENT_VENC1_VENC_EVENT_21 21 #define CMDQ_EVENT_VENC1_VENC_EVENT_22 22 #define CMDQ_EVENT_VENC1_VENC_EVENT_23 23 #define CMDQ_EVENT_VENC1_VENC_EVENT_24 24 #define CMDQ_EVENT_VENC1_VENC_EVENT_25 25 #define CMDQ_EVENT_VENC1_VENC_EVENT_26 26 #define CMDQ_EVENT_VENC1_VENC_EVENT_27 27 #define CMDQ_EVENT_VENC1_VENC_EVENT_28 28 #define CMDQ_EVENT_VENC1_VENC_EVENT_29 29 #define CMDQ_EVENT_VENC1_VENC_EVENT_30 30 #define CMDQ_EVENT_VENC1_VENC_EVENT_31 31 #define CMDQ_EVENT_IPE_IPE_FDVT_DONE 33 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_0 65 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_1 66 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_2 67 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_3 68 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_4 69 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_5 70 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_6 71 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_7 72 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_8 73 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_9 74 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_10 75 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_11 76 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_12 77 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_13 78 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_14 79 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_15 80 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_16 81 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_17 82 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_18 83 #define CMDQ_EVENT_IMG1_DIP_DMA_ERR_EVENT 84 #define CMDQ_EVENT_MDP_MDP_RDMA0_SOF 128 #define CMDQ_EVENT_MDP_MDP_RDMA1_SOF 129 #define CMDQ_EVENT_MDP_MDP_TDSHP0_SOF 130 #define CMDQ_EVENT_MDP_MDP_TDSHP1_SOF 131 #define CMDQ_EVENT_MDP_MDP_COLOR0_SOF 132 #define CMDQ_EVENT_MDP_MDP_COLOR1_SOF 133 #define CMDQ_EVENT_MDP_MDP_WROT0_SOF 134 #define CMDQ_EVENT_MDP_MDP_WROT1_SOF 135 #define CMDQ_EVENT_MDP_MDP_FG0_SOF 136 #define CMDQ_EVENT_MDP_MDP_FG1_SOF 137 #define CMDQ_EVENT_MDP_MDP_DLI_ASYNC0_SOF 138 #define CMDQ_EVENT_MDP_MDP_DLI_ASYNC1_SOF 139 #define CMDQ_EVENT_MDP_MDP_DLO_ASYNC0_SOF 140 #define CMDQ_EVENT_MDP_MDP_DLO_ASYNC1_SOF 141 #define CMDQ_EVENT_MDP_MDP_RSZ2_SOF 142 #define CMDQ_EVENT_MDP_MDP_RSZ3_SOF 143 #define CMDQ_EVENT_MDP_MDP_WROT2_SOF 144 #define CMDQ_EVENT_MDP_MDP_WROT3_SOF 145 #define CMDQ_EVENT_MDP_MDP_WROT3_FRAME_DONE 146 #define CMDQ_EVENT_MDP_MDP_WROT2_FRAME_DONE 147 #define CMDQ_EVENT_MDP_MDP_WROT1_FRAME_DONE 148 #define CMDQ_EVENT_MDP_MDP_WROT0_FRAME_DONE 149 #define CMDQ_EVENT_MDP_MDP_TDSHP1_FRAME_DONE 150 #define CMDQ_EVENT_MDP_MDP_TDSHP0_FRAME_DONE 151 #define CMDQ_EVENT_MDP_MDP_RSZ3_FRAME_DONE 152 #define CMDQ_EVENT_MDP_MDP_RSZ2_FRAME_DONE 153 #define CMDQ_EVENT_MDP_MDP_RSZ1_FRAME_DONE 154 #define CMDQ_EVENT_MDP_MDP_RSZ0_FRAME_DONE 155 #define CMDQ_EVENT_MDP_MDP_RDMA1_FRAME_DONE 156 #define CMDQ_EVENT_MDP_MDP_RDMA0_FRAME_DONE 157 #define CMDQ_EVENT_MDP_MDP_HDR1_FRAME_DONE 158 #define CMDQ_EVENT_MDP_MDP_HDR0_FRAME_DONE 159 #define CMDQ_EVENT_MDP_MDP_FG1_FRAME_DONE 160 #define CMDQ_EVENT_MDP_MDP_FG0_FRAME_DONE 161 #define CMDQ_EVENT_MDP_MDP_COLOR1_FRAME_DONE 162 #define CMDQ_EVENT_MDP_MDP_COLOR0_FRAME_DONE 163 #define CMDQ_EVENT_MDP_MDP_AAL1_FRAME_DONE 164 #define CMDQ_EVENT_MDP_MDP_AAL0_FRAME_DONE 165 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 166 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 167 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 168 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 169 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 170 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 171 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 172 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 173 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 174 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 175 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 176 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 177 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 178 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 179 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 180 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 181 #define CMDQ_EVENT_MDP_MDP_WROT3_SW_RST_DONE_ENG_EVENT 182 #define CMDQ_EVENT_MDP_MDP_WROT2_SW_RST_DONE_ENG_EVENT 183 #define CMDQ_EVENT_MDP_MDP_WROT1_SW_RST_DONE_ENG_EVENT 184 #define CMDQ_EVENT_MDP_MDP_WROT0_SW_RST_DONE_ENG_EVENT 185 #define CMDQ_EVENT_MDP_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 186 #define CMDQ_EVENT_MDP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 187 #define CMDQ_EVENT_MDP_BUF_UNDERFUN_ENG_EVENT_0 188 #define CMDQ_EVENT_MDP_BUF_UNDERFUN_ENG_EVENT_1 189 #define CMDQ_EVENT_MDP_BUF_UNDERFUN_ENG_EVENT_2 190 #define CMDQ_EVENT_MDP_BUF_UNDERFUN_ENG_EVENT_3 191 #define CMDQ_EVENT_CAM1_ISP_FRAME_DONE_A 257 #define CMDQ_EVENT_CAM1_ISP_FRAME_DONE_B 258 #define CMDQ_EVENT_CAM1_CAMSV1_PASS1_DONE 262 #define CMDQ_EVENT_CAM1_CAMSV2_PASS1_DONE 263 #define CMDQ_EVENT_CAM1_CAMSV3_PASS1_DONE 264 #define CMDQ_EVENT_CAM1_SENINF_CAM0_FIFO_FULL 269 #define CMDQ_EVENT_CAM1_SENINF_CAM1_FIFO_FULL 270 #define CMDQ_EVENT_CAM1_SENINF_CAM2_FIFO_FULL 271 #define CMDQ_EVENT_CAM1_SENINF_CAM3_FIFO_FULL 272 #define CMDQ_EVENT_CAM1_SENINF_CAM4_FIFO_FULL 273 #define CMDQ_EVENT_CAM1_SENINF_CAM5_FIFO_FULL 274 #define CMDQ_EVENT_CAM1_SENINF_CAM6_FIFO_FULL 275 #define CMDQ_EVENT_CAM1_SENINF_CAM7_FIFO_FULL 276 #define CMDQ_EVENT_CAM1_TG_OVRUN_A_INT 282 #define CMDQ_EVENT_CAM1_DMA_R1_ERROR_A_INT 283 #define CMDQ_EVENT_CAM1_TG_OVRUN_B_INT 284 #define CMDQ_EVENT_CAM1_DMA_R1_ERROR_B_INT 285 #define CMDQ_EVENT_CAM1_TG_GRABERR_A_INT 292 #define CMDQ_EVENT_CAM1_CQ_VR_SNAP_A_INT 293 #define CMDQ_EVENT_CAM1_TG_GRABERR_B_INT 294 #define CMDQ_EVENT_CAM1_CQ_VR_SNAP_B_INT 295 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_0 384 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_1 385 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_2 386 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_3 387 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_4 388 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_5 389 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_6 390 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_7 391 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_8 392 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_9 393 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_10 394 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_11 395 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_12 396 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_13 397 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_14 398 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_15 399 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_16 400 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_17 401 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_18 402 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_19 403 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_20 404 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_21 405 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_22 406 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_23 407 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_24 408 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_25 409 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_26 410 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_27 411 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_28 412 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_29 413 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_30 414 #define CMDQ_EVENT_VDEC1_VDEC_EVENT_31 415 #define CMDQ_EVENT_GCE_SMI_ALL_EVENT_0 898 #define CMDQ_EVENT_GCE_SMI_ALL_EVENT_1 899 #define CMDQ_EVENT_GCE_SMI_ALL_EVENT_2 900 /* CMDQ sw tokens * Following definitions are gce sw token which may use by clients * event operation API. * Note that token 512 to 639 may set secure */ /* end of hw event and begin of sw token */ #define CMDQ_MAX_HW_EVENT 512 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 514 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 515 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 516 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 517 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 518 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 519 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 520 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 521 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 522 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 523 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 524 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 525 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 526 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 527 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 528 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 529 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 530 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 531 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 532 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 533 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 534 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 535 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 536 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 537 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 538 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 539 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 540 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 541 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 542 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 543 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 544 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 545 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 546 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 547 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 548 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 549 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 550 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 551 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 552 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 553 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 554 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 555 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 556 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 557 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 558 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 559 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 560 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 561 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 562 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 563 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 564 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 565 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 566 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 567 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 568 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 569 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 570 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 571 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 572 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 573 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_61 574 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_62 575 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_63 576 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_64 577 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_65 578 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_66 579 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_67 580 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_68 581 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_69 582 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_70 583 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_71 584 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_72 585 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_73 586 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_74 587 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_75 588 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_76 589 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_77 590 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_78 591 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_79 592 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_80 593 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_81 594 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_82 595 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_83 596 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_84 597 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_85 598 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_86 599 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_87 600 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_88 601 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_89 602 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_90 603 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_91 604 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_92 605 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_93 606 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_94 607 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_95 608 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_96 609 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_97 610 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_98 611 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_99 612 #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_100 613 /* MML sw tokens */ #define CMDQ_SYNC_TOKEN_MML_WROT0_PIPE 630 #define CMDQ_SYNC_TOKEN_MML_WROT2_PIPE 631 #define CMDQ_SYNC_TOKEN_MML_IR_MML_READY 632 #define CMDQ_SYNC_TOKEN_MML_IR_DISP_READY 633 #define CMDQ_SYNC_TOKEN_MML_MML_STOP 634 /* Config thread notify trigger thread */ #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 /* Trigger thread notify config thread */ #define CMDQ_SYNC_TOKEN_STREAM_EOF 641 /* Block Trigger thread until the ESD check finishes. */ #define CMDQ_SYNC_TOKEN_ESD_EOF 642 #define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 /* check CABC setup finish */ #define CMDQ_SYNC_TOKEN_CABC_EOF 644 /*VFP period token for Msync*/ #define CMDQ_SYNC_TOKEN_VFP_PERIOD 645 /* Notify normal CMDQ there are some secure task done * MUST NOT CHANGE, this token sync with secure world */ #define CMDQ_SYNC_SECURE_THR_EOF 647 /* CMDQ use sw token */ #define CMDQ_SYNC_TOKEN_USER_0 649 #define CMDQ_SYNC_TOKEN_USER_1 650 #define CMDQ_SYNC_TOKEN_POLL_MONITOR 651 #define CMDQ_SYNC_TOKEN_TPR_LOCK 652 /* ISP sw token */ #define CMDQ_SYNC_TOKEN_MSS 665 #define CMDQ_SYNC_TOKEN_MSF 666 /* TZMP sw token */ #define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 653 #define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 654 #define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 676 #define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 677 #define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 678 #define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 679 /* PREBUILT sw token */ #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 682 #define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 685 #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 688 #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 691 #define CMDQ_SYNC_TOKEN_DISP_VA_START 692 #define CMDQ_SYNC_TOKEN_DISP_VA_END 693 /* histogram sw token */ #define CMDQ_SYNC_TOKEN_HISTOGRAM_MDP_WAIT 694 #define CMDQ_SYNC_TOKEN_HISTOGRAM_MDP_SET 695 #define CMDQ_SYNC_TOKEN_HISTOGRAM_VENC_WAIT 696 #define CMDQ_SYNC_TOKEN_HISTOGRAM_VENC_SET 697 /* GPR access tokens (for HW register backup) * There are 15 32-bit GPR, 3 GPR form a set * (64-bit for address, 32-bit for value) * MUST NOT CHANGE, these tokens sync with MDP */ #define CMDQ_SYNC_TOKEN_GPR_SET_0 700 #define CMDQ_SYNC_TOKEN_GPR_SET_1 701 #define CMDQ_SYNC_TOKEN_GPR_SET_2 702 #define CMDQ_SYNC_TOKEN_GPR_SET_3 703 #define CMDQ_SYNC_TOKEN_GPR_SET_4 704 /* Resource lock event to control resource in GCE thread */ #define CMDQ_SYNC_RESOURCE_WROT0 710 #define CMDQ_SYNC_RESOURCE_WROT1 711 /* VENC sw token */ #define CMDQ_SYNC_TOKEN_VENC_NORM_LOCK 732 #define CMDQ_SYNC_TOKEN_VENC_SEC_LOCK 733 /* event for gpr timer, used in sleep and poll with timeout */ #define CMDQ_TOKEN_GPR_TIMER_R0 994 #define CMDQ_TOKEN_GPR_TIMER_R1 995 #define CMDQ_TOKEN_GPR_TIMER_R2 996 #define CMDQ_TOKEN_GPR_TIMER_R3 997 #define CMDQ_TOKEN_GPR_TIMER_R4 998 #define CMDQ_TOKEN_GPR_TIMER_R5 999 #define CMDQ_TOKEN_GPR_TIMER_R6 1000 #define CMDQ_TOKEN_GPR_TIMER_R7 1001 #define CMDQ_TOKEN_GPR_TIMER_R8 1002 #define CMDQ_TOKEN_GPR_TIMER_R9 1003 #define CMDQ_TOKEN_GPR_TIMER_R10 1004 #define CMDQ_TOKEN_GPR_TIMER_R11 1005 #define CMDQ_TOKEN_GPR_TIMER_R12 1006 #define CMDQ_TOKEN_GPR_TIMER_R13 1007 #define CMDQ_TOKEN_GPR_TIMER_R14 1008 #define CMDQ_TOKEN_GPR_TIMER_R15 1009 #define CMDQ_EVENT_MAX 0x3FF /* CMDQ sw tokens END */ #endif