// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
/*
 * Device Tree defines for LCM settings
 * Copyright (c) 2021 MediaTek Inc.
 */

#include "mtk_lcm_settings.h"
#include "round_corner/nt36672c_fhdp_shenchao_rc.dtsi"

&pio {
	nt36672c_fhdp_dphy_vdo_shenchao_120hz: nt36672c-fhdp-dphy-vdo-shenchao-120hz {
		compatible = "mediatek,nt36672c_fhdp_dphy_vdo_shenchao_120hz";
		lcm-version = <0>;

		lcm-params{
			compatible = "mediatek,lcm-params";
			lcm-params-name = "nt36672c-fhdp-dphy-vdo-shenchao-120hz";
			lcm-params-types = <MTK_LCM_FUNC_DSI>;
			lcm-params-resolution = <1080 2400>;
			lcm-params-physical-width = <64>;
			lcm-params-physical-height = <129>;

			/* lk support */
			lcm-params-lk {
				compatible = "mediatek,lcm-params-lk";
				lcm-params-lk-ctrl;
				lcm-params-lk-lcm-if;
				lcm-params-lk-lcm-cmd-if;
				lcm-params-lk-io-select-mode;
				lcm-params-lk-lcm-x;
				lcm-params-lk-lcm-y;
				lcm-params-lk-virtual-resolution = <0 0>;
				lcm-params-lk-od-table-size;
				lcm-params-lk-od-table;
			};

			lcm-params-lk-round-corner {
				compatible = "mediatek,lcm-params-lk-round-corner";
				lcm-params-lk-rc-round-corner-en = <1>;
				lcm-params-lk-rc-round-corner-pattern =
					<&nt36672c_fhdp_shechao_round_corner_pattern>;
			};

			lcm-params-dbi {
				compatible = "mediatek,lcm-params-dbi";
				/* future reserved for dbi interfaces */
			};

			lcm-params-dpi {
				compatible = "mediatek,lcm-params-dpi";
				/* future reserved for dpi interfaces */
			};

			lcm-params-dsi {
				compatible = "mediatek,lcm-params-dsi";
				lcm-params-dsi-density = <480>;
				lcm-params-dsi-lanes = <4>;
				lcm-params-dsi-format = <MTK_MIPI_DSI_FMT_RGB888>;
				lcm-params-dsi-phy-type = <MTK_LCM_MIPI_DPHY>;
				lcm-params-dsi-mode-flags = <MTK_MIPI_DSI_MODE_VIDEO>,
						<MTK_MIPI_DSI_MODE_VIDEO_SYNC_PULSE>,
						<MTK_MIPI_DSI_MODE_LPM>,
						<MTK_MIPI_DSI_MODE_EOT_PACKET>,
						<MTK_MIPI_DSI_CLOCK_NON_CONTINUOUS>;
				lcm-params-dsi-mode-flags-doze-on;
				lcm-params-dsi-mode-flags-doze-off;

				lcm-params-dsi-need-fake-resolution;
				lcm-params-dsi-fake-resolution = <1080 2400>;

				lcm-gpio-size = <3>;
				lcm-gpio-list = <&pio 42 0>, /* gpio list*/
					<&pio 28 0>,
					<&pio 29 0>;
				pinctrl-names = "gpio1", "gpio2", "gpio3";
				pinctrl-0;
				pinctrl-1;
				pinctrl-2;
				status = "okay";

				lcm-params-dsi-default-mode = <0>;
				lcm-params-dsi-mode-count = <3>;
				lcm-params-dsi-mode-list =
					<0 1080 2400 60>,
					<1 1080 2400 90>,
					<2 1080 2400 120>;

				lcm-params-dsi-fps-0-1080-2400-60 {
					compatible = "mediatek,lcm-dsi-fps-0-1080-2400-60";
					lcm-params-dsi-voltage;
					lcm-params-dsi-fake = <0>;

					/* drm-display-mode */
					lcm-params-dsi-vrefresh = <60>;
					lcm-params-dsi-vertical-sync-active = <10>;
					lcm-params-dsi-vertical-backporch = <10>;
					lcm-params-dsi-vertical-frontporch = <2546>;
					lcm-params-dsi-vertical-active-line = <2400>;
					lcm-params-dsi-horizontal-sync-active = <22>;
					lcm-params-dsi-horizontal-backporch = <22>;
					lcm-params-dsi-horizontal-frontporch = <165>;
					lcm-params-dsi-horizontal-active-pixel = <1080>;
					lcm-params-dsi-pixel-clock = <382678>;
					lcm-params-dsi-hskew;
					lcm-params-dsi-vscan;

					/* mtk-panel-params */
					lcm-params-dsi-pll-clock = <591>;
					lcm-params-dsi-data-rate = <1182>;
					lcm-params-dsi-vfp-for-low-power = <4205>;
					lcm-params-dsi-ssc-enable;
					lcm-params-dsi-ssc-range;
					lcm-params-dsi-lcm-color-mode;
					lcm-params-dsi-min-luminance;
					lcm-params-dsi-average-luminance;
					lcm-params-dsi-max-luminance;
					lcm-params-dsi-round-corner-en = <1>;
					lcm-params-dsi-round-corner-pattern =
						<&nt36672c_fhdp_shechao_round_corner_pattern>;
					lcm-params-dsi-physical-width-um;
					lcm-params-dsi-physical-height-um;
					lcm-params-dsi-output-mode =
						<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
					lcm-params-dsi-lcm-cmd-if;
					lcm-params-dsi-hbm-en-time;
					lcm-params-dsi-hbm-dis-time;
					lcm-params-dsi-lcm-index;
					lcm-params-dsi-wait-sof-before-dec-vfp;
					lcm-params-dsi-doze-delay;
					lcm-params-dsi-lfr-enable = <1>;
					lcm-params-dsi-lfr-minimum-fps = <60>;
					lcm-params-dsi-msync2-enable = <1>;
					lcm-params-dsi-max-vfp-for-msync = <3995>;

					/* lane swap */
					lcm-params-dsi-lane-swap-en;
					lcm-params-dsi-lane-swap0;
					lcm-params-dsi-lane-swap1;

					/* esd check table */
					lcm-params-dsi-cust-esd-check = <0>;
					lcm-params-dsi-esd-check-enable = <1>;
					lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
					lcm-params-dsi-lcm-esd-check-table1;
					lcm-params-dsi-lcm-esd-check-table2;

					/* fpga support */
					lcm-params-dsi-fpga-params-0-1080-2400-60 {
						compatible = "mediatek,lcm-dsi-fpga-params";

						lcm-params-dsi-lk-pll-div = <0 0>;
						lcm-params-dsi-lk-fbk-div = <1>;
					};

					/* lk support */
					lcm-params-dsi-lk-params-0-1080-2400-60 {
						compatible = "mediatek,lcm-dsi-lk-params";
						lcm-params-dsi-lk-mode =
							<MTK_LK_SYNC_PULSE_VDO_MODE>;
						lcm-params-dsi-lk-switch-mode = <MTK_LK_CMD_MODE>;
						lcm-params-dsi-lk-switch-mode-enable = <0>;
						lcm-params-dsi-lk-dsi-wmem-conti;
						lcm-params-dsi-lk-dsi-rmem-conti;
						lcm-params-dsi-lk-vc-num;
						lcm-params-dsi-lk-data-format =
							<MTK_LCM_COLOR_ORDER_RGB>,
							<MTK_LCM_DSI_TRANS_SEQ_MSB_FIRST>,
							<MTK_LCM_DSI_PADDING_ON_LSB>,
							<MTK_LCM_DSI_FORMAT_RGB888>;
						lcm-params-dsi-lk-intermediat-buffer-num;
						lcm-params-dsi-lk-ps =
							<MTK_LCM_PACKED_PS_24BIT_RGB888>;
						lcm-params-dsi-lk-word-count;
						lcm-params-dsi-lk-packet-size = <256>;

						lcm-params-dsi-lk-horizontal-blanking-pixel;
						lcm-params-dsi-lk-bllp;
						lcm-params-dsi-lk-line-byte;
						lcm-params-dsi-lk-horizontal-sync-active-byte;
						lcm-params-dsi-lk-horizontal-backporch-byte;
						lcm-params-dsi-lk-horizontal-frontporch-byte;
						lcm-params-dsi-lk-rgb-byte;
						lcm-params-dsi-lk-horizontal-sync-active-word-count;
						lcm-params-dsi-lk-horizontal-backporch-word-count;
						lcm-params-dsi-lk-horizontal-frontporch-word-count;
						lcm-params-dsi-lk-pll-select;
						lcm-params-dsi-lk-pll-div;
						lcm-params-dsi-lk-fbk-div;
						lcm-params-dsi-lk-fbk-sel;
						lcm-params-dsi-lk-rg = <0 0 0>;
						lcm-params-dsi-lk-dsi-clock;
						lcm-params-dsi-lk-ssc-disable = <1>;
						lcm-params-dsi-lk-ssc-range;
						lcm-params-dsi-lk-compatibility-for-nvk;
						lcm-params-dsi-lk-cont-clock;
						lcm-params-dsi-lk-ufoe-enable;
						lcm-params-dsi-lk-ufoe-params = <0 0 0 0>;
						lcm-params-dsi-lk-edp-panel;
						lcm-params-dsi-lk-lcm-int-te-monitor;
						lcm-params-dsi-lk-lcm-int-te-period;
						lcm-params-dsi-lk-lcm-ext-te-monitor;
						lcm-params-dsi-lk-lcm-ext-te-period;
						lcm-params-dsi-lk-noncont-clock;
						lcm-params-dsi-lk-noncont-clock-period;
						lcm-params-dsi-lk-clk-lp-per-line-enable = <0>;
						lcm-params-dsi-lk-dual-dsi-type;
						lcm-params-dsi-lk-mixmode-enable;
						lcm-params-dsi-lk-mixmode-mipi-clock;
						lcm-params-dsi-lk-pwm-fps;
						lcm-params-dsi-lk-pll-clock-lp;
						lcm-params-dsi-lk-ulps-sw-enable;
						lcm-params-dsi-lk-null-packet-en;
						lcm-params-dsi-lk-vact-fps = <120>;
						lcm-params-dsi-lk-send-frame-enable;
						lcm-params-dsi-lk-lfr-enable;
						lcm-params-dsi-lk-lfr-mode;
						lcm-params-dsi-lk-lfr-type;
						lcm-params-dsi-lk-lfr-skip-num;
						lcm-params-dsi-lk-ext-te-edge;
						lcm-params-dsi-lk-eint-disable;
						lcm-params-dsi-lk-phy-sel = <0 0 0 0>;
					};

					lcm-params-dsi-dsc-params-0-1080-2400-60 {
						compatible =
							"mediatek,lcm-params-dsi-dsc-params";
						lcm-params-dsi-dsc-enable = <1>;
						lcm-params-dsi-dsc-enable-lk = <1>;
						lcm-params-dsi-dsc-ver = <17>;
						lcm-params-dsi-dsc-slice-mode = <1>;
						lcm-params-dsi-dsc-rgb-swap = <0>;
						lcm-params-dsi-dsc-cfg = <34>;
						lcm-params-dsi-dsc-rct-on = <1>;
						lcm-params-dsi-dsc-bit-per-channel = <8>;
						lcm-params-dsi-dsc-line-buf-depth = <9>;
						lcm-params-dsi-dsc-bp-enable = <1>;
						lcm-params-dsi-dsc-bit-per-pixel = <128>;
						lcm-params-dsi-dsc-pic-height = <2400>;
						lcm-params-dsi-dsc-pic-width = <1080>;
						lcm-params-dsi-dsc-slice-height = <8>;
						lcm-params-dsi-dsc-slice-width = <540>;
						lcm-params-dsi-dsc-chunk-size = <540>;
						lcm-params-dsi-dsc-xmit-delay = <170>;
						lcm-params-dsi-dsc-dec-delay = <526>;
						lcm-params-dsi-dsc-scale-value = <32>;
						lcm-params-dsi-dsc-increment-interval = <43>;
						lcm-params-dsi-dsc-decrement-interval = <7>;
						lcm-params-dsi-dsc-line-bpg-offset = <12>;
						lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
						lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
						lcm-params-dsi-dsc-initial-offset = <6144>;
						lcm-params-dsi-dsc-final-offset = <7072>;
						lcm-params-dsi-dsc-flatness-minqp = <3>;
						lcm-params-dsi-dsc-flatness-maxqp = <12>;
						lcm-params-dsi-dsc-rc-model-size = <8192>;
						lcm-params-dsi-dsc-rc-edge-factor = <6>;
						lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
						lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
						lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
						lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
					};

					lcm-params-dsi-phy-timcon-params-0-1080-2400-60 {
						compatible =
							"mediatek,lcm-params-dsi-phy-timcon";
						lcm-params-dsi-phy-timcon-hs-trail;
						lcm-params-dsi-phy-timcon-hs-prpr;
						lcm-params-dsi-phy-timcon-hs-zero;
						lcm-params-dsi-phy-timcon-lpx;
						lcm-params-dsi-phy-timcon-ta-get;
						lcm-params-dsi-phy-timcon-ta-sure;
						lcm-params-dsi-phy-timcon-ta-go;
						lcm-params-dsi-phy-timcon-da-hs-exit;
						lcm-params-dsi-phy-timcon-clk-trail;
						lcm-params-dsi-phy-timcon-cont-det;
						lcm-params-dsi-phy-timcon-da-hs-sync;
						lcm-params-dsi-phy-timcon-clk-zero;
						lcm-params-dsi-phy-timcon-clk-prpr;
						lcm-params-dsi-phy-timcon-clk-exit;
						lcm-params-dsi-phy-timcon-clk-post;

						/* lk support */
						lcm-params-dsi-phy-timcon-lk-hs-trail;
						lcm-params-dsi-phy-timcon-lk-hs-zero;
						lcm-params-dsi-phy-timcon-lk-hs-prpr;
						lcm-params-dsi-phy-timcon-lk-lpx;
						lcm-params-dsi-phy-timcon-lk-ta-sack;
						lcm-params-dsi-phy-timcon-lk-ta-get;
						lcm-params-dsi-phy-timcon-lk-ta-sure;
						lcm-params-dsi-phy-timcon-lk-ta-go;
						lcm-params-dsi-phy-timcon-lk-clk-trail;
						lcm-params-dsi-phy-timcon-lk-clk-zero;
						lcm-params-dsi-phy-timcon-lk-lpx-wait;
						lcm-params-dsi-phy-timcon-lk-cont-det;
						lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
						lcm-params-dsi-phy-timcon-lk-clk-hs-post;
						lcm-params-dsi-phy-timcon-lk-da-hs-exit;
						lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
					};

					lcm-params-dsi-dyn-params-0-1080-2400-60 {
						compatible =
							"mediatek,lcm-params-dsi-dyn";
						lcm-params-dsi-dyn-switch-en = <1>;
						lcm-params-dsi-dyn-pll-clk = <581>;
						lcm-params-dsi-dyn-data-rate;
						lcm-params-dsi-dyn-vsa;
						lcm-params-dsi-dyn-vbp;
						lcm-params-dsi-dyn-vfp = <2528>;
						lcm-params-dsi-dyn-vfp-lp-dyn = <4178>;
						lcm-params-dsi-dyn-vac;
						lcm-params-dsi-dyn-hsa;
						lcm-params-dsi-dyn-hbp;
						lcm-params-dsi-dyn-hfp = <161>;
						lcm-params-dsi-dyn-hac;
						lcm-params-dsi-dyn-max-vfp-for-msync-dyn = <3995>;
					};

					lcm-params-dsi-dyn-fps-params-0-1080-2400-60 {
						compatible =
							"mediatek,lcm-params-dsi-dyn-fps";
						lcm-params-dsi-dyn-fps-switch-en = <1>;
						lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
						lcm-params-dsi-dyn-fps-data-rate;
						lcm-params-dsi-dyn-fps-dfps-cmd-table0;
						lcm-params-dsi-dyn-fps-dfps-cmd-table1;
						lcm-params-dsi-dyn-fps-dfps-cmd-table2;
						lcm-params-dsi-dyn-fps-dfps-cmd-table3;
						lcm-params-dsi-dyn-fps-dfps-cmd-table4;
						lcm-params-dsi-dyn-fps-dfps-cmd-table5;
						lcm-params-dsi-dyn-fps-dfps-cmd-table6;
						lcm-params-dsi-dyn-fps-dfps-cmd-table7;
						lcm-params-dsi-dyn-fps-dfps-cmd-table8;
						lcm-params-dsi-dyn-fps-dfps-cmd-table9;
						lcm-params-dsi-dyn-fps-dfps-cmd-table10;
						lcm-params-dsi-dyn-fps-dfps-cmd-table11;
						lcm-params-dsi-dyn-fps-dfps-cmd-table12;
						lcm-params-dsi-dyn-fps-dfps-cmd-table13;
						lcm-params-dsi-dyn-fps-dfps-cmd-table14;
						lcm-params-dsi-dyn-fps-dfps-cmd-table15;
						lcm-params-dsi-dyn-fps-dfps-cmd-table16;
						lcm-params-dsi-dyn-fps-dfps-cmd-table17;
						lcm-params-dsi-dyn-fps-dfps-cmd-table18;
						lcm-params-dsi-dyn-fps-dfps-cmd-table19;
					};
				};

				lcm-params-dsi-fps-1-1080-2400-90 {
					compatible = "mediatek,lcm-dsi-fps-1-1080-2400-90";
					lcm-params-dsi-voltage;
					lcm-params-dsi-fake = <0>;

					/* drm-display-mode */
					lcm-params-dsi-vrefresh = <90>;
					lcm-params-dsi-vertical-sync-active = <10>;
					lcm-params-dsi-vertical-backporch = <10>;
					lcm-params-dsi-vertical-frontporch = <892>;
					lcm-params-dsi-vertical-active-line = <2400>;
					lcm-params-dsi-horizontal-sync-active = <22>;
					lcm-params-dsi-horizontal-backporch = <22>;
					lcm-params-dsi-horizontal-frontporch = <165>;
					lcm-params-dsi-horizontal-active-pixel = <1080>;
					lcm-params-dsi-pixel-clock = <382716>;
					lcm-params-dsi-hskew;
					lcm-params-dsi-vscan;

					/* mtk-panel-params */
					lcm-params-dsi-pll-clock = <591>;
					lcm-params-dsi-data-rate = <1182>;
					lcm-params-dsi-vfp-for-low-power = <2546>;
					lcm-params-dsi-ssc-enable;
					lcm-params-dsi-ssc-range;
					lcm-params-dsi-lcm-color-mode;
					lcm-params-dsi-min-luminance;
					lcm-params-dsi-average-luminance;
					lcm-params-dsi-max-luminance;
					lcm-params-dsi-round-corner-en = <1>;
					lcm-params-dsi-round-corner-pattern =
						<&nt36672c_fhdp_shechao_round_corner_pattern>;
					lcm-params-dsi-physical-width-um;
					lcm-params-dsi-physical-height-um;
					lcm-params-dsi-output-mode =
						<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
					lcm-params-dsi-lcm-cmd-if;
					lcm-params-dsi-hbm-en-time;
					lcm-params-dsi-hbm-dis-time;
					lcm-params-dsi-lcm-index;
					lcm-params-dsi-wait-sof-before-dec-vfp;
					lcm-params-dsi-doze-delay;
					lcm-params-dsi-lfr-enable = <1>;
					lcm-params-dsi-lfr-minimum-fps = <60>;
					lcm-params-dsi-msync2-enable = <1>;
					lcm-params-dsi-max-vfp-for-msync = <3995>;

					/* lane swap */
					lcm-params-dsi-lane-swap-en;
					lcm-params-dsi-lane-swap0;
					lcm-params-dsi-lane-swap1;

					/* esd check table */
					lcm-params-dsi-cust-esd-check = <0>;
					lcm-params-dsi-esd-check-enable = <1>;
					lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
					lcm-params-dsi-lcm-esd-check-table1;
					lcm-params-dsi-lcm-esd-check-table2;

					lcm-params-dsi-dsc-params-1-1080-2400-90 {
						compatible =
							"mediatek,lcm-params-dsi-dsc-params";
						lcm-params-dsi-dsc-enable = <1>;
						lcm-params-dsi-dsc-enable-lk = <0>;
						lcm-params-dsi-dsc-ver = <17>;
						lcm-params-dsi-dsc-slice-mode = <1>;
						lcm-params-dsi-dsc-rgb-swap = <0>;
						lcm-params-dsi-dsc-cfg = <34>;
						lcm-params-dsi-dsc-rct-on = <1>;
						lcm-params-dsi-dsc-bit-per-channel = <8>;
						lcm-params-dsi-dsc-line-buf-depth = <9>;
						lcm-params-dsi-dsc-bp-enable = <1>;
						lcm-params-dsi-dsc-bit-per-pixel = <128>;
						lcm-params-dsi-dsc-pic-height = <2400>;
						lcm-params-dsi-dsc-pic-width = <1080>;
						lcm-params-dsi-dsc-slice-height = <8>;
						lcm-params-dsi-dsc-slice-width = <540>;
						lcm-params-dsi-dsc-chunk-size = <540>;
						lcm-params-dsi-dsc-xmit-delay = <170>;
						lcm-params-dsi-dsc-dec-delay = <526>;
						lcm-params-dsi-dsc-scale-value = <32>;
						lcm-params-dsi-dsc-increment-interval = <43>;
						lcm-params-dsi-dsc-decrement-interval = <7>;
						lcm-params-dsi-dsc-line-bpg-offset = <12>;
						lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
						lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
						lcm-params-dsi-dsc-initial-offset = <6144>;
						lcm-params-dsi-dsc-final-offset = <7072>;
						lcm-params-dsi-dsc-flatness-minqp = <3>;
						lcm-params-dsi-dsc-flatness-maxqp = <12>;
						lcm-params-dsi-dsc-rc-model-size = <8192>;
						lcm-params-dsi-dsc-rc-edge-factor = <6>;
						lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
						lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
						lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
						lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
					};

					lcm-params-dsi-phy-timcon-params-1-1080-2400-90 {
						compatible =
							"mediatek,lcm-params-dsi-phy-timcon";
						lcm-params-dsi-phy-timcon-hs-trail;
						lcm-params-dsi-phy-timcon-hs-prpr;
						lcm-params-dsi-phy-timcon-hs-zero;
						lcm-params-dsi-phy-timcon-lpx;
						lcm-params-dsi-phy-timcon-ta-get;
						lcm-params-dsi-phy-timcon-ta-sure;
						lcm-params-dsi-phy-timcon-ta-go;
						lcm-params-dsi-phy-timcon-da-hs-exit;
						lcm-params-dsi-phy-timcon-clk-trail;
						lcm-params-dsi-phy-timcon-cont-det;
						lcm-params-dsi-phy-timcon-da-hs-sync;
						lcm-params-dsi-phy-timcon-clk-zero;
						lcm-params-dsi-phy-timcon-clk-prpr;
						lcm-params-dsi-phy-timcon-clk-exit;
						lcm-params-dsi-phy-timcon-clk-post;

						/* lk support */
						lcm-params-dsi-phy-timcon-lk-hs-trail;
						lcm-params-dsi-phy-timcon-lk-hs-zero;
						lcm-params-dsi-phy-timcon-lk-hs-prpr;
						lcm-params-dsi-phy-timcon-lk-lpx;
						lcm-params-dsi-phy-timcon-lk-ta-sack;
						lcm-params-dsi-phy-timcon-lk-ta-get;
						lcm-params-dsi-phy-timcon-lk-ta-sure;
						lcm-params-dsi-phy-timcon-lk-ta-go;
						lcm-params-dsi-phy-timcon-lk-clk-trail;
						lcm-params-dsi-phy-timcon-lk-clk-zero;
						lcm-params-dsi-phy-timcon-lk-lpx-wait;
						lcm-params-dsi-phy-timcon-lk-cont-det;
						lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
						lcm-params-dsi-phy-timcon-lk-clk-hs-post;
						lcm-params-dsi-phy-timcon-lk-da-hs-exit;
						lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
					};

					lcm-params-dsi-dyn-params-1-1080-2400-90 {
						compatible =
							"mediatek,lcm-params-dsi-dyn";
						lcm-params-dsi-dyn-switch-en = <1>;
						lcm-params-dsi-dyn-pll-clk = <581>;
						lcm-params-dsi-dyn-data-rate;
						lcm-params-dsi-dyn-vsa;
						lcm-params-dsi-dyn-vbp;
						lcm-params-dsi-dyn-vfp = <879>;
						lcm-params-dsi-dyn-vfp-lp-dyn = <2528>;
						lcm-params-dsi-dyn-vac;
						lcm-params-dsi-dyn-hsa;
						lcm-params-dsi-dyn-hbp;
						lcm-params-dsi-dyn-hfp = <161>;
						lcm-params-dsi-dyn-hac;
						lcm-params-dsi-dyn-max-vfp-for-msync-dyn = <3995>;
					};

					lcm-params-dsi-dyn-fps-params-1-1080-2400-90 {
						compatible =
							"mediatek,lcm-params-dsi-dyn-fps";
						lcm-params-dsi-dyn-fps-switch-en = <1>;
						lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
						lcm-params-dsi-dyn-fps-data-rate;
						lcm-params-dsi-dyn-fps-dfps-cmd-table0;
						lcm-params-dsi-dyn-fps-dfps-cmd-table1;
						lcm-params-dsi-dyn-fps-dfps-cmd-table2;
						lcm-params-dsi-dyn-fps-dfps-cmd-table3;
						lcm-params-dsi-dyn-fps-dfps-cmd-table4;
						lcm-params-dsi-dyn-fps-dfps-cmd-table5;
						lcm-params-dsi-dyn-fps-dfps-cmd-table6;
						lcm-params-dsi-dyn-fps-dfps-cmd-table7;
						lcm-params-dsi-dyn-fps-dfps-cmd-table8;
						lcm-params-dsi-dyn-fps-dfps-cmd-table9;
						lcm-params-dsi-dyn-fps-dfps-cmd-table10;
						lcm-params-dsi-dyn-fps-dfps-cmd-table11;
						lcm-params-dsi-dyn-fps-dfps-cmd-table12;
						lcm-params-dsi-dyn-fps-dfps-cmd-table13;
						lcm-params-dsi-dyn-fps-dfps-cmd-table14;
						lcm-params-dsi-dyn-fps-dfps-cmd-table15;
						lcm-params-dsi-dyn-fps-dfps-cmd-table16;
						lcm-params-dsi-dyn-fps-dfps-cmd-table17;
						lcm-params-dsi-dyn-fps-dfps-cmd-table18;
						lcm-params-dsi-dyn-fps-dfps-cmd-table19;
					};
				};

				lcm-params-dsi-fps-2-1080-2400-120 {
					compatible = "mediatek,lcm-dsi-fps-2-1080-2400-120";
					lcm-params-dsi-voltage;
					lcm-params-dsi-fake = <0>;

					/* drm-display-mode */
					lcm-params-dsi-vrefresh = <120>;
					lcm-params-dsi-vertical-sync-active = <10>;
					lcm-params-dsi-vertical-backporch = <10>;
					lcm-params-dsi-vertical-frontporch = <64>;
					lcm-params-dsi-vertical-active-line = <2400>;
					lcm-params-dsi-horizontal-sync-active = <22>;
					lcm-params-dsi-horizontal-backporch = <22>;
					lcm-params-dsi-horizontal-frontporch = <165>;
					lcm-params-dsi-horizontal-active-pixel = <1080>;
					lcm-params-dsi-pixel-clock = <382678>;
					lcm-params-dsi-hskew;
					lcm-params-dsi-vscan;

					/* mtk-panel-params */
					lcm-params-dsi-pll-clock = <591>;
					lcm-params-dsi-data-rate = <1182>;
					lcm-params-dsi-vfp-for-low-power = <2546>;
					lcm-params-dsi-ssc-enable;
					lcm-params-dsi-ssc-range;
					lcm-params-dsi-lcm-color-mode;
					lcm-params-dsi-min-luminance;
					lcm-params-dsi-average-luminance;
					lcm-params-dsi-max-luminance;
					lcm-params-dsi-round-corner-en = <1>;
					lcm-params-dsi-round-corner-pattern =
						<&nt36672c_fhdp_shechao_round_corner_pattern>;
					lcm-params-dsi-physical-width-um;
					lcm-params-dsi-physical-height-um;
					lcm-params-dsi-output-mode =
						<MTK_LCM_PANEL_DSC_SINGLE_PORT>;
					lcm-params-dsi-lcm-cmd-if;
					lcm-params-dsi-hbm-en-time;
					lcm-params-dsi-hbm-dis-time;
					lcm-params-dsi-lcm-index;
					lcm-params-dsi-wait-sof-before-dec-vfp;
					lcm-params-dsi-doze-delay;
					lcm-params-dsi-lfr-enable = <1>;
					lcm-params-dsi-lfr-minimum-fps = <60>;
					lcm-params-dsi-msync2-enable = <1>;
					lcm-params-dsi-max-vfp-for-msync = <3995>;

					/* lane swap */
					lcm-params-dsi-lane-swap-en;
					lcm-params-dsi-lane-swap0;
					lcm-params-dsi-lane-swap1;

					/* esd check table */
					lcm-params-dsi-cust-esd-check = <0>;
					lcm-params-dsi-esd-check-enable = <1>;
					lcm-params-dsi-lcm-esd-check-table0 = [0A 01 9C];
					lcm-params-dsi-lcm-esd-check-table1;
					lcm-params-dsi-lcm-esd-check-table2;

					lcm-params-dsi-dsc-params-2-1080-2400-120 {
						compatible =
							"mediatek,lcm-params-dsi-dsc-params";
						lcm-params-dsi-dsc-enable = <1>;
						lcm-params-dsi-dsc-enable-lk = <0>;
						lcm-params-dsi-dsc-ver = <17>;
						lcm-params-dsi-dsc-slice-mode = <1>;
						lcm-params-dsi-dsc-rgb-swap = <0>;
						lcm-params-dsi-dsc-cfg = <34>;
						lcm-params-dsi-dsc-rct-on = <1>;
						lcm-params-dsi-dsc-bit-per-channel = <8>;
						lcm-params-dsi-dsc-line-buf-depth = <9>;
						lcm-params-dsi-dsc-bp-enable = <1>;
						lcm-params-dsi-dsc-bit-per-pixel = <128>;
						lcm-params-dsi-dsc-pic-height = <2400>;
						lcm-params-dsi-dsc-pic-width = <1080>;
						lcm-params-dsi-dsc-slice-height = <8>;
						lcm-params-dsi-dsc-slice-width = <540>;
						lcm-params-dsi-dsc-chunk-size = <540>;
						lcm-params-dsi-dsc-xmit-delay = <170>;
						lcm-params-dsi-dsc-dec-delay = <526>;
						lcm-params-dsi-dsc-scale-value = <32>;
						lcm-params-dsi-dsc-increment-interval = <43>;
						lcm-params-dsi-dsc-decrement-interval = <7>;
						lcm-params-dsi-dsc-line-bpg-offset = <12>;
						lcm-params-dsi-dsc-nfl-bpg-offset = <3511>;
						lcm-params-dsi-dsc-slice-bpg-offset = <3255>;
						lcm-params-dsi-dsc-initial-offset = <6144>;
						lcm-params-dsi-dsc-final-offset = <7072>;
						lcm-params-dsi-dsc-flatness-minqp = <3>;
						lcm-params-dsi-dsc-flatness-maxqp = <12>;
						lcm-params-dsi-dsc-rc-model-size = <8192>;
						lcm-params-dsi-dsc-rc-edge-factor = <6>;
						lcm-params-dsi-dsc-rc-quant-incr-limit0 = <11>;
						lcm-params-dsi-dsc-rc-quant-incr-limit1 = <11>;
						lcm-params-dsi-dsc-rc-tgt-offset-hi = <3>;
						lcm-params-dsi-dsc-rc-tgt-offset-lo = <3>;
					};

					lcm-params-dsi-phy-timcon-params-2-1080-2400-120 {
						compatible =
							"mediatek,lcm-params-dsi-phy-timcon";
						lcm-params-dsi-phy-timcon-hs-trail;
						lcm-params-dsi-phy-timcon-hs-prpr;
						lcm-params-dsi-phy-timcon-hs-zero;
						lcm-params-dsi-phy-timcon-lpx;
						lcm-params-dsi-phy-timcon-ta-get;
						lcm-params-dsi-phy-timcon-ta-sure;
						lcm-params-dsi-phy-timcon-ta-go;
						lcm-params-dsi-phy-timcon-da-hs-exit;
						lcm-params-dsi-phy-timcon-clk-trail;
						lcm-params-dsi-phy-timcon-cont-det;
						lcm-params-dsi-phy-timcon-da-hs-sync;
						lcm-params-dsi-phy-timcon-clk-zero;
						lcm-params-dsi-phy-timcon-clk-prpr;
						lcm-params-dsi-phy-timcon-clk-exit;
						lcm-params-dsi-phy-timcon-clk-post;

						/* lk support */
						lcm-params-dsi-phy-timcon-lk-hs-trail;
						lcm-params-dsi-phy-timcon-lk-hs-zero;
						lcm-params-dsi-phy-timcon-lk-hs-prpr;
						lcm-params-dsi-phy-timcon-lk-lpx;
						lcm-params-dsi-phy-timcon-lk-ta-sack;
						lcm-params-dsi-phy-timcon-lk-ta-get;
						lcm-params-dsi-phy-timcon-lk-ta-sure;
						lcm-params-dsi-phy-timcon-lk-ta-go;
						lcm-params-dsi-phy-timcon-lk-clk-trail;
						lcm-params-dsi-phy-timcon-lk-clk-zero;
						lcm-params-dsi-phy-timcon-lk-lpx-wait;
						lcm-params-dsi-phy-timcon-lk-cont-det;
						lcm-params-dsi-phy-timcon-lk-clk-hs-prpr;
						lcm-params-dsi-phy-timcon-lk-clk-hs-post;
						lcm-params-dsi-phy-timcon-lk-da-hs-exit;
						lcm-params-dsi-phy-timcon-lk-clk-hs-exit;
					};

					lcm-params-dsi-dyn-params-2-1080-2400-120 {
						compatible =
							"mediatek,lcm-params-dsi-dyn";
						lcm-params-dsi-dyn-switch-en = <1>;
						lcm-params-dsi-dyn-pll-clk = <581>;
						lcm-params-dsi-dyn-data-rate;
						lcm-params-dsi-dyn-vsa;
						lcm-params-dsi-dyn-vbp;
						lcm-params-dsi-dyn-vfp = <54>;
						lcm-params-dsi-dyn-vfp-lp-dyn = <2528>;
						lcm-params-dsi-dyn-vac;
						lcm-params-dsi-dyn-hsa;
						lcm-params-dsi-dyn-hbp;
						lcm-params-dsi-dyn-hfp = <161>;
						lcm-params-dsi-dyn-hac;
						lcm-params-dsi-dyn-max-vfp-for-msync-dyn = <3995>;
					};

					lcm-params-dsi-dyn-fps-params-2-1080-2400-120 {
						compatible =
							"mediatek,lcm-params-dsi-dyn-fps";
						lcm-params-dsi-dyn-fps-switch-en = <1>;
						lcm-params-dsi-dyn-fps-vact-timing-fps = <120>;
						lcm-params-dsi-dyn-fps-data-rate;
						lcm-params-dsi-dyn-fps-dfps-cmd-table0;
						lcm-params-dsi-dyn-fps-dfps-cmd-table1;
						lcm-params-dsi-dyn-fps-dfps-cmd-table2;
						lcm-params-dsi-dyn-fps-dfps-cmd-table3;
						lcm-params-dsi-dyn-fps-dfps-cmd-table4;
						lcm-params-dsi-dyn-fps-dfps-cmd-table5;
						lcm-params-dsi-dyn-fps-dfps-cmd-table6;
						lcm-params-dsi-dyn-fps-dfps-cmd-table7;
						lcm-params-dsi-dyn-fps-dfps-cmd-table8;
						lcm-params-dsi-dyn-fps-dfps-cmd-table9;
						lcm-params-dsi-dyn-fps-dfps-cmd-table10;
						lcm-params-dsi-dyn-fps-dfps-cmd-table11;
						lcm-params-dsi-dyn-fps-dfps-cmd-table12;
						lcm-params-dsi-dyn-fps-dfps-cmd-table13;
						lcm-params-dsi-dyn-fps-dfps-cmd-table14;
						lcm-params-dsi-dyn-fps-dfps-cmd-table15;
						lcm-params-dsi-dyn-fps-dfps-cmd-table16;
						lcm-params-dsi-dyn-fps-dfps-cmd-table17;
						lcm-params-dsi-dyn-fps-dfps-cmd-table18;
						lcm-params-dsi-dyn-fps-dfps-cmd-table19;
					};
				};
			};
		};

		lcm-ops {
			compatible = "mediatek,lcm-ops";
			lcm-ops-dbi {
				compatible = "mediatek,lcm-ops-dbi";
				/* future reserved for dbi interfaces*/
			};

			lcm-ops-dpi {
				compatible = "mediatek,lcm-ops-dpi";
				/* future reserved for dpi interfaces*/
			};

			lcm-ops-dsi {
				compatible = "mediatek,lcm-ops-dsi";
				prepare-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0f],
					[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
					[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
					[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C0 03],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 11],
						[C1 89 28 00 08 00 AA 02 0E 00],
						[2B 00 07 0D B7 0C B7],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 03 C2 1B A0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 20],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 01 66],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 32 4D],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 69 D1],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F2 64],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F4 64],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F6 64],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F9 64],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 26],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 81 0E],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 84 03],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 86 03],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 88 07],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 27],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E3 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E4 EC],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E5 02],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E6 E3],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E7 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E8 EC],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 E9 02],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 EA 22],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 EB 03],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 EC 32],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 ED 02],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 EE 22],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 2A],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0C 04],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 0F 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 11 E0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 15 0E],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 16 78],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 19 0D],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1A F4],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 37 6E],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 88 76],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 2C],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4D 1E],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4E 04],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4F 00],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9D 1E],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9E 04],
					[MTK_LCM_PHASE_TYPE_HEX_START 01],
						[MTK_LCM_PHASE_HEX_KERNEL],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9F 17],
					[MTK_LCM_PHASE_TYPE_HEX_END 01],
						[MTK_LCM_PHASE_HEX_KERNEL],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF F0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 5A 00],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF E0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 25 02],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4E 02],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 85 02],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF D0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 09 AD],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 20],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 F8 64],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 2A],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 1A F0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 30 5E],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 31 CA],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 34 FE],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 35],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 36 A2],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 37 F8],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 38 37],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 39 A0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 3A 5E],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 D7],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 88 72],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 88 72],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 24],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C6 C0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF E0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 25 00],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4E 02],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 82],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF C0],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9C 11],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 9D 11],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FB 01],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 C0 03],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 51 00],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 35 00],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 53 24],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 55 00],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 FF 10],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 11],
					[MTK_LCM_PHASE_TYPE_HEX_START 02],
						[MTK_LCM_PHASE_HEX_LK],
						[MTK_LCM_PHASE_HEX_KERNEL],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 8c],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 29],
					[MTK_LCM_PHASE_TYPE_HEX_END 02],
						[MTK_LCM_PHASE_HEX_LK],
						[MTK_LCM_PHASE_HEX_KERNEL],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 28],
					[MTK_LCM_TYPE_HEX_END];

				unprepare-table =
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 28],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 10],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 4F 01],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 78],
					[MTK_LCM_TYPE_HEX_END];

				set-display-on-table =
					[MTK_LCM_PHASE_TYPE_HEX_START 02],
						[MTK_LCM_PHASE_HEX_LK],
						[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
					[MTK_LCM_UTIL_TYPE_HEX_TDELAY 01 78],
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 29],
					[MTK_LCM_PHASE_TYPE_HEX_END 02],
						[MTK_LCM_PHASE_HEX_LK],
						[MTK_LCM_PHASE_HEX_LK_DISPLAY_ON_DELAY],
					[MTK_LCM_TYPE_HEX_END];

				lcm-update-table;

				set-backlight-mask = <0xff>;
				set-backlight-cmdq-table =
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER_RUNTIME_INPUT 06],
						[MTK_LCM_INPUT_TYPE_HEX_CURRENT_BACKLIGHT 01 01],
						[02 51 ff],
					[MTK_LCM_TYPE_HEX_END];

				set-backlight-grp-cmdq-table;

				set-aod-light-mask = <0xff>;
				set-aod-light-table;

				ata-id-value-data = [00 00 00];
				ata-check-table =
					[MTK_LCM_CMD_TYPE_HEX_WRITE_BUFFER 02 05 04],
					[MTK_LCM_TYPE_HEX_END];

				compare-id-value-data = [D7];
				compare-id-table = [MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
					[MTK_LCM_UTIL_TYPE_HEX_RESET 01 00],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
					[MTK_LCM_UTIL_TYPE_HEX_RESET 01 01],
					[MTK_LCM_UTIL_TYPE_HEX_MDELAY 01 0a],
					[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM_COUNT 01 01],
					[MTK_LCM_LK_TYPE_HEX_PREPARE_PARAM 05 00 00 01 37 00],
					[MTK_LCM_LK_TYPE_HEX_WRITE_PARAM 00],
					[MTK_LCM_CMD_TYPE_HEX_READ_BUFFER 03 00 01 DA],
					[MTK_LCM_TYPE_HEX_END];

				doze-enable-start-table;

				doze-enable-table;

				doze-disable-table;

				doze-area-table;

				doze-post-disp-on-table;

				hbm-set-cmdq-switch-id;
				hbm-set-cmdq-switch-on;
				hbm-set-cmdq-switch-off;
				hbm-set-cmdq-table;

				/* fps switch cmd for high frame rate feature */
				lcm-ops-dsi-fps-switch-after-poweron {
					compatible =
						"mediatek,lcm-ops-dsi-fps-switch-after-poweron";
					fps-switch-0-1080-2400-60-table;

					fps-switch-1-1080-2400-90-table;

					fps-switch-2-1080-2400-120-table;
				};

				lcm-ops-dsi-fps-switch-before-powerdown {
					compatible =
						"mediatek,lcm-ops-dsi-fps-switch-before-powerdown";
					fps-switch-0-1080-2400-60-table;

					fps-switch-1-1080-2400-90-table;

					fps-switch-2-1080-2400-120-table;
				};
			};
		};
	};
};