/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2022 MediaTek Inc.
 */

#ifndef __MDP_ENGINE_H__
#define __MDP_ENGINE_H__

enum CMDQ_ENG_ENUM {
	/* MDP */
	CMDQ_ENG_MDP_RDMA0,	/* 0 */
	CMDQ_ENG_MDP_RDMA1,	/* 1 */
	CMDQ_ENG_MDP_DLI0_SEL,	/* 2 */
	CMDQ_ENG_MDP_DLI1_SEL,	/* 3 */
	CMDQ_ENG_MDP_FG0,	/* 4 */
	CMDQ_ENG_MDP_FG1,	/* 5 */
	CMDQ_ENG_MDP_HDR0,	/* 6 */
	CMDQ_ENG_MDP_HDR1,	/* 7 */
	CMDQ_ENG_MDP_AAL0,	/* 8 */
	CMDQ_ENG_MDP_AAL1,	/* 9 */
	CMDQ_ENG_MDP_RSZ0,	/* 10 */
	CMDQ_ENG_MDP_RSZ1,	/* 11 */
	CMDQ_ENG_MDP_TDSHP0,	/* 12 */
	CMDQ_ENG_MDP_TDSHP1,	/* 13 */
	CMDQ_ENG_MDP_COLOR0,	/* 14 */
	CMDQ_ENG_MDP_COLOR1,	/* 15 */
	CMDQ_ENG_MDP_DLO0_SOUT,	/* 16 */
	CMDQ_ENG_MDP_DLO1_SOUT,	/* 17 */
	CMDQ_ENG_MDP_WROT0,	/* 18 */
	CMDQ_ENG_MDP_WROT1,	/* 19 */
	CMDQ_ENG_MAX = CMDQ_MAX_ENGINE_COUNT	/* ALWAYS keep at the end */
};

#define MDP_ENG_LARB2 ((1LL << CMDQ_ENG_MDP_RDMA1) | \
		       (1LL << CMDQ_ENG_MDP_WROT1))

#define CMDQ_ENG_MDP_GROUP_BITS	((1LL << CMDQ_ENG_MDP_RDMA0)	| \
				 (1LL << CMDQ_ENG_MDP_RDMA1)	| \
				 (1LL << CMDQ_ENG_MDP_FG0)	| \
				 (1LL << CMDQ_ENG_MDP_FG1)	| \
				 (1LL << CMDQ_ENG_MDP_HDR0)	| \
				 (1LL << CMDQ_ENG_MDP_HDR1)	| \
				 (1LL << CMDQ_ENG_MDP_AAL0)	| \
				 (1LL << CMDQ_ENG_MDP_AAL1)	| \
				 (1LL << CMDQ_ENG_MDP_RSZ0)	| \
				 (1LL << CMDQ_ENG_MDP_RSZ1)	| \
				 (1LL << CMDQ_ENG_MDP_TDSHP0)	| \
				 (1LL << CMDQ_ENG_MDP_TDSHP1)	| \
				 (1LL << CMDQ_ENG_MDP_COLOR0)	| \
				 (1LL << CMDQ_ENG_MDP_COLOR1)	| \
				 (1LL << CMDQ_ENG_MDP_WROT0)	| \
				 (1LL << CMDQ_ENG_MDP_WROT1))

#define CMDQ_ENG_MDP_GROUP_FLAG(flag)   ((flag) & (CMDQ_ENG_MDP_GROUP_BITS))

#define CMDQ_FOREACH_GROUP(ACTION_struct)\
	ACTION_struct(CMDQ_GROUP_MDP, MDP)

#define MDP_GENERATE_ENUM(_enum, _string) _enum,

enum CMDQ_GROUP_ENUM {
	CMDQ_FOREACH_GROUP(MDP_GENERATE_ENUM)
	CMDQ_MAX_GROUP_COUNT,	/* ALWAYS keep at the end */
};

enum MDP_ENG_BASE {
	ENGBASE_MMSYS_CONFIG = 0,
	ENGBASE_MDP_RDMA0,
	ENGBASE_MDP_RDMA1,
	ENGBASE_MDP_FG0,
	ENGBASE_MDP_FG1,
	ENGBASE_MDP_HDR0,
	ENGBASE_MDP_HDR1,
	ENGBASE_MDP_AAL0,
	ENGBASE_MDP_AAL1,
	ENGBASE_MDP_RSZ0,
	ENGBASE_MDP_RSZ1,
	ENGBASE_MDP_TDSHP0,
	ENGBASE_MDP_TDSHP1,
	ENGBASE_MDP_COLOR0,
	ENGBASE_MDP_COLOR1,
	ENGBASE_MDP_WROT0,
	ENGBASE_MDP_WROT1,
	ENGBASE_MMSYS_MUTEX,
	ENGBASE_COUNT
};
#endif				/* __MDP_ENGINE_H__ */