// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2022 MediaTek Inc. */ /dts-v1/; #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include / { model = "MT6835"; compatible = "mediatek,MT6835"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; i2c7 = &i2c7; i2c8 = &i2c8; i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; ovl0 = &disp_ovl0; ovl4 = &disp_ovl1_2l; rdma0 = &disp_rdma0; wdma0 = &disp_wdma0; dsc0 = &disp_dsc0_wrap; dsi0 = &dsi0; rsz0 = &disp_rsz0; color0 = &disp_color0; ccorr0 = &disp_ccorr0; aal0 = &disp_aal0; gamma0 = &disp_gamma0; dither0 = &disp_dither0; postmask0 = &disp_postmask0; c3d0 = &disp_c3d0; mtksmmu0 = &disp_iommu; }; /* chosen */ chosen: chosen { bootargs = "console=tty0 root=/dev/ram \ rcupdate.rcu_expedited=1 \ vmalloc=400M swiotlb=noforce \ transparent_hugepage=never \ 8250.nr_uarts=2 \ firmware_class.path=/vendor/firmware pelt=8 \ androidboot.hardware=mt6835 \ loop.max_part=7"; kaslr-seed = <0 0>; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0000>; performance-domains = <&performance 0>; enable-method = "psci"; capacity-dmips-mhz = <383>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0100>; performance-domains = <&performance 0>; enable-method = "psci"; capacity-dmips-mhz = <383>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0200>; performance-domains = <&performance 0>; enable-method = "psci"; capacity-dmips-mhz = <383>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0300>; performance-domains = <&performance 0>; enable-method = "psci"; capacity-dmips-mhz = <383>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu4: cpu@4 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0400>; performance-domains = <&performance 0>; enable-method = "psci"; capacity-dmips-mhz = <383>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu5: cpu@5 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0500>; performance-domains = <&performance 0>; enable-method = "psci"; capacity-dmips-mhz = <383>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu6: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0600>; performance-domains = <&performance 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu7: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0700>; performance-domains = <&performance 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff &system_mem &system_pll &system_bus &s2idle>; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; core4 { cpu = <&cpu4>; }; core5 { cpu = <&cpu5>; }; }; cluster1 { core0 { cpu = <&cpu6>; }; core1 { cpu = <&cpu7>; }; }; }; idle-states { entry-method = "arm,psci"; cpuoff_l: cpuoff_l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010000>; local-timer-stop; entry-latency-us = <50>; exit-latency-us = <100>; min-residency-us = <1600>; }; cpuoff_b: cpuoff_b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010000>; local-timer-stop; entry-latency-us = <50>; exit-latency-us = <100>; min-residency-us = <1400>; }; clusteroff_l: clusteroff_l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; entry-latency-us = <100>; exit-latency-us = <250>; min-residency-us = <2100>; }; clusteroff_b: clusteroff_b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; entry-latency-us = <100>; exit-latency-us = <250>; min-residency-us = <1900>; }; mcusysoff: mcusysoff { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010007>; local-timer-stop; entry-latency-us = <450>; exit-latency-us = <600>; min-residency-us = <4000>; }; system_mem: system_mem { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0101000f>; local-timer-stop; entry-latency-us = <700>; exit-latency-us = <850>; min-residency-us = <4000>; }; system_pll: system_pll { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0101001f>; local-timer-stop; entry-latency-us = <800>; exit-latency-us = <950>; min-residency-us = <4000>; }; system_bus: system_bus { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0101007f>; local-timer-stop; entry-latency-us = <1300>; exit-latency-us = <2800>; min-residency-us = <4000>; }; s2idle: s2idle { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x010180ff>; local-timer-stop; entry-latency-us = <10000>; exit-latency-us = <10000>; min-residency-us = <4294967295>; }; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; gic: interrupt-controller { compatible = "arm,gic-v3"; #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; #redistributor-regions = <1>; interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x0c000000 0 0x40000>, // distributor <0 0x0c040000 0 0x200000>; // redistributor interrupts = ; }; cpuhvfs: cpuhvfs@114400 { compatible = "mediatek,cpufreq-hybrid"; reg = <0 0x00114400 0 0xc00>, <0 0x0011bc00 0 0x1400>, <0 0x00112800 0 0x1800>, <0 0x00114f40 0 0xc0>; reg-names = "USRAM", "CSRAM", "ESRAM"; cslog-range = <0x03d0>, <0x0fa0>; tbl-off = <4>, <76>, <148>; /* pll mcucfg */ mcucfg-ver = <0>; apmixedsys = <&cpu_pll>; clk-div-base = <&cpu_mcucfg>; pll-con = <0x20c>, <0x21c>, <0x23c>; clk-div = <0xa2a0>, <0xa2a4>, <0xa2e0>; /* leakage info */ nvmem-cells = <&lkginfo>; nvmem-cell-names = "lkginfo"; }; tboard_thermistor1: thermal-ntc1 { compatible = "mediatek,mt6377-tia-ntc"; #thermal-sensor-cells = <0>; temperature-lookup-table = < (-40000) 4397119 (-39000) 4092874 (-38000) 3811717 (-37000) 3551749 (-36000) 3311236 (-35000) 3088599 (-34000) 2882396 (-33000) 2691310 (-32000) 2514137 (-31000) 2349778 (-30000) 2197225 (-29000) 2055558 (-28000) 1923932 (-27000) 1801573 (-26000) 1687773 (-25000) 1581881 (-24000) 1483100 (-23000) 1391113 (-22000) 1305413 (-21000) 1225531 (-20000) 1151037 (-19000) 1081535 (-18000) 1016661 (-17000) 956080 (-16000) 899481 (-15000) 846579 (-14000) 797111 (-13000) 750834 (-12000) 707524 (-11000) 666972 (-10000) 628988 (-9000) 593342 (-8000) 559931 (-7000) 528602 (-6000) 499212 (-5000) 471632 (-4000) 445772 (-3000) 421480 (-2000) 398652 (-1000) 377193 0 357012 1000 338006 2000 320122 3000 303287 4000 287434 5000 272500 6000 258426 7000 245160 8000 232649 9000 220847 10000 209710 11000 199196 12000 189268 13000 179890 14000 171027 15000 162651 16000 154726 17000 147232 18000 140142 19000 133432 20000 127080 21000 121066 22000 115368 23000 109970 24000 104852 25000 100000 26000 95398 27000 91032 28000 86889 29000 82956 30000 79222 31000 75675 32000 72306 33000 69104 34000 66061 35000 63167 36000 60415 37000 57797 38000 55306 39000 52934 40000 50677 41000 48528 42000 46482 43000 44533 44000 42675 45000 40904 46000 39213 47000 37601 48000 36063 49000 34595 50000 33195 51000 31859 52000 30584 53000 29366 54000 28203 55000 27091 56000 26028 57000 25013 58000 24042 59000 23113 60000 22224 61000 21374 62000 20560 63000 19782 64000 19036 65000 18322 66000 17640 67000 16986 68000 16360 69000 15759 70000 15184 71000 14631 72000 14100 73000 13591 74000 13103 75000 12635 76000 12187 77000 11756 78000 11343 79000 10946 80000 10565 81000 10199 82000 9847 83000 9509 84000 9184 85000 8872 86000 8572 87000 8283 88000 8005 89000 7738 90000 7481 91000 7234 92000 6997 93000 6769 94000 6548 95000 6337 96000 6132 97000 5934 98000 5744 99000 5561 100000 5384 101000 5214 102000 5051 103000 4893 104000 4741 105000 4594 106000 4453 107000 4316 108000 4184 109000 4057 110000 3934 111000 3816 112000 3701 113000 3591 114000 3484 115000 3380 116000 3281 117000 3185 118000 3093 119000 3003 120000 2916 121000 2832 122000 2751 123000 2672 124000 2596 125000 2522>; }; tboard_thermistor2: thermal-ntc2 { compatible = "mediatek,mt6377-tia-ntc"; #thermal-sensor-cells = <0>; temperature-lookup-table = < (-40000) 4397119 (-39000) 4092874 (-38000) 3811717 (-37000) 3551749 (-36000) 3311236 (-35000) 3088599 (-34000) 2882396 (-33000) 2691310 (-32000) 2514137 (-31000) 2349778 (-30000) 2197225 (-29000) 2055558 (-28000) 1923932 (-27000) 1801573 (-26000) 1687773 (-25000) 1581881 (-24000) 1483100 (-23000) 1391113 (-22000) 1305413 (-21000) 1225531 (-20000) 1151037 (-19000) 1081535 (-18000) 1016661 (-17000) 956080 (-16000) 899481 (-15000) 846579 (-14000) 797111 (-13000) 750834 (-12000) 707524 (-11000) 666972 (-10000) 628988 (-9000) 593342 (-8000) 559931 (-7000) 528602 (-6000) 499212 (-5000) 471632 (-4000) 445772 (-3000) 421480 (-2000) 398652 (-1000) 377193 0 357012 1000 338006 2000 320122 3000 303287 4000 287434 5000 272500 6000 258426 7000 245160 8000 232649 9000 220847 10000 209710 11000 199196 12000 189268 13000 179890 14000 171027 15000 162651 16000 154726 17000 147232 18000 140142 19000 133432 20000 127080 21000 121066 22000 115368 23000 109970 24000 104852 25000 100000 26000 95398 27000 91032 28000 86889 29000 82956 30000 79222 31000 75675 32000 72306 33000 69104 34000 66061 35000 63167 36000 60415 37000 57797 38000 55306 39000 52934 40000 50677 41000 48528 42000 46482 43000 44533 44000 42675 45000 40904 46000 39213 47000 37601 48000 36063 49000 34595 50000 33195 51000 31859 52000 30584 53000 29366 54000 28203 55000 27091 56000 26028 57000 25013 58000 24042 59000 23113 60000 22224 61000 21374 62000 20560 63000 19782 64000 19036 65000 18322 66000 17640 67000 16986 68000 16360 69000 15759 70000 15184 71000 14631 72000 14100 73000 13591 74000 13103 75000 12635 76000 12187 77000 11756 78000 11343 79000 10946 80000 10565 81000 10199 82000 9847 83000 9509 84000 9184 85000 8872 86000 8572 87000 8283 88000 8005 89000 7738 90000 7481 91000 7234 92000 6997 93000 6769 94000 6548 95000 6337 96000 6132 97000 5934 98000 5744 99000 5561 100000 5384 101000 5214 102000 5051 103000 4893 104000 4741 105000 4594 106000 4453 107000 4316 108000 4184 109000 4057 110000 3934 111000 3816 112000 3701 113000 3591 114000 3484 115000 3380 116000 3281 117000 3185 118000 3093 119000 3003 120000 2916 121000 2832 122000 2751 123000 2672 124000 2596 125000 2522>; }; tboard_thermistor3: thermal-ntc3 { compatible = "mediatek,mt6377-tia-ntc"; #thermal-sensor-cells = <0>; temperature-lookup-table = < (-40000) 4397119 (-39000) 4092874 (-38000) 3811717 (-37000) 3551749 (-36000) 3311236 (-35000) 3088599 (-34000) 2882396 (-33000) 2691310 (-32000) 2514137 (-31000) 2349778 (-30000) 2197225 (-29000) 2055558 (-28000) 1923932 (-27000) 1801573 (-26000) 1687773 (-25000) 1581881 (-24000) 1483100 (-23000) 1391113 (-22000) 1305413 (-21000) 1225531 (-20000) 1151037 (-19000) 1081535 (-18000) 1016661 (-17000) 956080 (-16000) 899481 (-15000) 846579 (-14000) 797111 (-13000) 750834 (-12000) 707524 (-11000) 666972 (-10000) 628988 (-9000) 593342 (-8000) 559931 (-7000) 528602 (-6000) 499212 (-5000) 471632 (-4000) 445772 (-3000) 421480 (-2000) 398652 (-1000) 377193 0 357012 1000 338006 2000 320122 3000 303287 4000 287434 5000 272500 6000 258426 7000 245160 8000 232649 9000 220847 10000 209710 11000 199196 12000 189268 13000 179890 14000 171027 15000 162651 16000 154726 17000 147232 18000 140142 19000 133432 20000 127080 21000 121066 22000 115368 23000 109970 24000 104852 25000 100000 26000 95398 27000 91032 28000 86889 29000 82956 30000 79222 31000 75675 32000 72306 33000 69104 34000 66061 35000 63167 36000 60415 37000 57797 38000 55306 39000 52934 40000 50677 41000 48528 42000 46482 43000 44533 44000 42675 45000 40904 46000 39213 47000 37601 48000 36063 49000 34595 50000 33195 51000 31859 52000 30584 53000 29366 54000 28203 55000 27091 56000 26028 57000 25013 58000 24042 59000 23113 60000 22224 61000 21374 62000 20560 63000 19782 64000 19036 65000 18322 66000 17640 67000 16986 68000 16360 69000 15759 70000 15184 71000 14631 72000 14100 73000 13591 74000 13103 75000 12635 76000 12187 77000 11756 78000 11343 79000 10946 80000 10565 81000 10199 82000 9847 83000 9509 84000 9184 85000 8872 86000 8572 87000 8283 88000 8005 89000 7738 90000 7481 91000 7234 92000 6997 93000 6769 94000 6548 95000 6337 96000 6132 97000 5934 98000 5744 99000 5561 100000 5384 101000 5214 102000 5051 103000 4893 104000 4741 105000 4594 106000 4453 107000 4316 108000 4184 109000 4057 110000 3934 111000 3816 112000 3701 113000 3591 114000 3484 115000 3380 116000 3281 117000 3185 118000 3093 119000 3003 120000 2916 121000 2832 122000 2751 123000 2672 124000 2596 125000 2522>; }; tsx_thermistor: thermal-ntc4 { compatible = "mediatek,mt6377-tia-ntc"; #thermal-sensor-cells = <0>; temperature-lookup-table = < (-40000) 5319893 (-39000) 4921450 (-38000) 4555864 (-37000) 4220193 (-36000) 3911778 (-35000) 3628214 (-34000) 3367324 (-33000) 3127136 (-32000) 2905864 (-31000) 2701885 (-30000) 2513730 (-29000) 2340060 (-28000) 2179662 (-27000) 2031430 (-26000) 1894358 (-25000) 1767530 (-24000) 1650110 (-23000) 1541338 (-22000) 1440519 (-21000) 1347016 (-20000) 1260250 (-19000) 1179692 (-18000) 1104854 (-17000) 1035294 (-16000) 970604 (-15000) 910412 (-14000) 854374 (-13000) 802177 (-12000) 753533 (-11000) 708176 (-10000) 665864 (-9000) 626371 (-8000) 589493 (-7000) 555039 (-6000) 522835 (-5000) 492719 (-4000) 464542 (-3000) 438167 (-2000) 413469 (-1000) 390328 0 368639 1000 348299 2000 329218 3000 311309 4000 294493 5000 278697 6000 263852 7000 249896 8000 236769 9000 224418 10000 212791 11000 201843 12000 191528 13000 181808 14000 172643 15000 163999 16000 155844 17000 148146 18000 140877 19000 134011 20000 127523 21000 121390 22000 115591 23000 110105 24000 104914 25000 100000 26000 95347 27000 90939 28000 86762 29000 82803 30000 79049 31000 75488 32000 72109 33000 68902 34000 65857 35000 62965 36000 60218 37000 57607 38000 55125 39000 52765 40000 50520 41000 48384 42000 46351 43000 44415 44000 42572 45000 40816 46000 39143 47000 37548 48000 36028 49000 34578 50000 33195 51000 31875 52000 30615 53000 29412 54000 28264 55000 27167 56000 26119 57000 25117 58000 24159 59000 23243 60000 22368 61000 21530 62000 20728 63000 19961 64000 19226 65000 18523 66000 17849 67000 17203 68000 16584 69000 15991 70000 15423 71000 14878 72000 14355 73000 13853 74000 13372 75000 12910 76000 12466 77000 12040 78000 11631 79000 11238 80000 10861 81000 10498 82000 10149 83000 9814 84000 9491 85000 9181 86000 8883 87000 8596 88000 8319 89000 8053 90000 7797 91000 7551 92000 7313 93000 7084 94000 6864 95000 6651 96000 6446 97000 6249 98000 6059 99000 5875 100000 5698 101000 5527 102000 5362 103000 5203 104000 5050 105000 4901 106000 4758 107000 4620 108000 4486 109000 4357 110000 4233 111000 4112 112000 3996 113000 3883 114000 3774 115000 3669 116000 3567 117000 3469 118000 3374 119000 3281 120000 3192 121000 3106 122000 3022 123000 2941 124000 2863 125000 2787>; }; mt6363_temp: mt6363-temp { compatible = "mediatek,mt6363-pmic-temp"; }; mt6368_temp: mt6368-temp { compatible = "mediatek,mt6368-pmic-temp"; }; mt6377_temp: mt6377-temp { compatible = "mediatek,mt6377-pmic-temp"; }; md_cooler: md-cooler { compatible = "mediatek,mt6299-md-cooler"; pa1: pa1 { mutt_pa1: mutt-pa1 { #cooling-cells = <2>; }; tx_pwr_pa1: tx-pwr-pa1 { #cooling-cells = <2>; }; }; pa2: pa2 { mutt_pa2: mutt-pa2 { #cooling-cells = <2>; }; tx_pwr_pa2: tx-pwr-pa2 { #cooling-cells = <2>; }; scg_off_pa2: scg-off-pa2 { #cooling-cells = <2>; }; }; }; charger_cooler: charger-cooler { compatible = "mediatek,mt6375-charger-cooler"; #cooling-cells = <2>; }; backlight_cooler: backlight-cooler { compatible = "mediatek,backlight-cooler"; backlight-names = "lcd-backlight"; #cooling-cells = <2>; }; therm_intf: therm_intf@114000 { compatible = "mediatek,therm_intf"; reg = <0 0x00114000 0 0x400>; reg-names = "therm_sram"; }; thermal_zones: thermal-zones { soc_max { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 0>; trips { soc_max_crit: soc_max_crit@0 { temperature = <113500>; hysteresis = <2000>; type = "critical"; }; }; }; cpu_big1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 1>; }; cpu_big2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 2>; }; cpu_big3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 3>; }; cpu_big4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 4>; }; cpu_little1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 5>; }; cpu_little2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 6>; }; cpu_little3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 7>; }; cpu_little4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 8>; }; gpu2 { polling-delay = <500>; /* milliseconds */ polling-delay-passive = <300>; /* milliseconds */ thermal-sensors = <&lvts 9>; trips { gpu_throttle: trip-point@0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; }; cooling-maps { map0 { trip = <&gpu_throttle>; cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; }; }; gpu1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 10>; }; soc1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 11>; }; soc2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 12>; }; soc3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 13>; }; soc4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 14>; }; md1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 15>; }; md2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 16>; }; md3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 17>; }; md4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 18>; }; consys { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&consys>; }; }; lastbus: lastbus { compatible = "mediatek,lastbus"; enabled = <1>; sw_version = <1>; timeout_ms = <200>; timeout_type = <0>; monitors { monitor1 { monitor_name = "debug_ctrl_ao_INFRA_AO"; base = <0x10023000>; num_ports = <53>; idle_masks = <0x08 0x00008000>, <0x10 0x80000000>, <0x14 0x000000ff>, <0x18 0x0fff0000>; bus_freq_mhz = <78>; }; monitor2 { monitor_name = "debug_ctrl_ao_INFRA_AO1"; base = <0x1002b000>; num_ports = <18>; bus_freq_mhz = <78>; }; monitor3 { monitor_name = "debug_ctrl_ao_EMI_AO"; base = <0x10042000>; num_ports = <12>; idle_masks = <0x08 0xf8000000>, <0x0c 0x001fffff>; bus_freq_mhz = <533>; }; monitor4 { monitor_name = "debug_ctrl_ao_PERI_PAR_AO"; base = <0x11037000>; num_ports = <21>; bus_freq_mhz = <78>; }; monitor5 { monitor_name = "debug_ctrl_ao_VLP_AO"; base = <0x1c01d000>; num_ports = <12>; bus_freq_mhz = <156>; }; monitor6 { monitor_name = "debug_ctrl_ao_MM_AO"; base = <0x1e825000>; num_ports = <23>; bus_freq_mhz = <688>; }; }; }; memory { device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; odm: odm { compatible = "simple-bus"; }; uarthub: uarthub { compatible = "mediatek,mt6835-uarthub"; uarthub_disable = <1>; }; firmware: firmware { scmi: scmi { compatible = "arm,scmi"; mboxes = <&tinysys_mbox 0>, <&tinysys_mbox 1>; shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>; mbox-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; scmi_tinysys: protocol@80 { reg = <0x80>; scmi-qos = <1>; scmi-met = <3>; scmi-gpupm = <6>; scmi-plt = <7>; scmi-cm = <9>; scmi-slbc = <10>; scmi-apmcupm = <12>; scmi-mminfra = <13>; }; }; }; reserved_memory: reserved-memory { /*TODO: add reserved memory node here*/ #address-cells = <2>; #size-cells = <2>; ranges; ssmr_cma_mem: ssmr-reserved-cma_memory { compatible = "shared-dma-pool"; reusable; size = <0 0x10000000>; alignment = <0 0x1000000>; }; ssheap_cma_mem: ssheap-reserved-cma_memory { compatible = "shared-dma-pool"; reusable; size = <0 0x10000000>; alignment = <0 0x200000>; }; }; memory_ssmr_features: memory-ssmr-features { compatible = "mediatek,memory-ssmr-features"; svp-region-based-size = <0 0x18000000>; svp-page-based-size = <0 0>; tui-size = <0 0x4000000>; wfd-region-based-size = <0 0x4000000>; wfd-page-based-size = <0 0>; prot-region-based-size = <0 0x10000000>; prot-page-based-size = <0 0>; }; ssmr { compatible = "mediatek,trusted_mem"; memory-region = <&ssmr_cma_mem>; }; ssheap { compatible = "mediatek,trusted_mem_ssheap"; memory-region = <&ssheap_cma_mem>; }; drm_wv: drm-wv { compatible = "mediatek,drm_wv"; status = "okay"; }; mtee_svp: mtee-svp { compatible = "medaitek,svp"; }; touch: touch { compatible = "mediatek,touch"; }; //add by wangfei for fp 20231018 start focaltech_fp: focaltech_fp { compatible = "focaltech,fp"; }; //add by wangfei for fp 20231018 end qos:qos@11bb00 { compatible = "mediatek,mt6893-qos"; mediatek,qos-enable = <1>; reg = <0 0x0011bb00 0 0x100>; }; sspm: sspm@1c340000 { compatible = "mediatek,sspm"; reg = <0 0x1c300000 0 0x30000>, <0 0x1c340000 0 0x10000>, <0 0x1c380000 0 0x80>; reg-names = "sspm_base", "cfgreg", "mbox_share"; interrupts = ; interrupt-names = "ipc"; sspm_res_ram_start = <0x0>; sspm_res_ram_size = <0x110000>; /* 1M + 64K */ }; /* Trustonic Mobicore SW IRQ number 576 = 32 + 544 */ mobicore: mobicore { compatible = "trustonic,mobicore"; interrupts = ; }; /* Microtrust SW IRQ number 578(578 - 32) ~ 579(579 - 32) */ utos: utos { compatible = "microtrust,utos"; interrupts = ; }; utos_tester { compatible = "microtrust,tester-v1"; }; teeperf { compatible = "mediatek,teeperf"; cpu-type = <2>; /* 1: CPU_V9_TYPE, 2: CPU_V8_TYPE */ cpu-map = <2>; /* 1: CPU_4_3_1_MAP, 2: CPU_6_2_MAP */ }; ssram1@1c350000 { compatible = "mmio-sram_1"; reg = <0x0 0x1c350000 0x0 0x80>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x1c350000 0x80>; scmi_tx_shmem: tiny_mbox@0 { compatible = "arm,scmi-shmem"; reg = <0x0 0x80>; }; }; ssram2@1c360000 { compatible = "mmio-sram_2"; reg = <0x0 0x1c360000 0x0 0x80>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x1c360000 0x80>; scmi_rx_shmem: tiny_mbox@1 { compatible = "arm,scmi-shmem"; reg = <0x0 0x80>; }; }; tinysys_mbox: tinysys_mbox@1c351000 { compatible = "mediatek,tinysys_mbox"; reg = <0 0x1c351000 0 0x1000>, <0 0x1c361000 0 0x1000>; /* for profiling */ shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>; interrupts = , ; #mbox-cells = <1>; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; dfd_mcu: dfd-mcu { compatible = "mediatek,dfd_mcu"; enabled = <1>; hw-version = <30>; sw-version = <1>; dfd-timeout = <0x1f4>; buf-length = <0x100000>; buf-addr-align = <0x1000000>; nr-max-core = <8>; nr-big-core = <2>; nr-rs-entry-little = <6>; nr-rs-entry-big = <2>; nr-header-row = <0>; chip-id-offset = <0x18>; check-pattern-offset = <0x0>; /* dfd_disable_efuse = <25 12>; */ dfd-disable-efuse = <(-1) (-1)>; dfd_cache: dfd-cache { enabled = <0>; dfd-timeout = <0x2710>; buf-length = <0x800000>; tap-en = <0x43ff>; }; }; scp_infra: scp_infra@10001000 { compatible = "mediatek,scpinfra"; reg = <0 0x10001000 0 0x1000>, /* infracfg_ao */ <0 0x10006000 0 0x1000>, /* spm */ <0 0x10000000 0 0x1000>; /* topckgen */ #clock-cells = <1>; }; performance: performance-controller@11bc00 { compatible = "mediatek,cpufreq-hw"; reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; reg-names = "performance-domain0", "performance-domain1"; #performance-domain-cells = <1>; }; eas_info: eas_info { compatible = "mediatek,eas-info"; csram-base = <0x0011bc00>; /* L, B, CCI */ offs-thermal-limit = <0x1208 0x120c 0x1210>; offs-cap = <0xfa0>; }; lkg: lkg@114400 { compatible = "mediatek,mtk-lkg"; reg = <0 0x00114400 0 0xc00>; }; cpu_mcucfg: mcusys_ao_cfg@c530000 { reg = <0 0x0c530000 0 0x10000>; /* 64KB */ }; bus_parity { compatible = "mediatek,bus-parity"; reg = <0 0x0c538800 0 0x20>, /* M0, MST_CCIM0 */ <0 0x0c538820 0 0x20>, /* M1, MST_CCIM1 */ <0 0x0c538840 0 0x20>, /* M2, MST_INTAXI */ <0 0x0c538860 0 0x40>, /* S0, SLV_1TO2 */ <0 0x0c5388a0 0 0x30>, /* S1, SLV_L3C */ <0 0x0c5388d0 0 0x30>, /* S2, SLV_GIC */ <0 0x10270600 0 0x14>, /* S4, MCU2EMI_M0 */ <0 0x10270620 0 0x14>, /* S5, MCU2EMI_M1 */ <0 0x100017a8 0 0x14>, /* S3, MCU2IFR */ <0 0x100017bc 0 0x8>, /* M5, IFR_L3C2MCU */ <0 0x0c53a39c 0 0x4>; /* BUS_PARITY_FAIL */ interrupts = , /* MCU */ ; /* Infra */ interrupt-names = "mcu-bus-parity", "infra-bus-parity"; mcu-names = "MST_CCI_M0", "MST_CCI_M1", "MST_INTAXI_", "SLV_1TO2", "SLV_L3C", "SLV_GIC"; infra-names = "MCU2EMI_M0", "MCU2EMI_M1", "MCU2IFR", "IFR_L3C2MCU"; /* 0: master, 1: slave, 2: emi */ mcu-types = <0 0 0 1 1 1>; infra-types = <2 2 1 0>; /* offset of MST_XXX_LOG_RD0/SLV_XXX_LOG_WD0 for mcu bpm */ mcu-rd0wd0-offset = <0x10 0x10 0x10 0x30 0x28 0x28>; /* shift of parity fail bit in BUS_PARITY_FAIL for mcu bpm */ mcu-fail-bit-shift = <0 1 2 3 4 5>; mcu-data-len = <4 4 2 4 2 2>; }; cpu_pll: mcusys_pll1u_top@1000c000 { reg = <0 0x1000c000 0 0x1000>; /* 4KB */ }; cm_mgr: cm_mgr@c530000 { compatible = "mediatek,mt6835-cm_mgr"; reg = <0 0x0c530000 0 0x9000>; reg-names = "cm_mgr_base"; interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "cm-perf-bw"; required-opps = <&dvfsrc_freq_opp0>, <&dvfsrc_freq_opp1>, <&dvfsrc_freq_opp2>, <&dvfsrc_freq_opp3>, <&dvfsrc_freq_opp4>, <&dvfsrc_freq_opp5>, <&dvfsrc_freq_opp6>; cm_mgr,cp_down = <100 100 100 100 100 100 100>; cm_mgr,cp_up = <100 100 100 100 100 100 100>; cm_mgr,dt_down = <3 0 0 0 0 0 0>; cm_mgr,dt_up = <0 0 0 0 0 0 0>; cm_mgr,vp_down = <100 100 100 100 100 100 100>; cm_mgr,vp_up = <100 100 100 100 100 100 100>; use_bcpu_weight = "enable"; cpu_power_bcpu_weight_max = <100>; cpu_power_bcpu_weight_min = <100>; /* use_cpu_to_dram_map = "enable"; */ /* cm_mgr_cpu_opp_to_dram = <0 0 0 0 1 1 1 1 */ /* 1 2 2 2 2 2 2 2>; */ /* use_cpu_to_dram_map_new = "enable"; */ }; mcupm: mcupm@c540000 { compatible = "mediatek,mcupm"; reg = <0 0x0c540000 0 0x22000>, <0 0x0c55fb00 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fba0 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fc40 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fce0 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fd80 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fe20 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fec0 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55ff60 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>; reg-names = "mcupm_base", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_send", "mbox0_recv", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_send", "mbox1_recv", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_send", "mbox2_recv", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_send", "mbox3_recv", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_send", "mbox4_recv", "mbox5_base", "mbox5_set", "mbox5_clr", "mbox5_send", "mbox5_recv", "mbox6_base", "mbox6_set", "mbox6_clr", "mbox6_send", "mbox6_recv", "mbox7_base", "mbox7_set", "mbox7_clr", "mbox7_send", "mbox7_recv"; interrupts = , , , , , , , ; interrupt-names = "mbox0", "mbox1", "mbox2", "mbox3", "mbox4", "mbox5", "mbox6", "mbox7"; }; systimer: systimer@1c011000 { compatible = "mediatek,mt6835-timer", "mediatek,mt6765-timer"; reg = <0 0x1c011000 0 0x1000>; interrupts = , , ; clocks = <&clk13m>; }; topckgen@10000000 { compatible = "mediatek,topckgen"; reg = <0 0x10000000 0 0x1000>; }; dcm: dcm@10001000 { compatible = "mediatek,mt6835-dcm"; reg = <0 0x10001000 0 0x1000>, <0 0x10022000 0 0x1000>, <0 0x11035000 0 0x1000>, <0 0x112ba000 0 0x1000>, <0 0x1c017000 0 0x1000>, <0 0xc530000 0 0x5000>, <0 0xc538000 0 0x5000>; reg-names = "infracfg_ao", "infra_ao_bcrm", "peri_ao_bcrm", "ufs0_ao_bcrm", "vlp_ao_bcrm", "mcusys_par_wrap", "mp_cpusys_top"; }; infracfg_ao@10001000 { compatible = "mediatek,infracfg_ao"; reg = <0 0x10001000 0 0x1000>; }; infracfg_ao_mem@10002000 { compatible = "mediatek,infracfg_ao_mem"; reg = <0 0x10002000 0 0x1000>; }; pericfg@10003000 { compatible = "mediatek,pericfg"; reg = <0 0x10003000 0 0x1000>; }; gpio: gpio@10005000 { compatible = "mediatek,gpio"; reg = <0 0x10005000 0 0x1000>; }; pio: pinctrl { compatible = "mediatek,mt6835-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x11b10000 0 0x1000>, <0 0x11c40000 0 0x1000>, <0 0x11d10000 0 0x1000>, <0 0x11d30000 0 0x1000>, <0 0x11d40000 0 0x1000>, <0 0x11e30000 0 0x1000>, <0 0x11eb0000 0 0x1000>, <0 0x11ec0000 0 0x1000>; reg-names = "gpio", "iocfg_lm", "iocfg_rb", "iocfg_bl", "iocfg_bm", "iocfg_br", "iocfg_lt", "iocfg_rm", "iocfg_rt"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 193>; interrupt-controller; #interrupt-cells = <2>; mediatek,eint = <&eint>; }; eint: apirq@11e60000 { compatible = "mediatek,mt6983-eint"; reg = <0 0x11e60000 0 0x1000>, <0 0x11ee0000 0 0x1000>, <0 0x11de0000 0 0x1000>, <0 0x1c01e000 0 0x1000>; reg-name = "eint-w", "eint-e", "eint-s", "eint-c"; interrupts = ; mediatek,instance-num = <4>; mediatek,total-pin-number = <213>; mediatek,pins = <0 2 0 1>,<1 2 1 1>,<2 2 2 1>,<3 2 3 1>, <4 2 4 1>,<5 2 5 1>,<6 2 6 1>,<7 2 7 1>, <8 2 8 1>,<9 2 9 1>,<10 2 10 1>,<11 2 11 1>, <12 2 12 1>,<13 2 13 1>,<14 2 14 1>,<15 2 15 1>, <16 2 16 1>,<17 2 17 1>,<18 2 18 1>,<19 2 19 1>, <20 2 20 1>,<21 2 21 1>,<22 2 22 1>,<23 2 23 1>, <24 2 24 1>,<25 2 25 1>,<26 2 26 1>,<27 2 27 1>, <28 2 28 1>,<29 2 29 1>,<30 2 30 1>,<31 2 31 1>, <32 2 32 1>,<33 2 33 1>,<34 2 34 1>,<35 2 35 1>, <36 1 0 0>,<37 1 1 0>,<38 1 2 0>,<39 1 3 0>, <40 1 4 0>,<41 1 5 0>,<42 1 6 0>,<43 2 36 0>, <44 2 37 0>,<45 2 38 0>,<46 2 39 0>,<47 2 40 0>, <48 2 41 0>,<49 2 42 0>,<50 2 43 0>,<51 2 44 0>, <52 2 45 0>,<53 2 46 0>,<54 2 47 0>,<55 2 48 0>, <56 0 0 0>,<57 0 1 0>,<58 0 2 0>,<59 0 3 0>, <60 1 7 0>,<61 1 8 0>,<62 1 9 0>,<63 1 10 0>, <64 1 11 0>,<65 1 12 0>,<66 1 13 0>,<67 1 14 0>, <68 0 4 0>,<69 0 5 0>,<70 0 6 0>,<71 0 7 0>, <72 0 8 0>,<73 1 15 0>,<74 1 16 0>,<75 1 17 0>, <76 1 18 0>,<77 1 19 0>,<78 1 20 0>,<79 2 49 0>, <80 2 50 0>,<81 2 51 0>,<82 2 52 0>,<83 2 53 0>, <84 2 54 0>,<85 2 55 0>,<86 2 56 0>,<87 2 57 0>, <88 1 21 0>,<89 1 22 0>,<90 1 23 0>,<91 1 24 0>, <92 1 25 0>,<93 2 58 0>,<94 2 59 0>,<95 2 60 0>, <96 2 61 0>,<97 2 62 0>,<98 2 63 0>,<99 2 64 0>, <100 2 65 0>,<101 2 66 0>,<102 2 67 0>,<103 2 68 0>, <104 2 69 0>,<105 2 70 0>,<106 2 71 0>,<107 2 72 0>, <108 2 73 0>,<109 2 74 0>,<110 2 75 0>,<111 2 76 0>, <112 2 77 0>,<113 2 78 0>,<114 2 79 0>,<193 3 0 1>, <194 3 1 1>,<195 3 2 1>,<196 3 3 1>,<197 3 4 1>, <198 3 5 0>,<199 3 6 0>,<200 3 7 0>,<201 3 8 0>, <202 3 9 0>,<203 3 10 0>,<204 3 11 0>,<205 3 12 0>, <206 3 13 0>,<207 3 14 0>,<208 3 15 0>,<209 3 16 0>, <210 3 17 0>,<211 3 18 0>,<212 3 19 0>; }; spmi: spmi@1c804000 { compatible = "mediatek,mt6835-spmi"; reg = <0 0x1c804000 0 0x0008ff>, <0 0x1c801000 0 0x000100>; reg-names = "pmif", "spmimst","spmi_nack_irq"; interrupts-extended = <&pio 209 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, <&gic GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "rcs_irq","pmif_irq","spmi_nack_irq"; interrupt-controller; #interrupt-cells = <1>; irq_event_en = <0x80000000 0x10204081 0x0 0x0 0x0>; swinf_ch_start = <7>; ap_swinf_no = <2>; #address-cells = <2>; #size-cells = <0>; }; spmi_pmif_mpu: spmi-pmif-mpu@1c804900 { compatible = "mediatek,mt6835-spmi-pmif-mpu"; reg = <0 0x1c804900 0 0x000500>; reg-names = "pmif_mpu"; mediatek,pmic-all-rgn-en = <0x4865>; mediatek,pmic-all-rgn-en-2 = <0x0>; mediatek,kernel-enable-time = <0x3c>; }; mmc0: mmc@11230000 { compatible = "mediatek,mt6835-mmc"; reg = <0 0x11230000 0 0x10000>, <0 0x11e70000 0 0x1000>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_MSDC50_0_HCLK_SEL>, <&topckgen_clk CLK_TOP_MSDC50_0_SEL>, <&topckgen_clk CLK_TOP_AES_MSDCFDE_SEL>, <&topckgen_clk CLK_TOP_MSDC_0P_MACRO_SEL>, <&pericfg_ao_clk CLK_PERAOP_MSDC0_HCLK>, <&pericfg_ao_clk CLK_PERAOP_MSDC0_SRC>, <&pericfg_ao_clk CLK_PERAOP_MSDC0_AES>, <&pericfg_ao_clk CLK_PERAOP_MSDC0_HCLK_WRAP>, <&pericfg_ao_clk CLK_PERAOP_MSDC0_XCLK>; clock-names = "bus_clk", "source", "crypto_clk", "new_rx_clk", "hclk", "source_cg", "crypto_cg", "pclk_cg", "axi_cg"; status = "disabled"; }; mmc1: mmc@11240000 { compatible = "mediatek,mt6835-mmc"; reg = <0 0x11240000 0 0x1000>, <0 0x11e80000 0 0x1000>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>, <&topckgen_clk CLK_TOP_MSDC_1P_RX_SEL>, <&pericfg_ao_clk CLK_PERAOP_MSDC1_HCLK>, <&pericfg_ao_clk CLK_PERAOP_MSDC1_SRC>; clock-names = "source", "new_rx_clk", "hclk", "source_cg"; status = "disabled"; }; mali: mali@13000000 { compatible = "mediatek,mali", "arm,mali-valhall"; reg = <0 0x13000000 0 0x4000>; interrupts = , , , , ; interrupt-names = "GPU", "MMU", "JOB", "EVENT", "PWR"; operating-points-v2 = <&gpu_mali_opp>; #cooling-cells = <2>; ged-supply = <&ged>; }; gpu_mali_opp: opp-table0 { compatible = "operating-points-v2"; opp00 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <900000>; }; opp01 { opp-hz = /bits/ 64 <1086000000>; opp-microvolt = <893750>; }; opp02 { opp-hz = /bits/ 64 <1072000000>; opp-microvolt = <887500>; }; opp03 { opp-hz = /bits/ 64 <1058000000>; opp-microvolt = <881250>; }; opp04 { opp-hz = /bits/ 64 <1045000000>; opp-microvolt = <875000>; }; opp05 { opp-hz = /bits/ 64 <1031000000>; opp-microvolt = <868750>; }; opp06 { opp-hz = /bits/ 64 <1017000000>; opp-microvolt = <862500>; }; opp07 { opp-hz = /bits/ 64 <1003000000>; opp-microvolt = <856250>; }; opp08 { opp-hz = /bits/ 64 <990000000>; opp-microvolt = <850000>; }; opp09 { opp-hz = /bits/ 64 <976000000>; opp-microvolt = <843750>; }; opp10 { opp-hz = /bits/ 64 <962000000>; opp-microvolt = <831250>; }; opp11 { opp-hz = /bits/ 64 <948000000>; opp-microvolt = <825000>; }; opp12 { opp-hz = /bits/ 64 <935000000>; opp-microvolt = <818750>; }; opp13 { opp-hz = /bits/ 64 <921000000>; opp-microvolt = <812500>; }; opp14 { opp-hz = /bits/ 64 <907000000>; opp-microvolt = <806250>; }; opp15 { opp-hz = /bits/ 64 <893000000>; opp-microvolt = <800000>; }; opp16 { opp-hz = /bits/ 64 <880000000>; opp-microvolt = <793750>; }; opp17 { opp-hz = /bits/ 64 <868000000>; opp-microvolt = <787500>; }; opp18 { opp-hz = /bits/ 64 <857000000>; opp-microvolt = <781250>; }; opp19 { opp-hz = /bits/ 64 <846000000>; opp-microvolt = <775000>; }; opp20 { opp-hz = /bits/ 64 <835000000>; opp-microvolt = <768750>; }; opp21 { opp-hz = /bits/ 64 <823000000>; opp-microvolt = <762500>; }; opp22 { opp-hz = /bits/ 64 <812000000>; opp-microvolt = <756250>; }; opp23 { opp-hz = /bits/ 64 <801000000>; opp-microvolt = <756250>; }; opp24 { opp-hz = /bits/ 64 <790000000>; opp-microvolt = <750000>; }; opp25 { opp-hz = /bits/ 64 <778000000>; opp-microvolt = <743750>; }; opp26 { opp-hz = /bits/ 64 <767000000>; opp-microvolt = <737500>; }; opp27 { opp-hz = /bits/ 64 <756000000>; opp-microvolt = <731250>; }; opp28 { opp-hz = /bits/ 64 <745000000>; opp-microvolt = <725000>; }; opp29 { opp-hz = /bits/ 64 <733000000>; opp-microvolt = <718750>; }; opp30 { opp-hz = /bits/ 64 <722000000>; opp-microvolt = <712500>; }; opp31 { opp-hz = /bits/ 64 <711000000>; opp-microvolt = <706250>; }; opp32 { opp-hz = /bits/ 64 <700000000>; opp-microvolt = <700000>; }; opp33 { opp-hz = /bits/ 64 <674000000>; opp-microvolt = <700000>; }; opp34 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <700000>; }; opp35 { opp-hz = /bits/ 64 <622000000>; opp-microvolt = <693750>; }; opp36 { opp-hz = /bits/ 64 <596000000>; opp-microvolt = <693750>; }; opp37 { opp-hz = /bits/ 64 <570000000>; opp-microvolt = <693750>; }; opp38 { opp-hz = /bits/ 64 <545000000>; opp-microvolt = <687500>; }; opp39 { opp-hz = /bits/ 64 <519000000>; opp-microvolt = <687500>; }; opp40 { opp-hz = /bits/ 64 <493000000>; opp-microvolt = <687500>; }; opp41 { opp-hz = /bits/ 64 <467000000>; opp-microvolt = <681250>; }; opp42 { opp-hz = /bits/ 64 <441000000>; opp-microvolt = <681250>; }; opp43 { opp-hz = /bits/ 64 <415000000>; opp-microvolt = <681250>; }; opp44 { opp-hz = /bits/ 64 <390000000>; opp-microvolt = <675000>; }; }; gpufreq: gpufreq { compatible = "mediatek,gpufreq"; reg = <0 0x13fbf000 0 0x1000>, /* MFG_TOP_CONFIG */ <0 0x1c001000 0 0x1000>, /* SLEEP */ <0 0x10000000 0 0x1000>, /* TOPCKGEN */ <0 0x1021c000 0 0x1000>, /* NTH_EMICFG */ <0 0x1021e000 0 0x1000>, /* STH_EMICFG */ <0 0x10270000 0 0x1000>, /* NTH_EMICFG_AO_MEM */ <0 0x1030e000 0 0x1000>, /* STH_EMICFG_AO_MEM */ <0 0x1020e000 0 0x1000>, /* INFRACFG */ <0 0x10001000 0 0x1000>, /* INFRACFG_AO */ <0 0x10042000 0 0x1000>, /* NTH_EMI_AO_DEBUG_CTRL */ <0 0x10028000 0 0x1000>, /* STH_EMI_AO_DEBUG_CTRL */ <0 0x10023000 0 0x1000>, /* INFRA_AO_DEBUG_CTRL */ <0 0x1002b000 0 0x1000>, /* INFRA_AO1_DEBUG_CTRL */ <0 0x11c10000 0 0x1000>, /* EFUSE */ <0 0x0010F000 0 0x2000>; /* SYSRAM_MFG_HISTORY */ reg-names = "mfg_top_config", "sleep", "topckgen", "nth_emicfg", "sth_emicfg", "nth_emicfg_ao_mem", "sth_emicfg_ao_mem", "infracfg", "infracfg_ao", "nth_emi_ao_debug_ctrl", "sth_emi_ao_debug_ctrl", "infra_ao_debug_ctrl", "infra_ao1_debug_ctrl", "efuse", "sysram_mfg_history"; clocks = <&topckgen_clk CLK_TOP_MFG_PLL_SEL>, <&topckgen_clk CLK_TOP_MFG_REF_SEL>, <&topckgen_clk CLK_TOP_MFGPLL>, <&topckgen_clk CLK_TOP_MFG_REF_SEL_CK>, <&mfg_top_config_clk CLK_MFGCFG_BG3D>; clock-names = "clk_mux", "clk_ref_mux", "clk_main_parent", "clk_sub_parent", "subsys_bg3d"; power-domains = <&scpsys MT6835_POWER_DOMAIN_MFG0_DORMANT>, <&scpsys MT6835_POWER_DOMAIN_MFG1>, <&scpsys MT6835_POWER_DOMAIN_MFG2>, <&scpsys MT6835_POWER_DOMAIN_MFG3>; power-domain-names = "pd_mfg0", "pd_mfg1", "pd_mfg2", "pd_mfg3"; _dvfsrc-supply = <&dvfsrc_vcore>; nvmem-cells = <&efuse_segment>; nvmem-cell-names = "efuse_segment_cell"; fhctl-supply = <&fhctl>; gpufreq_wrapper-supply = <&gpufreq_wrapper>; }; gpueb: gpueb { compatible = "mediatek,gpueb"; gpueb-support = <0>; gpueb_mem_table = <0 0x4000>; /* 16KB */ gpueb_mem_name_table = "MEM_ID_GPUFREQ"; /* GPUFREQ */ }; gpufreq_wrapper: gpufreq_wrapper { compatible = "mediatek,gpufreq_wrapper"; gpufreq-version = <2>; dual-buck = <0>; gpueb-support = <0>; gpufreq-bringup = <0>; }; ged: ged { compatible = "mediatek,ged"; gpufreq-supply = <&gpufreq>; }; sleep@1c001000 { compatible = "mediatek,sleep"; reg = <0 0x1c001000 0 0x1000>; interrupts = ; }; toprgu@10007000 { compatible = "mediatek,toprgu"; reg = <0 0x10007000 0 0x1000>; }; apxgpt@10008000 { compatible = "mediatek,apxgpt"; reg = <0 0x10008000 0 0x1000>; }; sej@1000a000 { compatible = "mediatek,sej"; reg = <0 0x1000a000 0 0x1000>; interrupts = ; }; apmixed@1000c000 { compatible = "mediatek,apmixed"; reg = <0 0x1000c000 0 0xe00>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = ; }; dsu-pmu-0 { compatible = "arm,dsu-pmu"; interrupts = ; cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; emicen: emicen@10219000 { compatible = "mediatek,common-emicen"; reg = <0 0x10219000 0 0x1000>; mediatek,emi-reg = <&emichn>; a2d_hash = <7>; a2d_disph = <0>; }; emichn: emichn@10245000 { compatible = "mediatek,common-emichn"; reg = <0 0x10245000 0 0x1000>, <0 0x10235000 0 0x1000>; }; emi-fake-eng@1026c000 { compatible = "mediatek,emi-fake-engine"; reg = <0 0x1026c000 0 0x1000>, <0 0x1026d000 0 0x1000>; }; emiisu { compatible = "mediatek,common-emiisu"; ctrl_intf = <1>; }; emimpu: emimpu@10226000 { compatible = "mediatek,common-emimpu"; reg = <0 0x10226000 0 0x1000>; mediatek,emi-reg = <&emicen>; interrupts = ; region_cnt = <32>; domain_cnt = <16>; addr_align = <16>; dump = <0x1f0 0x1f8 0x1fc>; clear = <0x160 0xffffffff 16>, <0x200 0x00000003 16>, <0x1f0 0x80000000 1>; clear_md = <0x1fc 0x80000000 1>; ctrl_intf = <1>; slverr = <0>; }; fhctl: fhctl@1000ce00 { compatible = "mediatek,mt6835-fhctl"; reg = <0 0x1000ce00 0 0x200>, //AP FHCTL base <0 0x1000c000 0 0xe00>; //APMIX base map0 { domain = "top"; method = "fhctl-mcupm"; armpll_ll { fh-id = <0>; pll-id = ; }; armpll_bl { fh-id = <1>; pll-id = ; }; armpll_b { fh-id = <2>; pll-id = <999>; }; ccipll { fh-id = <3>; pll-id = ; }; mpll { fh-id = <6>; pll-id = ; }; mmpll { fh-id = <7>; pll-id = ; }; mainpll { fh-id = <8>; pll-id = ; }; msdcpll { fh-id = <9>; pll-id = ; }; mfgpll { fh-id = <10>; pll-id = ; }; imgpll { fh-id = <11>; pll-id = ; }; tvdpll { fh-id = <12>; pll-id = ; }; }; }; seninf_n3d_top: seninf-n3d-top@1a004000 { compatible = "mediatek,seninf_n3d_top"; interrupts = ; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>; reg = <0 0x1a004000 0 0x100>, <0 0x1a004100 0 0x100>, <0 0x1a004200 0 0x100>; reg-names = "seninf_top", "seninf_n3d_a", "seninf_n3d_b"; clocks = <&camsys_main_clk CLK_CAM_M_SENINF>, <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAMTG>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "CAMSYS_SENINF_CGPDN", "CAMSYS_CAM_CGPDN", "CAMSYS_CAMTG_CGPDN", "CAMSYS_CAMTM_SEL"; }; seninf_top:seninf_top@1a004000 { compatible = "mediatek,seninf_top"; reg = <0 0x1a004000 0 0x1000>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>; mediatek,platform = "mt6835"; mediatek,seninf_max_num = "6"; clocks = <&camsys_main_clk CLK_CAM_M_SENINF>, <&topckgen_clk CLK_TOP_SENINF_SEL>, <&topckgen_clk CLK_TOP_SENINF1_SEL>, <&topckgen_clk CLK_TOP_SENINF2_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTG2_SEL>, <&topckgen_clk CLK_TOP_CAMTG3_SEL>, <&topckgen_clk CLK_TOP_CAMTG4_SEL>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>, <&topckgen_clk CLK_TOP_UNIVPLL_192M_D8>, <&topckgen_clk CLK_TOP_UNIVPLL_D6_D8>, <&topckgen_clk CLK_TOP_UNIVPLL_192M_D4>, <&topckgen_clk CLK_TOP_F26M_CK_D2>, <&topckgen_clk CLK_TOP_UNIVPLL_192M_D16>, <&topckgen_clk CLK_TOP_UNIVPLL_192M_D32>, <&topckgen_clk CLK_TOP_IMGPLL>, <&topckgen_clk CLK_TOP_MMPLL_D7>, <&topckgen_clk CLK_TOP_UNIVPLL_D5>; clock-names = "CAMSYS_SENINF_CGPDN", "TOP_MUX_SENINF", "TOP_MUX_SENINF1", "TOP_MUX_SENINF2", "TOP_MUX_CAMTG", "TOP_MUX_CAMTG2", "TOP_MUX_CAMTG3", "TOP_MUX_CAMTG4", "TOP_CLK26M", "TOP_UNIVP_192M_D8", "TOP_UNIVPLL_D6_D8", "TOP_UNIVP_192M_D4", "TOP_F26M_CK_D2", "TOP_UNIVP_192M_D16", "TOP_UNIVP_192M_D32", "TOP_IMGPLL", "TOP_MMPLL_D7", "TOP_UNIVPLL_D5"; operating-points-v2 = <&opp_table_cam>; dvfsrc-vcore-supply = <&dvfsrc_vcore>; }; kd_camera_hw1:kd_camera_hw1@1a004000 { compatible = "mediatek,imgsensor"; }; seninf1@1a004000 { compatible = "mediatek,seninf1"; reg = <0 0x1a004000 0 0x1000>; }; seninf2@1a005000 { compatible = "mediatek,seninf2"; reg = <0 0x1a005000 0 0x1000>; }; seninf3@1a006000 { compatible = "mediatek,seninf3"; reg = <0 0x1a006000 0 0x1000>; }; seninf4@1a007000 { compatible = "mediatek,seninf4"; reg = <0 0x1a007000 0 0x1000>; }; seninf5@1a008000 { compatible = "mediatek,seninf5"; reg = <0 0x1a008000 0 0x1000>; }; seninf6@1a009000 { compatible = "mediatek,seninf6"; reg = <0 0x1a009000 0 0x1000>; }; pwrap??@1000d000 { compatible = "mediatek,pwrap??"; reg = <0 0x1000d000 0 0x1000>; }; drm: drm@1000d000 { compatible = "mediatek,dbgtop-drm"; reg = <0 0x1000d000 0 0x1000>; }; devapc_ao_infra_peri@1000e000 { compatible = "mediatek,devapc_ao_infra_peri"; reg = <0 0x1000e000 0 0x1000>; }; sleep_reg_md@1000f000 { compatible = "mediatek,sleep_reg_md"; reg = <0 0x1000f000 0 0x1000>; }; pmsr_apb@1000f000 { compatible = "mediatek,pmsr_apb"; reg = <0 0x1000f000 0 0x800>; }; topmisc@10011000 { compatible = "mediatek,topmisc"; reg = <0 0x10011000 0 0x1000>; }; mbist_ao@10013000 { compatible = "mediatek,mbist_ao"; reg = <0 0x10013000 0 0x1000>; }; apcldmain_ao@10014000 { compatible = "mediatek,apcldmain_ao"; reg = <0 0x10014000 0 0x400>; }; apcldmaout_ao@10014400 { compatible = "mediatek,apcldmaout_ao"; reg = <0 0x10014400 0 0x400>; }; apcldmamisc_ao@10014800 { compatible = "mediatek,apcldmamisc_ao"; reg = <0 0x10014800 0 0x400>; }; apcldmamisc_ao@10014c00 { compatible = "mediatek,apcldmamisc_ao"; reg = <0 0x10014c00 0 0x400>; }; devapc_mpu_ao@10015000 { compatible = "mediatek,devapc_mpu_ao"; reg = <0 0x10015000 0 0x1000>; }; mdcldmaout_ao@10015400 { compatible = "mediatek,mdcldmaout_ao"; reg = <0 0x10015400 0 0x400>; }; mdcldmamisc_ao@10015800 { compatible = "mediatek,mdcldmamisc_ao"; reg = <0 0x10015800 0 0x400>; }; aes_top0@10016000 { compatible = "mediatek,aes_top0"; reg = <0 0x10016000 0 0x1000>; }; modem_temp_share@10018000 { compatible = "mediatek,modem_temp_share"; reg = <0 0x10018000 0 0x1000>; }; devapc_ao_md@10019000 { compatible = "mediatek,devapc_ao_md"; reg = <0 0x10019000 0 0x1000>; }; masp@1000a000 { compatible = "mediatek,masp"; reg = <0 0x1000a000 0 0x1000>; interrupts = ; /* GIC_IRQ ID(sej_axgpt_irq) - 32 = 279 - 32 = 247 */ }; security_ao@1001a000 { compatible = "mediatek,security_ao"; reg = <0 0x1001a000 0 0x1000>; }; topckgen_ao@1001b000 { compatible = "mediatek,topckgen_ao"; reg = <0 0x1001b000 0 0x1000>; }; devapc_ao_mm@1001c000 { compatible = "mediatek,devapc_ao_mm"; reg = <0 0x1001c000 0 0x1000>; }; sleep_sram@1001e000 { compatible = "mediatek,sleep_sram"; reg = <0 0x1001e000 0 0x4000>; }; devapc_ao_infra_peri@10025000 { compatible = "mediatek,devapc_ao_infra_peri"; reg = <0 0x10025000 0 0x1000>; }; sys_cirq@10204000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10204000 0 0x1000>; interrupts = ; }; mcucfg@10200000 { compatible = "mediatek,mcucfg"; reg = <0 0x10200000 0 0x1000>; }; mcucfg@10201000 { compatible = "mediatek,mcucfg"; reg = <0 0x10201000 0 0x1000>; }; mcucfg@10202000 { compatible = "mediatek,mcucfg"; reg = <0 0x10202000 0 0x1000>; }; mcucfg@10203000 { compatible = "mediatek,mcucfg"; reg = <0 0x10203000 0 0x1000>; }; devapc@10207000 { compatible = "mediatek,mt6835-devapc"; reg = <0 0x10207000 0 0x1000>, /* infra pd */ <0 0x10274000 0 0x1000>, /* infra1 pd */ <0 0x11020000 0 0x1000>, /* peri pd */ <0 0x1c01c000 0 0x1000>, /* vlp pd */ <0 0x1e826000 0 0x1000>, /* fake adsp pd */ <0 0x1e826000 0 0x1000>, /* mminfra pd */ <0 0x1eca4000 0 0x1000>, /* mmup pd */ <0 0x10030000 0 0x1000>, /* infra ao */ <0 0x1103c000 0 0x1000>, /* peri ao */ <0 0x1c018000 0 0x1000>, /* vlp ao */ <0 0x1e820000 0 0x1000>, /* fake adsp ao */ <0 0x1e820000 0 0x1000>, /* mminfra ao*/ <0 0x1eca0000 0 0x1000>, /* mmup ao*/ <0 0x1020e000 0 0x1000>, /* infracfg */ <0 0x10033000 0 0x1000>, /* swp */ <0 0x0010c000 0 0x1000>; /* sramrom */ interrupts = , /* infra irq */ , /* fake peri irq */ , /* vlp irq */ , /* fake adsp irq */ , /* mminfra irq */ ; /* mmup irq */ }; bus_dbg@10208000 { compatible = "mediatek,bus_dbg"; reg = <0 0x10208000 0 0x1000>; }; ap_ccif0@10209000 { compatible = "mediatek,ap_ccif0"; reg = <0 0x10209000 0 0x1000>; }; md_ccif0@1020a000 { compatible = "mediatek,md_ccif0"; reg = <0 0x1020a000 0 0x1000>; }; ap_ccif1@1020b000 { compatible = "mediatek,ap_ccif1"; reg = <0 0x1020b000 0 0x1000>; }; md_ccif1@1020c000 { compatible = "mediatek,md_ccif1"; reg = <0 0x1020c000 0 0x1000>; }; infra_mbist@1020d000 { compatible = "mediatek,infra_mbist"; reg = <0 0x1020d000 0 0x1000>; }; infracfg@1020e000 { compatible = "mediatek,infracfg", "syscon", "simple-mfd"; reg = <0 0x1020e000 0 0x1000>; infracfg_rst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < 0xf50 15 0xf54 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */ 0xf20 19 0xf24 19 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */ >; }; }; trng@1020f000 { compatible = "mediatek,trng"; reg = <0 0x1020f000 0 0x1000>; interrupts = ; }; dxcc_sec@10210000 { compatible = "mediatek,dxcc_sec"; reg = <0 0x10210000 0 0x1000>; interrupts = ; }; md2md_md1_ccif0@10211000 { compatible = "mediatek,md2md_md1_ccif0"; reg = <0 0x10211000 0 0x1000>; }; cq_dma@10212000 { compatible = "mediatek,cq_dma"; reg = <0 0x10212000 0 0x1000>; interrupts = ; }; md2md_md2_ccif0@10213000 { compatible = "mediatek,md2md_md2_ccif0"; reg = <0 0x10213000 0 0x1000>; }; sramrom@10214000 { compatible = "mediatek,sramrom"; reg = <0 0x10214000 0 0x1000>; }; infra_bcrm@10215000 { compatible = "mediatek,infra_bcrm"; reg = <0 0x10215000 0 0x1000>; }; dbg_tracker2@10218000 { compatible = "mediatek,dbg_tracker2"; reg = <0 0x10218000 0 0x1000>; }; apdma: dma-controller@11300900 { compatible = "mediatek,mt6779-uart-dma"; reg = <0 0x11300900 0 0x80>, <0 0x11300980 0 0x80>, <0 0x11300a00 0 0x80>, <0 0x11300a80 0 0x80>; interrupts = , , , ; clocks = <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "apdma"; dma-requests = <4>; #dma-cells = <1>; }; uart0: serial@11001000 { compatible = "mediatek,mt6577-uart"; reg = <0 0x11001000 0 0x1000>; interrupts = ; clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAOP_UART0>; clock-names = "baud", "bus"; dmas = <&apdma 0 &apdma 1>; dma-names = "tx", "rx"; uart_line = <0>; }; uart1: serial@11002000 { compatible = "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = ; clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAOP_UART1>; clock-names = "baud", "bus"; dmas = <&apdma 2 &apdma 3>; dma-names = "tx", "rx"; uart_line = <1>; }; spi0: spi0@11010000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11010000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI0_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi1: spi1@11011000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11011000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI1_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; tee-only; }; spi2: spi2@11012000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11012000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI2_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi3: spi3@11013000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11013000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI3_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi4: spi4@11014000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11014000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI4_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi5: spi5@11015000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11015000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI5_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi6: spi6@11016000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11016000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI6_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi7: spi7@11017000 { compatible = "mediatek,mt6983-spi"; mediatek,pad-select = <0>; reg = <0 0x11017000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAOP_SPI7_BCLK>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; goodix_fp: fingerprint { compatible = "mediatek,goodix-fp"; }; mminfra-imax { compatible = "mediatek,mminfra-imax"; reg = <0 0x14000000 0 0x1000>, /* dispsys */ <0 0x14021000 0 0x1000>, /* disp_larb_0 */ <0 0x14022000 0 0x1000>; /* disp_larb_1 */ disp-larb0-fake-port = <4>; disp-larb1-fake-port = <4>; reg-names = "dispsys", "disp_larb_0", "disp_larb_1"; }; efuse: efuse@11c10000 { compatible = "mediatek,devinfo"; reg = <0 0x11c10000 0 0x10000>; #address-cells = <1>; #size-cells = <1>; efuse_segment: segment@1c { reg = <0x1c 0x4>; }; u3_phy_data: u3-phy-data@1ac { reg = <0x1ac 0x4>; }; u2_phy_data: u2-phy-data@1b0 { reg = <0x1b0 0x4>; }; lvts_e_data1: data1 { reg = <0x1d0 0x10>; }; lvts_e_data2: data2 { reg = <0x2f8 0x38>; }; lkginfo: lkg { reg = <0x218 0x18>; }; }; i2c0: i2c@11ed0000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11ed0000 0 0x1000>, <0 0x11300080 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C0>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c1: i2c@11db0000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11db0000 0 0x1000>, <0 0x11300100 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C1>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c2: i2c@11ed1000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11ed1000 0 0x1000>, <0 0x11300180 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C2>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c3: i2c@11b20000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11b20000 0 0x1000>, <0 0x11300280 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_ws_clk CLK_IMPWS_AP_CLOCK_I2C3>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c4: i2c@11ed2000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11ed2000 0 0x1000>, <0 0x11300300 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C4>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c5: i2c@11b21000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11b21000 0 0x1000>, <0 0x11300400 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_ws_clk CLK_IMPWS_AP_CLOCK_I2C5>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c6: i2c@11db1000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11db1000 0 0x1000>, <0 0x11300480 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C6>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c7: i2c@11db2000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11db2000 0 0x1000>, <0 0x11300500 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C7>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c8: i2c@11db3000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11db3000 0 0x1000>, <0 0x11300600 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C8>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c9: i2c@11ed3000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11ed3000 0 0x1000>, <0 0x11300700 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C9>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c10: i2c@11280000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11280000 0 0x1000>, <0 0x11300800 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_c_clk CLK_IMPC_AP_CLOCK_I2C10>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; i2c11: i2c@11281000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11281000 0 0x1000>, <0 0x11300880 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_c_clk CLK_IMPC_AP_CLOCK_I2C11>, <&pericfg_ao_clk CLK_PERAOP_APDMA>; clock-names = "main", "dma"; clock-div = <1>; }; emi@10219000 { compatible = "mediatek,emi"; reg = <0 0x10219000 0 0x1000>; interrupts = ; }; device_mpu_low@1021a000 { compatible = "mediatek,device_mpu_low"; reg = <0 0x1021a000 0 0x1000>; prot-base = <0x0 0x40000000>; prot-size = <0x4 0x00000000>; page-size = <0x200000>; interrupts = ; }; infra_device_mpu@1021b000 { compatible = "mediatek,infra_device_mpu"; reg = <0 0x1021b000 0 0x1000>; }; infracfg_mem@1021c000 { compatible = "mediatek,infracfg_mem"; reg = <0 0x1021c000 0 0x1000>; }; apcldmain@1021f000 { compatible = "mediatek,apcldmain"; reg = <0 0x1021f000 0 0x1000>; }; apcldmaout@1021b400 { compatible = "mediatek,apcldmaout"; reg = <0 0x1021b400 0 0x400>; }; apcldmamisc@1021b800 { compatible = "mediatek,apcldmamisc"; reg = <0 0x1021b800 0 0x400>; }; apcldmamisc@1021bc00 { compatible = "mediatek,apcldmamisc"; reg = <0 0x1021bc00 0 0x400>; }; mdcldmain@1021c000 { compatible = "mediatek,mdcldmain"; reg = <0 0x1021c000 0 0x400>; }; mdcldmaout@1021c400 { compatible = "mediatek,mdcldmaout"; reg = <0 0x1021c400 0 0x400>; }; mdcldmamisc@1021c800 { compatible = "mediatek,mdcldmamisc"; reg = <0 0x1021c800 0 0x400>; }; mdcldmamisc@1021cc00 { compatible = "mediatek,mdcldmamisc"; reg = <0 0x1021cc00 0 0x400>; }; infra_md@1021d000 { compatible = "mediatek,infra_md"; reg = <0 0x1021d000 0 0x1000>; }; bpi_bsi_slv0@1021e000 { compatible = "mediatek,bpi_bsi_slv0"; reg = <0 0x1021e000 0 0x1000>; }; bpi_bsi_slv1@1021f000 { compatible = "mediatek,bpi_bsi_slv1"; reg = <0 0x1021f000 0 0x1000>; }; bpi_bsi_slv2@10225000 { compatible = "mediatek,bpi_bsi_slv2"; reg = <0 0x10225000 0 0x1000>; }; m4u@10220000 { compatible = "mediatek,m4u"; reg = <0 0x10220000 0 0x1000>; }; m4u@10221000 { compatible = "mediatek,m4u"; reg = <0 0x10221000 0 0x1000>; }; m4u@10222000 { compatible = "mediatek,m4u"; reg = <0 0x10222000 0 0x1000>; }; m4u@10223000 { compatible = "mediatek,m4u"; reg = <0 0x10223000 0 0x1000>; }; apdma@10220000 { compatible = "mediatek,apdma"; reg = <0 0x10220000 0 0x4000>; }; m4u@10224000 { compatible = "mediatek,m4u"; reg = <0 0x10224000 0 0x1000>; }; emi_mpu@10226000 { compatible = "mediatek,emi_mpu"; reg = <0 0x10226000 0 0x1000>; interrupts = ; }; infra_dpmaif@1022c000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022c000 0 0x1000>; }; infra_dpmaif@1022d000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022d000 0 0x1000>; }; infra_dpmaif@1022e000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022e000 0 0x1000>; }; infra_dpmaif@1022f000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022f000 0 0x1000>; }; dramc: dramc@10230000 { compatible = "mediatek,mt6835-dramc", "mediatek,common-dramc"; reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */ <0 0x10240000 0 0x2000>, /* DRAMC AO CHB */ <0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */ <0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */ <0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */ <0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */ <0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */ <0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */ <0 0x10006000 0 0x1000>; /* SLEEP BASE */ mr4_version = <1>; mr4_rg = <0x0090 0x0000ffff 0>; fmeter_version = <1>; crystal_freq = <52>; pll_id = <0x050c 0x00000100 8>; shu_lv = <0x050c 0x00030000 16>; shu_of = <0x700>; sdmpcw = <0x0704 0xffff0000 16>, <0x0724 0xffff0000 16>; prediv = <0x0708 0x000c0000 18>, <0x0728 0x000c0000 18>; posdiv = <0x0708 0x00000007 0>, <0x0728 0x00000007 0>; ckdiv4 = <0x0874 0x00000004 2>, <0x0874 0x00000004 2>; pll_md = <0x0744 0x00000100 8>, <0x0744 0x00000100 8>; cldiv2 = <0x08b4 0x00000002 1>, <0x08b4 0x00000002 1>; fbksel = <0x070c 0x00000040 6>, <0x070c 0x00000040 6>; dqsopen = <0x0870 0x00100000 20>, <0x0870 0x00100000 20>; dqopen = <0x0870 0x00200000 21>, <0x0870 0x00200000 21>; ckdiv4_ca = <0x0b74 0x00000004 2>, <0x0b74 0x00000004 2>; }; ap_ccif2@1023c000 { compatible = "mediatek,ap_ccif2"; reg = <0 0x1023c000 0 0x1000>; }; md_ccif2@1023d000 { compatible = "mediatek,md_ccif2"; reg = <0 0x1023d000 0 0x1000>; }; ap_ccif3@1023e000 { compatible = "mediatek,ap_ccif3"; reg = <0 0x1023e000 0 0x1000>; }; md_ccif3@1023f000 { compatible = "mediatek,md_ccif3"; reg = <0 0x1023f000 0 0x1000>; }; dramc_ch1_top0@10240000 { compatible = "mediatek,dramc_ch1_top0"; reg = <0 0x10240000 0 0x2000>; interrupts = ; }; dramc_ch1_top1@10242000 { compatible = "mediatek,dramc_ch1_top1"; reg = <0 0x10242000 0 0x2000>; }; dramc_ch1_top2@10244000 { compatible = "mediatek,dramc_ch1_top2"; reg = <0 0x10244000 0 0x1000>; }; dramc_ch1_top3@10245000 { compatible = "mediatek,dramc_ch1_top3"; reg = <0 0x10245000 0 0x1000>; }; dramc_ch1_rsv@10246000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10246000 0 0x2000>; }; dramc_ch1_rsv@10248000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10248000 0 0x2000>; }; dramc_ch1_rsv@1024a000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x1024a000 0 0x2000>; }; ap_ccif4@1024c000 { compatible = "mediatek,ap_ccif4"; reg = <0 0x1024c000 0 0x1000>; }; auxadc: auxadc@11072000 { compatible = "mediatek,mt6765-auxadc"; reg = <0 0x11072000 0 0x1000>; clocks = <&pericfg_ao_clk CLK_AUXADC_BCLK_AP>; clock-names = "main"; #io-channel-cells = <1>; /* Auxadc efuse calibration */ /* 1. Auxadc cali on/off bit shift */ mediatek,cali-en-bit = <20>; /* 2. Auxadc cali ge bits shift */ mediatek,cali-ge-bit = <10>; /* 3. Auxadc cali oe bits shift */ mediatek,cali-oe-bit = <0>; /* 4. Auxadc cali efuse reg offset */ mediatek,cali-efuse-reg-offset = <0x1c4>; nvmem = <&efuse>; nvmem-names = "mtk_efuse"; #interconnect-cells = <1>; }; pwm@11008000 { compatible = "mediatek,pwm"; reg = <0 0x11008000 0 0x1000>; interrupts = ; clocks = <&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK1>, <&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK2>, <&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK3>, <&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK4>, <&pericfg_ao_clk CLK_PERAOP_PWM_HCLK>, <&pericfg_ao_clk CLK_PERAOP_PWM_BCLK>; clock-names = "PWM1-main", "PWM2-main", "PWM3-main", "PWM4-main", "PWM-HCLK-main", "PWM-main"; /* 1. pwm periclk control reg offset */ mediatek,pwm-topclk-ctl-reg = <0x24>; /* 2. pwm bclk sw ctrl offset */ mediatek,pwm-bclk-sw-ctrl-offset = <12>; /* 3. pwm_x bclk sw ctrl offset */ mediatek,pwm1-bclk-sw-ctrl-offset = <20>; mediatek,pwm2-bclk-sw-ctrl-offset = <18>; mediatek,pwm3-bclk-sw-ctrl-offset = <16>; mediatek,pwm4-bclk-sw-ctrl-offset = <14>; /* 4. pwm clock all on off wa support */ mediatek,pwm-clk-all-on-off; /* 5. pwm version */ mediatek,pwm-version = <0x2>; pwmsrcclk = <&pericfg_ao_clk>; }; irtx_pwm:irtx_pwm { compatible = "mediatek,irtx-pwm"; pwm_ch = <0>; pwm_data_invert = <0>; }; md_ccif4@1024d000 { compatible = "mediatek,md_ccif4"; reg = <0 0x1024d000 0 0x1000>; }; dramc_ch1_top0@10250000 { compatible = "mediatek,dramc_ch1_top0"; reg = <0 0x10250000 0 0x2000>; }; dramc_ch1_top1@10252000 { compatible = "mediatek,dramc_ch1_top1"; reg = <0 0x10252000 0 0x2000>; }; dramc_ch1_top2@10254000 { compatible = "mediatek,dramc_ch1_top2"; reg = <0 0x10254000 0 0x1000>; }; dramc_ch1_top3@10255000 { compatible = "mediatek,dramc_ch1_top3"; reg = <0 0x10255000 0 0x1000>; }; dramc_ch1_rsv@10256000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10256000 0 0x2000>; }; dramc_ch1_rsv@10258000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10258000 0 0x2000>; }; dramc_ch1_rsv@1025a000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x1025a000 0 0x2000>; }; ap_ccif5@1025c000 { compatible = "mediatek,ap_ccif5"; reg = <0 0x1025c000 0 0x1000>; }; md_ccif5@1025d000 { compatible = "mediatek,md_ccif5"; reg = <0 0x1025d000 0 0x1000>; }; mm_vpu_m0_sub_common@1025e000 { compatible = "mediatek,mm_vpu_m0_sub_common"; reg = <0 0x1025e000 0 0x1000>; }; mm_vpu_m1_sub_common@1025f000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1025f000 0 0x1000>; }; dramc_ch1_top0@10260000 { compatible = "mediatek,dramc_ch1_top0"; reg = <0 0x10260000 0 0x2000>; }; dramc_ch1_top1@10262000 { compatible = "mediatek,dramc_ch1_top1"; reg = <0 0x10262000 0 0x2000>; }; dramc_ch1_top2@10264000 { compatible = "mediatek,dramc_ch1_top2"; reg = <0 0x10264000 0 0x1000>; }; dramc_ch1_top3@10265000 { compatible = "mediatek,dramc_ch1_top3"; reg = <0 0x10265000 0 0x1000>; }; dramc_ch1_rsv@10266000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10266000 0 0x2000>; }; dramc_ch1_rsv@10268000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10268000 0 0x2000>; }; dramc_ch1_rsv@1026a000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x1026a000 0 0x2000>; }; infracfg_ao_mem@10270000 { compatible = "mediatek,infracfg_ao_mem"; reg = <0 0x10270000 0 0x1000>; }; mm_vpu_m1_sub_common@1030c000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1030c000 0 0x1000>; }; mm_vpu_m1_sub_common@1030d000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1030d000 0 0x1000>; }; sys_cirq@10312000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10312000 0 0x1000>; }; sys_cirq@10313000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10313000 0 0x1000>; }; sys_cirq@10314000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10314000 0 0x1000>; }; sys_cirq@10350000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10350000 0 0x1000>; }; sys_cirq@10351000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10351000 0 0x1000>; }; sys_cirq@10352000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10352000 0 0x1000>; }; sys_cirq@10354000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10354000 0 0x1000>; }; sys_cirq@10355000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10355000 0 0x1000>; }; sys_cirq@10356000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10356000 0 0x1000>; }; dramc_ch1_rsv@10940000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10940000 0 0xc0000>; }; dramc_ch1_rsv@10a00000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10a00000 0 0x40000>; }; dramc_ch1_rsv@10a40000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10a40000 0 0xc0000>; }; dramc_ch1_rsv@10b00000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10b00000 0 0x40000>; }; dramc_ch1_rsv@10b40000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10b40000 0 0xc0000>; }; dramc_ch1_rsv@10c00000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10c00000 0 0x40000>; }; dramc_ch1_rsv@10c40000 { compatible = "mediatek,dramc_ch1_rsv"; reg = <0 0x10c40000 0 0xc0000>; }; gic500@c000000 { compatible = "mediatek,gic500"; reg = <0 0x0c000000 0 0x400000>; }; gic_cpu@c400000 { compatible = "mediatek,gic_cpu"; reg = <0 0x0c400000 0 0x40000>; }; dfd@c600000 { compatible = "mediatek,dfd"; reg = <0 0x0c600000 0 0x100000>; }; dbg_cti@d020000 { compatible = "mediatek,dbg_cti"; reg = <0 0x0d020000 0 0x10000>; }; dbg_etr@d030000 { compatible = "mediatek,dbg_etr"; reg = <0 0x0d030000 0 0x1000>; }; dbg_dem@d0a0000 { compatible = "mediatek,dbg_dem"; reg = <0 0x0d0a0000 0 0x10000>; }; dbg_mdsys1@d100000 { compatible = "mediatek,dbg_mdsys1"; reg = <0 0x0d100000 0 0x100000>; }; dpmaif:dpmaif@10014000 { compatible = "mediatek,dpmaif"; reg = <0 0x10014000 0 0x1000>, /*AO_UL*/ <0 0x1022d000 0 0x1000>, /*PD_UL*/ <0 0x1022c000 0 0x1000>, /*PD_MD_MISC*/ <0 0x1022e000 0 0x1000>; /*SRAM*/ /* rxq0 irq: 142 238 270 */ interrupts = , ; /* new rxq1 irq: 163 259 291 */ mediatek,dpmaif-ver = <3>; mediatek,dpmaif-cap = <0x00000004>; mediatek,plat-info = <6835>; /* skb-gfp-mask for skb alloc mask, 1 is GFP_ATOMIC */ mediatek,skb-gfp-mask = <1>; clocks = <&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>, <&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>, <&infracfg_ao_clk CLK_IFRAO_RG_MMW_DPMAIF26M_CK>; clock-names = "infra-dpmaif-clk", "infra-dpmaif-blk-clk", "infra-dpmaif-rg-mmw-clk"; interconnects = <&dvfsrc MT6873_MASTER_NETSYS &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "icc-mdspd-bw"; required-opps = <&dvfsrc_freq_opp0>, <&dvfsrc_freq_opp1>; net-spd-ver = <6>; hw-reset-ver = <1>; dpmaif-infracfg = <&infracfg_ao_clk>; }; ccifdriver:ccifdriver@10209000 { compatible = "mediatek,ccci_ccif"; reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/ <0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/ mediatek,sram-size = <512>; /* ccif hw reset version */ mediatek,ccif-hw-reset-ver = <1>; /* ccif hw reset bit */ mediatek,ccif-hw-reset-bit = <18>; /* DTS/GIC_ID: CCIF0 228/260; CCIF0 229/261 */ interrupts = , ; clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF_AP>, <&infracfg_ao_clk CLK_IFRAO_CCIF_MD>, <&infracfg_ao_clk CLK_IFRAO_CCIF1_AP>, <&infracfg_ao_clk CLK_IFRAO_CCIF1_MD>, <&infracfg_ao_clk CLK_IFRAO_CCIF4_MD>; clock-names = "infra-ccif-ap", "infra-ccif-md", "infra-ccif1-ap", "infra-ccif1-md", "infra-ccif4-md"; }; mddriver:mddriver { compatible = "mediatek,mddriver"; /* bit0~3: CLDMA|CCIF|DPMAIF */ mediatek,mdhif-type = <6>; mediatek,md-id = <0>; mediatek,ap-plat-info = <6835>; mediatek,md-generation = <6299>; /* 0x44: epon offset; */ /* 0x06: once a value[1] exist, means in l2sram */ /* value[1] not exist means in mddbgsys. the value(6) has no meaningful */ mediatek,offset-epon-md1 = <0x64 0x06>; mediatek,cldma-capability = <14>; /* bit0:srcclkena|bit1:srclken-o1-on|bit2:revert-sequencer*/ /* bit3:pll-setting|bit4:md1-disable-sequencer */ mediatek,power-flow-config = <0x2>; /* srclken-o1 set value |= 1<<14 */ mediatek,srclken-o1 = <0x4000>; reg = <0 0x0d180000 0 0x2000>; /* l2sram base address */ /* DTS/GIC_ID: MDWDT 543/575/; CCIF0 228/260; CCIF0 229/261 */ interrupts = , , ; power-domains = <&scpsys MT6835_POWER_DOMAIN_MD>; ccci-infracfg = <&infracfg_ao_clk>; ccci-topckgen = <&topckgen_clk>; ccci-spmsleep = <&apccci_mdo1>; #address-cells = <2>; #size-cells = <2>; ranges; md-bus-addr@0 { compatible = "mediatek,md-bus"; reg = <0 0x21a00200 0 0x4>; }; }; md_auxadc:md-auxadc { compatible = "mediatek,md_auxadc"; io-channels = <&auxadc 6>; io-channel-names = "md-channel"; }; ccci_scp:ccci-scp { compatible = "mediatek,ccci_md_scp"; reg = <0 0x1023c000 0 0x1000>, /*AP_CCIF2_BASE*/ <0 0x1023d000 0 0x1000>; /*MD_CCIF2_BASE*/ clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF2_AP>, <&infracfg_ao_clk CLK_IFRAO_CCIF2_MD>; clock-names = "infra-ccif2-ap", "infra-ccif2-md"; }; gpio_usage_mapping:gpio { compatible = "mediatek,gpio_usage_mapping"; }; md1_sim1_hot_plug_eint:MD1-SIM1-HOT-PLUG-EINT { }; md1_sim2_hot_plug_eint:MD1-SIM2-HOT-PLUG-EINT { }; dfd@13e00000 { compatible = "mediatek,dfd"; reg = <0 0x13e00000 0 0x112000>; }; g3d_dvfs@13fbb000 { compatible = "mediatek,g3d_dvfs"; reg = <0 0x13fbb000 0 0x1000>; }; g3d_config@13fbc000 { compatible = "mediatek,g3d_config"; reg = <0 0x13fbc000 0 0x1000>; }; g3d_config@13fbd000 { compatible = "mediatek,g3d_config"; reg = <0 0x13fbd000 0 0x1000>; }; g3d_config@13fbf000 { compatible = "mediatek,g3d_config"; reg = <0 0x13fbf000 0 0x1000>; }; mtkfb: mtkfb@0 { compatible = "mediatek,mtkfb"; }; mminfra-debug@1e827000 { compatible = "mediatek,mminfra-debug"; reg = <0 0x1e827000 0 0x80>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; interrupts = ; mminfra-bkrs = <1>; bkrs-reg = <0x1e800280>; init-clk-on; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "clk0", "clk1", "clk2", "clk3"; }; disp_pwm: disp_pwm0@1100e000 { compatible = "mediatek,disp_pwm0", "mediatek,mt6835-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; interrupts = ; #pwm-cells = <2>; clocks = <&pericfg_ao_clk CLK_PERAOP_DISP_PWM0>, <&topckgen_clk CLK_TOP_DISP_PWM_SEL>, <&topckgen_clk CLK_TOP_OSC_D4>; clock-names = "main", "mm", "pwm_src"; }; dispsys_config: dispsys_config@14000000 { compatible = "mediatek,mt6835-mmsys"; reg = <0 0x14000000 0 0x1000>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_OVL_RDMA0>; fake-engine = <&smi_larb0 M4U_PORT_L0_DISP_FAKE1>, <&smi_larb1 M4U_PORT_L1_DISP_FAKE1>; nvmem-cells = <&efuse_segment>; nvmem-cell-names = "efuse_seg_disp_cell"; clocks = <&dispsys_config_clk CLK_MM_APB_BUS>, <&dispsys_config_clk CLK_MM_DISP_HRT_URGENT>, <&dispsys_config_clk CLK_MM_DISP_MUTEX0>; clock-num = <3>; power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>; operating-points-v2 = <&opp_table_disp0>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; interconnects = <&mmqos SLAVE_LARB(21) &mmqos SLAVE_COMMON(0)>; interconnect-names = "disp_hrt_qos"; pre-define-bw = <0xffffffff>, <0>, <0>, <0>; /* define threads, see mt6835-gce.h */ mediatek,mailbox-gce = <&gce>; mboxes = <&gce 0 0 CMDQ_THR_PRIO_4>, <&gce 1 0 CMDQ_THR_PRIO_4>, <&gce 2 0 CMDQ_THR_PRIO_4>, <&gce 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>, <&gce 4 0 CMDQ_THR_PRIO_4>, <&gce 6 0 CMDQ_THR_PRIO_3>; gce-client-names = "CLIENT_CFG0", "CLIENT_CFG1", "CLIENT_CFG2", "CLIENT_TRIG_LOOP0", "CLIENT_SUB_CFG0", "CLIENT_DSI_CFG0"; gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, <&gce 0x14010000 SUBSYS_1401XXXX>, <&gce 0x14020000 SUBSYS_1402XXXX>; gce-event-names = "disp_mutex0_eof", "disp_token_stream_dirty0", "disp_wait_dsi0_te", "disp_token_stream_eof0", "disp_dsi0_eof", "disp_token_esd_eof0", "disp_rdma0_eof0", "disp_wdma0_eof0", "disp_token_stream_block0", "disp_token_cabc_eof0", "disp_wdma0_eof2", "disp_dsi0_sof0", "disp_token_disp_va_start0", "disp_token_disp_va_end0", "disp_token_disp_va_start2", "disp_token_disp_va_end2"; gce-events = <&gce CMDQ_EVENT_DISPSYS_STREAM_DONE_ENG_EVENT_0>, <&gce CMDQ_SYNC_TOKEN_CONFIG_DIRTY>, <&gce CMDQ_EVENT_DISPSYS_DSI0_TE_ENG_EVENT>, <&gce CMDQ_SYNC_TOKEN_STREAM_EOF>, <&gce CMDQ_EVENT_DISPSYS_DSI0_FRAME_DONE>, <&gce CMDQ_SYNC_TOKEN_ESD_EOF>, <&gce CMDQ_EVENT_DISPSYS_DISP_RDMA0_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS_DISP_WDMA0_FRAME_DONE>, <&gce CMDQ_SYNC_TOKEN_STREAM_BLOCK>, <&gce CMDQ_SYNC_TOKEN_CABC_EOF>, <&gce CMDQ_EVENT_DISPSYS_DISP_WDMA0_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_SOF>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_START>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_END>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_START>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_END>; helper-name = "MTK_DRM_OPT_STAGE", "MTK_DRM_OPT_USE_CMDQ", "MTK_DRM_OPT_USE_M4U", "MTK_DRM_OPT_MMQOS_SUPPORT", "MTK_DRM_OPT_MMDVFS_SUPPORT", "MTK_DRM_OPT_SODI_SUPPORT", "MTK_DRM_OPT_IDLE_MGR", "MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE", "MTK_DRM_OPT_IDLEMGR_BY_REPAINT", "MTK_DRM_OPT_IDLEMGR_ENTER_ULPS", "MTK_DRM_OPT_IDLEMGR_KEEP_LP11", "MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING", "MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ", "MTK_DRM_OPT_MET_LOG", "MTK_DRM_OPT_USE_PQ", "MTK_DRM_OPT_ESD_CHECK_RECOVERY", "MTK_DRM_OPT_ESD_CHECK_SWITCH", "MTK_DRM_OPT_PRESENT_FENCE", "MTK_DRM_OPT_RDMA_UNDERFLOW_AEE", "MTK_DRM_OPT_DSI_UNDERRUN_AEE", "MTK_DRM_OPT_HRT", "MTK_DRM_OPT_HRT_MODE", "MTK_DRM_OPT_DELAYED_TRIGGER", "MTK_DRM_OPT_OVL_EXT_LAYER", "MTK_DRM_OPT_AOD", "MTK_DRM_OPT_RPO", "MTK_DRM_OPT_DUAL_PIPE", "MTK_DRM_OPT_DC_BY_HRT", "MTK_DRM_OPT_OVL_WCG", "MTK_DRM_OPT_OVL_SBCH", "MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK", "MTK_DRM_OPT_MET", "MTK_DRM_OPT_REG_PARSER_RAW_DUMP", "MTK_DRM_OPT_VP_PQ", "MTK_DRM_OPT_GAME_PQ", "MTK_DRM_OPT_MMPATH", "MTK_DRM_OPT_HBM", "MTK_DRM_OPT_VDS_PATH_SWITCH", "MTK_DRM_OPT_LAYER_REC", "MTK_DRM_OPT_CLEAR_LAYER", "MTK_DRM_OPT_LFR", "MTK_DRM_OPT_SF_PF", "MTK_DRM_OPT_DYN_MIPI_CHANGE", "MTK_DRM_OPT_PRIM_DUAL_PIPE", "MTK_DRM_OPT_MSYNC2_0", "MTK_DRM_OPT_MML_PRIMARY", "MTK_DRM_OPT_DUAL_TE", "MTK_DRM_OPT_VIRTUAL_DISP", "MTK_DRM_OPT_SPHRT", "MTK_DRM_OPT_RES_SWITCH"; helper-value = <0>, /*MTK_DRM_OPT_STAGE*/ <1>, /*MTK_DRM_OPT_USE_CMDQ*/ <1>, /*MTK_DRM_OPT_USE_M4U*/ <1>, /*MTK_DRM_OPT_MMQOS_SUPPORT*/ <1>, /*MTK_DRM_OPT_MMDVFS_SUPPORT*/ <1>, /*MTK_DRM_OPT_SODI_SUPPORT*/ <1>, /*MTK_DRM_OPT_IDLE_MGR*/ <0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/ <1>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/ <0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/ <0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/ <1>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/ <1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/ <0>, /*MTK_DRM_OPT_MET_LOG*/ <1>, /*MTK_DRM_OPT_USE_PQ*/ <1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/ <1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/ <1>, /*MTK_DRM_OPT_PRESENT_FENCE*/ <0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/ <0>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/ <1>, /*MTK_DRM_OPT_HRT*/ <1>, /*MTK_DRM_OPT_HRT_MODE*/ <0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/ <1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/ <1>, /*MTK_DRM_OPT_AOD*/ <1>, /*MTK_DRM_OPT_RPO*/ <0>, /*MTK_DRM_OPT_DUAL_PIPE*/ <0>, /*MTK_DRM_OPT_DC_BY_HRT*/ <0>, /*MTK_DRM_OPT_OVL_WCG*/ <0>, /*MTK_DRM_OPT_OVL_SBCH*/ <1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/ <0>, /*MTK_DRM_OPT_MET*/ <0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/ <0>, /*MTK_DRM_OPT_VP_PQ*/ <0>, /*MTK_DRM_OPT_GAME_PQ*/ <0>, /*MTK_DRM_OPT_MMPATH*/ <0>, /*MTK_DRM_OPT_HBM*/ <0>, /*MTK_DRM_OPT_VDS_PATH_SWITCH*/ <0>, /*MTK_DRM_OPT_LAYER_REC*/ <1>, /*MTK_DRM_OPT_CLEAR_LAYER*/ <1>, /*MTK_DRM_OPT_LFR*/ <0>, /*MTK_DRM_OPT_SF_PF*/ <1>, /*MTK_DRM_OPT_DYN_MIPI_CHANGE*/ <0>, /*MTK_DRM_OPT_PRIM_DUAL_PIPE*/ <0>, /*MTK_DRM_OPT_MSYNC2_0*/ <0>, /*MTK_DRM_OPT_MML_PRIMARY*/ <0>, /*MTK_DRM_OPT_DUAL_TE*/ <0>, /*MTK_DRM_OPT_VIRTUAL_DISP*/ <1>, /*MTK_DRM_OPT_SPHRT*/ <0>; /*MTK_DRM_OPT_RES_SWITCH*/ }; disp_mutex0: disp_mutex@14001000 { compatible = "mediatek,disp_mutex0", "mediatek,mt6835-disp-mutex"; reg = <0 0x14001000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_MUTEX0>; }; disp_ovl0: disp_ovl0@14002000 { compatible = "mediatek,disp_ovl0", "mediatek,mt6835-disp-ovl"; reg = <0 0x14002000 0 0x1000>; interrupts = ; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_OVL_RDMA0>, <&disp_iommu M4U_PORT_L0_OVL_RDMA0_HDR>; clocks = <&dispsys_config_clk CLK_MM_DISP_OVL0>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_OVL_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL0_qos", "DDP_COMPONENT_OVL0_fbdc_qos", "DDP_COMPONENT_OVL0_hrt_qos"; }; disp_ovl1_2l: disp_ovl1_2l@14004000 { compatible = "mediatek,disp_ovl1_2l", "mediatek,mt6835-disp-ovl"; reg = <0 0x14004000 0 0x1000>; interrupts = ; mediatek,larb = <&smi_larb1>; mediatek,smi-id = <1>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L1_OVL_2L_RDMA0>, <&disp_iommu M4U_PORT_L1_OVL_2L_RDMA0_HDR>; clocks = <&dispsys_config_clk CLK_MM_DISP_OVL1_2L>, <&dispsys_config_clk CLK_MM_DISP_DUMMY_MOD_B0>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_OVL_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL1_2L_qos", "DDP_COMPONENT_OVL1_2L_fbdc_qos", "DDP_COMPONENT_OVL1_2L_hrt_qos"; }; disp_rsz0: disp_rsz0@14005000 { compatible = "mediatek,disp_rsz0", "mediatek,mt6835-disp-rsz"; reg = <0 0x14005000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_RSZ0>; }; disp_rdma0: disp_rdma0@14006000 { compatible = "mediatek,disp_rdma0", "mediatek,mt6835-disp-rdma"; reg = <0 0x14006000 0 0x1000>; interrupts = ; mediatek,larb = <&smi_larb1>; mediatek,smi-id = <1>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L1_DISP_RDMA0>; clocks = <&dispsys_config_clk CLK_MM_DISP_RDMA0>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_RDMA0_qos", "DDP_COMPONENT_RDMA0_hrt_qos"; }; disp_c3d0: disp-c3d0@14008000 { compatible = "mediatek,disp_c3d0", "mediatek,mt6835-disp-c3d"; reg = <0 0x14008000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_C3D0>; }; disp_color0: disp_color0@14009000 { compatible = "mediatek,disp_color0", "mediatek,mt6835-disp-color"; reg = <0 0x14009000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_COLOR0>; }; disp_ccorr0: disp_ccorr0@1400a000 { compatible = "mediatek,disp_ccorr0", "mediatek,mt6835-disp-ccorr"; reg = <0 0x1400a000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_CCORR0>; ccorr_bit = <13>; ccorr_num_per_pipe = <1>; ccorr_linear_per_pipe = <0x01>; }; disp_aal0: disp_aal0@1400d000 { compatible = "mediatek,disp_aal0", "mediatek,mt6835-disp-aal"; reg = <0 0x1400d000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_AAL0>; mtk_aal_support = <1>; }; disp_gamma0: disp_gamma0@1400e000 { compatible = "mediatek,disp_gamma0", "mediatek,mt6835-disp-gamma"; reg = <0 0x1400e000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_GAMMA0>; gamma_data_mode = <2>; color_protect_red = <0>; color_protect_green = <0>; color_protect_blue = <0>; color_protect_white = <0>; color_protect_black = <0>; color_protect_lsb = <0>; }; disp_postmask0: disp_postmask0@1400f000 { compatible = "mediatek,disp_postmask0", "mediatek,mt6835-disp-postmask"; reg = <0 0x1400f000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_POSTMASK0>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_POSTMASK0>; }; disp_dither0: disp_dither0@14010000 { compatible = "mediatek,disp_dither0", "mediatek,mt6835-disp-dither"; reg = <0 0x14010000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_DITHER0>; pure_clr_det = <0>; pure_clr_num = <7>; pure_clr_rgb = <255 0 0 0 255 0 0 0 255 255 255 0 255 0 255 0 255 255 255 255 255>; }; mipi_tx_config0: mipi_tx_config@11e50000 { compatible = "mediatek,mipi_tx_config0", "mediatek,mt6835-mipi-tx"; reg = <0 0x11e50000 0 0x1000>; clocks = <&clk26m>; #clock-cells = <0>; #phy-cells = <0>; clock-output-names = "mipi_tx0_pll"; }; gateic0: gateic@0 { compatible = "mediatek,mtk-drm-gateic-drv"; }; disp_dsc0_wrap: disp-dsc-wrap@14015000 { compatible = "mediatek,disp_dsc_wrap", "mediatek,mt6835-disp-dsc"; reg = <0 0x14015000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_DSC_WRAP0>; }; dsi0: dsi@14017000 { compatible = "mediatek,dsi0", "mediatek,mt6835-dsi"; reg = <0 0x14017000 0 0x1000>; interrupts = ; phys = <&mipi_tx_config0>; phy-names = "dphy"; clocks = <&dispsys_config_clk CLK_MM_DISP_DSI0>, <&dispsys_config_clk CLK_MM_DISP_DSI>, <&mipi_tx_config0>; clock-names = "engine", "digital", "hs"; }; dsi_te: dsi_te { compatible = "mediatek, dsi_te-eint"; status = "disabled"; }; mt6382nfc: mt6382nfc { compatible = "mediatek, mt6382_nfc-eint"; interrupt-parent = <&pio>; interrupts = <41 IRQ_TYPE_EDGE_BOTH 41 0>; mt6382-nfc-srclk = <&pio 41 0x0>; status = "disabled"; }; bdgsupport: bdgsupport { compatible = "mediatek,disp,6382,bdg"; }; disp_wdma0: disp_wdma0@14018000 { compatible = "mediatek,disp_wdma0", "mediatek,mt6835-disp-wdma"; reg = <0 0x14018000 0 0x1000>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_WDMA0>; clocks = <&dispsys_config_clk CLK_MM_DISP_WDMA0>; }; reserved@1401d000 { compatible = "mediatek,reserved"; reg = <0 0x1401d000 0 0x1000>; }; disp_dbpi0@1401e000 { compatible = "mediatek,disp_dbpi0"; reg = <0 0x1401e000 0 0x1000>; interrupts = ; }; disp_iommu_bank1: iommu@1e803000 { compatible = "mediatek,common-disp-iommu-bank1"; mediatek,bank-id = <1>; reg = <0 0x1e803000 0 0x1000>; interrupts = ; }; disp_iommu_bank2: iommu@1e804000 { compatible = "mediatek,common-disp-iommu-bank2"; mediatek,bank-id = <2>; reg = <0 0x1e804000 0 0x1000>; interrupts = ; }; disp_iommu_bank3: iommu@1e805000 { compatible = "mediatek,common-disp-iommu-bank3"; mediatek,bank-id = <3>; reg = <0 0x1e805000 0 0x1000>; interrupts = ; }; disp_iommu_bank4: iommu@1e806000 { compatible = "mediatek,common-disp-iommu-bank4"; mediatek,bank-id = <4>; reg = <0 0x1e806000 0 0x1000>; interrupts = ; }; disp_iommu: iommu@1e802000 { compatible = "mediatek,mt6835-disp-iommu"; reg = <0 0x1e802000 0 0x1000>; interrupts = ; mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2 &smi_larb4 &smi_larb7 &smi_larb9 &smi_larb13 &smi_larb16 &smi_larb17 &smi_larb20>; mediatek,iommu_banks = <&disp_iommu_bank1 &disp_iommu_bank2 &disp_iommu_bank3 &disp_iommu_bank4>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; #iommu-cells = <1>; }; ktf_iommu_test { compatible = "mediatek,ktf-iommu-test"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_POSTMASK0>; }; ktf_dmabuf_iommu0 { compatible = "mediatek, mtk_dmabufheap, iommu0"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_FAKE1>; }; ktf_dmabuf_iommu1 { compatible = "mediatek, mtk_dmabufheap, iommu1"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L1_DISP_FAKE1>; }; mtk_iommu_debug { compatible = "mediatek,mt6835-iommu-debug"; }; mtk_iommu_test_dmaheap_normal { compatible = "mediatek,dmaheap-normal"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_POSTMASK0>; }; mtk_sec_dmaheap { compatible = "mediatek,dmaheap-region-base"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_POSTMASK0>; }; mtk_iommu_test0 { compatible = "mediatek,iommu-test-dom0"; dma-ranges = <0x2 0x0 0x2 0x0 0x2 0x0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_POSTMASK0>; }; mtk_iommu_test1 { compatible = "mediatek,iommu-test-dom1"; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L16_IMGO_R1_A>; }; mtk_iommu_test2 { compatible = "mediatek,iommu-test-dom2"; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L4_HW_VDEC_MC_EXT>; }; inlinerot0@14020000 { compatible = "mediatek,inlinerot0"; reg = <0 0x14020000 0 0x1000>; }; i2c@14024000 { compatible = "mediatek,i2c"; reg = <0 0x14024000 0 0x1000>; }; imgsys_config: imgsys_config@15020000 { compatible = "mediatek,imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; mediatek,larb = <&smi_larb9>; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_DIP1>; iommus = <&disp_iommu M4U_PORT_L9_IMGI_D1>, <&disp_iommu M4U_PORT_L9_IMGBI_D1>, <&disp_iommu M4U_PORT_L9_DMGI_D1>, <&disp_iommu M4U_PORT_L9_UFDI_D1>, <&disp_iommu M4U_PORT_L9_LCEI_D1>, <&disp_iommu M4U_PORT_L9_SMTI_D1>, <&disp_iommu M4U_PORT_L9_SMTO_D2>, <&disp_iommu M4U_PORT_L9_SMTO_D1>, <&disp_iommu M4U_PORT_L9_CRZO_D1>, <&disp_iommu M4U_PORT_L9_IMG3O_D1>, <&disp_iommu M4U_PORT_L9_VIPI_D1>, <&disp_iommu M4U_PORT_L9_SMTI_D5>, <&disp_iommu M4U_PORT_L9_TIMGO_D1>; clocks = <&imgsys1_clk CLK_IMGSYS1_LARB9>, <&imgsys1_clk CLK_IMGSYS1_DIP>; clock-names = "DIP_CG_IMG_LARB9", "DIP_CG_IMG_DIP"; }; dip_a0@15021000 { compatible = "mediatek,dip1"; reg = <0 0x15021000 0 0xc000>; interrupts = ; }; dip_a1@15022000 { compatible = "mediatek,dip_a1"; reg = <0 0x15022000 0 0x1000>; }; dip_a2@15023000 { compatible = "mediatek,dip_a2"; reg = <0 0x15023000 0 0x1000>; }; dip_a3@15024000 { compatible = "mediatek,dip_a3"; reg = <0 0x15024000 0 0x1000>; }; dip_a4@15025000 { compatible = "mediatek,dip_a4"; reg = <0 0x15025000 0 0x1000>; }; dip_a5@15026000 { compatible = "mediatek,dip_a5"; reg = <0 0x15026000 0 0x1000>; }; dip_a6@15027000 { compatible = "mediatek,dip_a6"; reg = <0 0x15027000 0 0x1000>; }; dip_a7@15028000 { compatible = "mediatek,dip_a7"; reg = <0 0x15028000 0 0x1000>; }; dip_a8@15029000 { compatible = "mediatek,dip_a8"; reg = <0 0x15029000 0 0x1000>; }; dip_a9@1502a000 { compatible = "mediatek,dip_a9"; reg = <0 0x1502a000 0 0x1000>; }; vcp: vcp@1ec00000 { compatible = "mediatek,vcp"; vcp-support = <1>; status = "okay"; reg = <0 0x1ea00000 0 0x20000>, /* tcm */ <0 0x1ec24000 0 0x1000>, /* cfg */ <0 0x1ec30000 0 0x1000>, /* cfg core0 */ <0 0x1ec40000 0 0x1000>, /* cfg core1 */ <0 0x1ec52000 0 0x1000>, /* bus tracker dbg */ <0 0x1ec60000 0 0x40000>, /* llc dbg */ <0 0x1eca5000 0 0x4>, /* cfg_sec dbg */ <0 0x1e820000 0 0x4>, /* mmu dbg */ <0 0x1ecfb000 0 0x100>, /* mbox0 base */ <0 0x1ecfb100 0 0x4>, /* mbox0 set */ <0 0x1ecfb10c 0 0x4>, /* mbox0 clr */ <0 0x1eca5020 0 0x4>, /* mbox0 init */ <0 0x1ecfc000 0 0x100>, /* mbox1 base */ <0 0x1ecfc100 0 0x4>, /* mbox1 set */ <0 0x1ecfc10c 0 0x4>, /* mbox1 clr */ <0 0x1eca5024 0 0x4>, /* mbox1 init */ <0 0x1ecfd000 0 0x100>, /* mbox2 base */ <0 0x1ecfd100 0 0x4>, /* mbox2 set */ <0 0x1ecfd10c 0 0x4>, /* mbox2 clr */ <0 0x1eca5028 0 0x4>, /* mbox2 init */ <0 0x1ecfe000 0 0x100>, /* mbox3 base */ <0 0x1ecfe100 0 0x4>, /* mbox3 set */ <0 0x1ecfe10c 0 0x4>, /* mbox3 clr */ <0 0x1eca502c 0 0x4>, /* mbox3 init */ <0 0x1ecff000 0 0x100>, /* mbox4 base */ <0 0x1ecff100 0 0x4>, /* mbox4 set */ <0 0x1ecff10c 0 0x4>, /* mbox4 clr */ <0 0x1eca5030 0 0x4>; /* mbox4 init */ reg-names = "vcp_sram_base", "vcp_cfgreg", "vcp_cfgreg_core0", "vcp_cfgreg_core1", "vcp_bus_tracker", "vcp_l1creg", "vcp_cfgreg_sec", "vcp_cfgreg_mmu", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_init", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_init", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_init", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_init", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_init"; interrupts = , , , , , , ; interrupt-names = "wdt", "reserved", "mbox0", "mbox1", "mbox2", "mbox3", "mbox4"; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L22_VIDEO_UP_256MB1>; mediatek,smi = <&smi_mdp_subcommon0>; core-0 = "enable"; vcp-hwvoter = "disable"; vcp-sramSize = <0x00020000>; vcp-dramSize = <0x00800000>; core-nums = <1>; /* core number */ twohart = <0>; /* two hart arch */ femter-ck = <8>; /* clk table fmeter f_fmmup_ck */ mbox-count = <5>; vcp-ee-enable = <1>; /* id, mbox, send_size*/ send-table = < 0 0 18>,/* IPI_OUT_VDEC_1 */ < 2 1 2>,/* IPI_OUT_C_SLEEP_0 */ < 3 1 1>,/* IPI_OUT_TEST_0 */ <12 2 18>,/* IPI_OUT_VENC_0 */ <14 2 4>,/* IPI_OUT_VCP_MPOOL_0 */ <16 3 2>,/* IPI_OUT_C_SLEEP_1 */ <17 3 1>,/* IPI_OUT_TEST_1 */ <18 3 6>,/* IPI_OUT_LOGGER_CTRL */ <19 3 2>,/* IPI_OUT_VCPCTL_1 */ <24 4 4>;/* IPI_OUT_VCP_MPOOL_1 */ /* id, mbox, recv_size, recv_opt */ recv-table = < 1 0 18 0>,/* IPI_IN_VDEC_1 */ < 2 1 1 1>,/* IPI_OUT_C_SLEEP_0 */ < 4 1 10 0>,/* IPI_IN_VCP_ERROR_INFO_0 */ < 5 1 1 0>,/* IPI_IN_VCP_READY_0 */ < 6 1 2 0>,/* IPI_IN_VCP_RAM_DUMP_0 */ <13 2 18 0>,/* IPI_IN_VENC_0 */ <15 2 4 0>,/* IPI_IN_VCP_MPOOL_0 */ <16 3 1 1>,/* IPI_OUT_C_SLEEP_1 */ <20 3 10 0>,/* IPI_IN_VCP_ERROR_INFO_1 */ <21 3 6 0>,/* IPI_IN_LOGGER_CTRL */ <22 3 1 0>,/* IPI_IN_VCP_READY_1 */ <23 3 2 0>,/* IPI_IN_VCP_RAM_DUMP_1 */ <25 4 4 0>;/* IPI_IN_VCP_MPOOL_1 */ vcp-secure-dump = <1>; /* enable dump via secure world*/ vcp-secure-dump-size = <0x200000>; vcp-secure-dump-offset = <0x600000>; vcp-sec-dump-key = "mediatek,me_vcp_reserved"; memorydump = <0x20000>, /* l2tcm */ <0x020000>, /* l1c */ <0x003f00>, /* regdump */ <0x000200>, /* trace buffer */ <0x160000>; /* dram */ vcp-mem-tbl = <0 0x78000>, /* VDEC_MEM_ID 480KB */ <1 0x8000>, /* VENC_MEM_ID 32KB */ <2 0x180000>, /* LOGGER 1MB 512KB*/ <3 0x400>, /* VDEC_SET_PROP_MEM_ID 1KB */ <4 0x400>, /* VENC_SET_PROP_MEM_ID 1KB */ <5 0x400>, /* VDEC_VCP_LOG_INFO_ID 1KB */ <6 0x400>, /* VENC_VCP_LOG_INFO_ID 1KB */ <7 0x100000>, /* GCE_MEM_ID 256*4KB */ <9 0x0>; /* secure dump, its size is in secure_dump_size */ power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_PROC_DORMANT>; clocks = <&topckgen_clk CLK_TOP_MMUP_SEL>, <&topckgen_clk CLK_TOP_MAINPLL_D5_D2>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>; clock-names = "mmup-sel", "mmup-clk", "mmup-26m"; }; vcp_iommu_vdec { vcp-support = <2>; compatible = "mediatek,vcp-io-vdec"; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L22_VIDEO_UP_512MB1>; }; vcp_iommu_venc { vcp-support = <3>; compatible = "mediatek,vcp-io-venc"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L22_VIDEO_UP_512MB2>; }; vcp_iommu_work { vcp-support = <4>; compatible = "mediatek,vcp-io-work"; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L22_VIDEO_UP_256MB2>; }; vcp-iommu-sec { #address-cells = <2>; #size-cells = <2>; vcp-support = <7>; compatible = "mediatek,vcp-io-sec"; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L22_VIDEO_UP_512MB1>; }; vcu: vcu@16000000 { compatible = "mediatek-vcu"; mediatek,vcuid = <0>; mediatek,vcuname = "vcu"; mediatek,vcu-off = <1>; reg = <0 0x16000000 0 0x40000>, /* VDEC_BASE */ <0 0x17020000 0 0x10000>, /* VENC_BASE */ <0 0x17820000 0 0x10000>, /* VENC_C1_BASE */ <0 0x14006000 0 0x1000>, /* DISP_WDMA0_BASE */ <0 0x14106000 0 0x1000>, /* DISP_WDMA1_BASE */ <0 0x17000000 0 0x1000>; /* VENC_C0_BASE */ iommus = <&disp_iommu M4U_PORT_L4_HW_VDEC_MC_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PP_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_RD_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_WR_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PPWRAP_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_TILE_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_VLD_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_VLD2_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_AVC_MV_EXT>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; }; vcu_iommu_venc { compatible = "mediatek,vcu-io-venc"; mediatek,vcuid = <0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L7_VENC_RCPU>, <&disp_iommu M4U_PORT_L7_VENC_REC>, <&disp_iommu M4U_PORT_L7_VENC_BSDMA>, <&disp_iommu M4U_PORT_L7_VENC_SV_COMV>, <&disp_iommu M4U_PORT_L7_VENC_RD_COMV>, <&disp_iommu M4U_PORT_L7_VENC_CUR_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_CUR_CHROMA>, <&disp_iommu M4U_PORT_L7_VENC_REF_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_REF_CHROMA>, <&disp_iommu M4U_PORT_L7_JPGENC_Y_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_C_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_Q_TABLE>, <&disp_iommu M4U_PORT_L7_JPGENC_BSDMA>; }; vdec@16000000 { compatible = "mediatek,mt6835-vcodec-dec"; mediatek,platform = "platform:mt6835"; mediatek,ipm = <1>; reg = <0 0x16000000 0 0x1000>, /* VDEC_BASE */ <0 0x1602f000 0 0x1000>, /* VDEC_SYS */ <0 0x16020000 0 0x1000>, /* VDEC_VLD */ <0 0x16021000 0 0x1000>, /* VDEC_MC */ <0 0x16023000 0 0x1000>, /* VDEC_MV */ <0 0x16025000 0 0x4000>; /* VDEC_MISC */ reg-names = "VDEC_BASE", "VDEC_SYS", "VDEC_VLD", "VDEC_MC", "VDEC_MV", "VDEC_MISC"; iommus = <&disp_iommu M4U_PORT_L4_HW_VDEC_MC_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PP_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_RD_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PRED_WR_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_PPWRAP_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_TILE_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_VLD_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_VLD2_EXT>, <&disp_iommu M4U_PORT_L4_HW_VDEC_AVC_MV_EXT>; m4u-ports = , , , , , , , , , , , , ; m4u-port-names = "M4U_PORT_VDEC_MC", "M4U_PORT_VDEC_PP", "M4U_PORT_VDEC_PRED_RD", "M4U_PORT_VDEC_PRED_WR", "M4U_PORT_VDEC_PPWRAP", "M4U_PORT_VDEC_TILE", "M4U_PORT_VDEC_VLD", "M4U_PORT_VDEC_VLD2", "M4U_PORT_VDEC_AVC_MV", "M4U_PORT_VIDEO_UP_1", "M4U_PORT_VIDEO_UP_2", "M4U_PORT_VIDEO_UP_3", "M4U_PORT_VIDEO_UP_4"; mediatek,larbs = <&smi_larb4>; interrupts = ; //dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6835_POWER_DOMAIN_VDE0>; mediatek,vcu = <&vcu>; clocks = <&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN>; clock-names = "CORE_MT_CG_VDEC0"; mediatek,clock-parents = <4 3>; operating-points-v2 = <&opp_table_vdec>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_MC_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PP_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_RD_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PRED_WR_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_PPWRAP_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_TILE_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD2_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_AVC_MV_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos SLAVE_LARB(4) &mmqos SLAVE_COMMON(0)>; interconnect-names = "path_vdec_mc","path_vdec_pp", "path_vdec_pred_rd", "path_vdec_pred_wr", "path_vdec_ppwrap", "path_vdec_tile", "path_vdec_vld", "path_vdec_vld2", "path_vdec_avc_mv","path_larb4"; interconnect-num = <10>; throughput-op-rate-thresh = <120>; throughput-min = <218000000>; throughput-normal-max = <416000000>; profile-duration = <60 2000>; profile-target = <15 25 30 50 60 90 120 150 180 240 480>; max-op-rate-table = <877088845 921600 30 3686400 30 8847360 30>, /* MPEG4 */ <859189832 921600 30 3686400 30 8847360 30>, /* H.263 */ <875967048 921600 30 3686400 30 8847360 30>, /* H.264 */ <826496577 921600 30 3686400 30 8847360 30>, /* H.264 */ <1129727304 921600 30 3686400 30 8847360 30>, /* HEVC */ <892744264 921600 30 3686400 30 8847360 30>, /* H.265 */ <809062486 921600 30 3686400 30 8847360 30>; /* VP9 */ throughput-table = <877088845 0 642 642>, /* MPEG4, FHD60 416M */ <859189832 0 595 595>, /* H.263, FHD60 312M */ <875967048 0 595 595>, /* H.264 */ <826496577 0 595 595>, /* H.264 */ <1129727304 0 595 595>, /* HEVC */ <892744264 0 595 595>, /* H.265 */ <809062486 0 595 595>; /* VP9 */ bandwidth-table = <3 1089>, <2 975>, <5 0>, <5 0>, <5 0>, <5 34>, <0 0>, <0 106>, <5 0>, <6 4>; support-svp-region = <1>; }; venc@17000000 { compatible = "mediatek,mt6835-vcodec-enc"; mediatek,platform = "platform:mt6835"; mediatek,ipm = <1>; reg = <0 0x17020000 0 0x2000>, <0 0x17820000 0 0x20000>; reg-names = "VENC_SYS", "VENC_C1_SYS"; iommus = <&disp_iommu M4U_PORT_L7_VENC_RCPU>, <&disp_iommu M4U_PORT_L7_VENC_REC>, <&disp_iommu M4U_PORT_L7_VENC_BSDMA>, <&disp_iommu M4U_PORT_L7_VENC_SV_COMV>, <&disp_iommu M4U_PORT_L7_VENC_RD_COMV>, <&disp_iommu M4U_PORT_L7_VENC_CUR_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_CUR_CHROMA>, <&disp_iommu M4U_PORT_L7_VENC_REF_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_REF_CHROMA>, <&disp_iommu M4U_PORT_L7_JPGENC_Y_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_C_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_Q_TABLE>, <&disp_iommu M4U_PORT_L7_JPGENC_BSDMA>; mediatek,larbs = <&smi_larb7>; interrupts = ; //dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6835_POWER_DOMAIN_VEN0>; mediatek,vcu = <&vcu>; clocks = <&venc_gcon_clk CLK_VEN1_CKE1_VENC>; clock-names = "MT_CG_VENC0"; operating-points-v2 = <&opp_table_venc>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_RCPU) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REC) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_BSDMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_SV_COMV) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_RD_COMV) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_LUMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_CHROMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_LUMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_CHROMA) &mmqos SLAVE_COMMON(0)>, <&mmqos SLAVE_LARB(7) &mmqos SLAVE_COMMON(0)>; interconnect-names = "path_venc_rcpu", "path_venc_rec", "path_venc_bsdma", "path_venc_sv_comv", "path_venc_rd_comv", "path_venc_cur_luma", "path_venc_cur_chroma", "venc_ref_luma", "path_venc_ref_chroma", "path_larb7"; interconnect-num = <10>; throughput-op-rate-thresh = <120>; throughput-min = <250000000>; throughput-normal-max = <458000000>; throughput-config-offset = <2>; throughput-table = <875967048 3 864 864>, /* H.264 */ <875967048 4 850 850>, <875967048 5 845 845>, <1129727304 2 850 850>, /* HEVC low power*/ <1129727304 4 845 845>, <892744264 2 850 850>, /* H265*/ <892744264 4 845 845>, <1179206984 2 3500 3500>, /* HEIF */ <1179206984 3 1720 1720>, /* HEIF */ <1179206984 4 1100 1100>; config-table = <875967048 108000 3 3>, /* H.264, 720p30 */ <875967048 243000 4 4>, /* 1080p30 */ <875967048 486000 5 5>, /* 1080p60 */ <875967048 4294967295 5 5>, <1129727304 243000 2 2>, /* HEVC, 1080p30 */ <1129727304 486000 4 4>, /* 1080p60 */ <1129727304 4294967295 4 4>, <892744264 243000 2 2>, /* H265, 1080p30 */ <892744264 486000 4 4>, /* 1080p60 */ <892744264 4294967295 4 4>, <1179206984 108000 2 2>, /* HEIF, 720p30 */ <1179206984 243000 3 3>, /* 1080p30 */ <1179206984 486000 4 4>, /* 1080p60 */ <1179206984 4294967295 4 4>; bandwidth-table = <4 6>, <3 81>, <0 19>, <5 2>, <5 3>, <1 100>, <2 50>, <1 0>, <2 331>, <6 7>; support-wfd-region = <1>; }; jpgenc@17030000 { compatible = "mediatek,mtk-jpgenc"; mediatek,34bits = <1>; reg = <0 0x17030000 0 0x10000>, <0 0x17000000 0 0x1000>; /* VENC_C0_BASE */ interrupts = ; clocks = <&venc_gcon_clk CLK_VEN1_CKE2_JPGENC>; clock-names = "jpgenc"; power-domains = <&scpsys MT6835_POWER_DOMAIN_VEN0>; mediatek,larb = <&smi_larb7>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L7_JPGENC_Y_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_C_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_Q_TABLE>, <&disp_iommu M4U_PORT_L7_JPGENC_BSDMA>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_RDMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_TABLE) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA) &mmqos SLAVE_COMMON(0)>; interconnect-names = "path_jpegenc_y_rdma", "path_jpegenc_c_rmda", "path_jpegenc_q_table", "path_jpegenc_bsdma"; operating-points-v2 = <&opp_table_venc>; dvfsrc-vcore-supply = <&dvfsrc_vcore>; }; mbist@17060000 { compatible = "mediatek,mbist"; reg = <0 0x17060000 0 0x10000>; }; jpgenc@17830000 { compatible = "mediatek,jpgenc"; reg = <0 0x17830000 0 0x10000>; }; jpgdec@17840000 { compatible = "mediatek,jpgdec"; reg = <0 0x17840000 0 0x10000>; }; mbist@17860000 { compatible = "mediatek,mbist"; reg = <0 0x17860000 0 0x10000>; }; mtk_leds: mtk_leds { backlight { label = "lcd-backlight"; max-brightness = <2047>; min-brightness = <24>; max-hw-brightness = <2047>; /* prize liuyong, modify boot up backlight, 20231205, start*/ default-brightness = <1638>; /* prize liuyong, modify boot up backlight, 20231205, end*/ }; }; btif: btif@1100c000 { compatible = "mediatek,btif"; /*btif base*/ reg = <0 0x1100c000 0 0x1000>, /*btif tx dma base*/ <0 0x11300b00 0 0x80>, /*btif rx dma base*/ <0 0x11300b80 0 0x80>, /*apdma clk addr*/ <0 0x11036010 0 0x4>, /*apdma idle en addr*/ <0 0x11036a84 0 0x4>; /*btif irq, IRQS_Sync ID, btif_irq_b*/ interrupts = , /*btif tx dma irq*/ , /*btif rx dma irq*/ ; clocks = <&pericfg_ao_clk CLK_PERAOP_BTIF_BCLK>, /*btif clock*/ <&pericfg_ao_clk CLK_PERAOP_APDMA>; /*ap dma clock*/ clock-names = "btifc","apdmac"; debug-reg = <0x11036158 0x1103615c 0x11036a84 0x11036010 0x11300020 0x11300024 0x113000d0 0x11300150 0x113001d0 0x11300250 0x113002d0 0x11300350 0x113003d0 0x11300450 0x113004d0 0x11300550 0x113005d0 0x11300650 0x113006d0 0x11300750 0x113007d0 0x11300850 0x113008d0 0x11300950 0x113009d0 0x11300a50 0x11300ad0 0x11300b50 0x11300bd0 0x113000d4 0x11300154 0x113001d4 0x11300254 0x113002d4 0x11300354 0x113003d4 0x11300454 0x113004d4 0x11300554 0x113005d4 0x11300654 0x113006d4 0x11300754 0x113007d4 0x11300854 0x113008d4 0x11300098 0x11300118 0x11300198 0x11300218 0x11300298 0x11300318 0x11300398 0x11300418 0x11300498 0x11300518 0x11300598 0x11300618 0x11300698 0x11300718 0x11300798 0x11300818 0x11300898 0x1130091c 0x1130099c 0x11300a1c 0x11300a9c 0x11300b1c 0x11300b9c 0x10001c80 0x10001c8c 0x11036014 0x11036018 0x100000b0>; }; consys: consys@18002000 { compatible = "mediatek,mt6835-consys"; #thermal-sensor-cells = <0>; #address-cells = <2>; #size-cells = <2>; /*CONN_MCU_CONFIG_BASE */ reg = <0 0x18002000 0 0x1000>, /*TOP_RGU_BASE */ <0 0x1c007000 0 0x0100>, /*INFRACFG_AO_BASE */ <0 0x10001000 0 0x1000>, /*SPM_BASE */ <0 0x1c001000 0 0x1000>, /*CONN_HIF_ON_BASE */ <0 0x18007000 0 0x1000>, /*CONN_TOP_MISC_OFF_BASE */ <0 0x180b1000 0 0x1000>, /*CONN_MCU_CFG_ON_BASE */ <0 0x180a3000 0 0x1000>, /*CONN_MCU_CIRQ_BASE */ <0 0x180a5000 0 0x800>, /*CONN_TOP_MISC_ON_BASE */ <0 0x180c1000 0 0x1000>, /*CONN_HIF_PDMA_BASE */ <0 0x18004000 0 0x1000>, /* INFRASYS_COMMON AP2MD_PCCIF4_BASE */ <0 0x1024c000 0 0x40>; /*BGF_EINT */ interrupts = , /*WDT_EINT */ , /*conn2ap_sw_irq*/ ; power-domains = <&scpsys MT6835_POWER_DOMAIN_CONN>; emi-addr = <0>; emi-size = <0x800000>; emi-alignment = <0x1000000>; emi-max-addr = <0x80000000>; clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF4_AP>; clock-names = "ccif"; }; cam_qos_legacy { /* non-v4l2 legacy camera */ compatible = "mediatek,cam_qos_legacy"; operating-points-v2 = <&opp_table_cam>; dvfsrc-vcore-supply = <&dvfsrc_vcore>; l13_cam_camsv4 = ; l13_cam_camsv5 = ; l13_cam_camsv6 = ; l16_cam_imgo_r1_a = ; l16_cam_rrzo_r1_a = ; l16_cam_cqi_r1_a = ; l16_cam_bpci_r1_a = ; l16_cam_yuvo_r1_a = ; l16_cam_ufdi_r2_a = ; l16_cam_rawi_r2_a = ; l16_cam_rawi_r3_a = ; l16_cam_aao_r1_a = ; l16_cam_afo_r1_a = ; l16_cam_flko_r1_a = ; l16_cam_lceso_r1_a = ; l16_cam_crzo_r1_a = ; l16_cam_ltmso_r1_a = ; l16_cam_rsso_r1_a = ; l16_cam_aaho_r1_a = ; l16_cam_lsci_r1_a = ; l17_cam_imgo_r1_b = ; l17_cam_rrzo_r1_b = ; l17_cam_cqi_r1_b = ; l17_cam_bpci_r1_b = ; l17_cam_yuvo_r1_b = ; l17_cam_ufdi_r2_b = ; l17_cam_rawi_r2_b = ; l17_cam_rawi_r3_b = ; l17_cam_aao_r1_b = ; l17_cam_afo_r1_b = ; l17_cam_flko_r1_b = ; l17_cam_lceso_r1_b = ; l17_cam_crzo_r1_b = ; l17_cam_ltmso_r1_b = ; l17_cam_rsso_r1_b = ; l17_cam_aaho_r1_b = ; l17_cam_lsci_r1_b = ; }; cam_mem { compatible = "mediatek,cam_mem"; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; iommus = /* imgsys_config, msf_b and wpe */ <&disp_iommu M4U_PORT_L9_IMGI_D1>, <&disp_iommu M4U_PORT_L9_IMGBI_D1>, <&disp_iommu M4U_PORT_L9_DMGI_D1>, <&disp_iommu M4U_PORT_L9_UFDI_D1>, <&disp_iommu M4U_PORT_L9_LCEI_D1>, <&disp_iommu M4U_PORT_L9_SMTI_D1>, <&disp_iommu M4U_PORT_L9_SMTO_D2>, <&disp_iommu M4U_PORT_L9_SMTO_D1>, <&disp_iommu M4U_PORT_L9_CRZO_D1>, <&disp_iommu M4U_PORT_L9_IMG3O_D1>, <&disp_iommu M4U_PORT_L9_VIPI_D1>, <&disp_iommu M4U_PORT_L9_SMTI_D5>, <&disp_iommu M4U_PORT_L9_TIMGO_D1>; }; camisp_legacy: camisp_legacy@1a000000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camisp_legacy"; reg = <0 0x1a000000 0 0x10000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>; mediatek,larb = <&smi_larb13>; mediatek,platform = "mt6835"; #clock-cells = <1>; /* Camera CCF */ clocks = <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAMTG>, <&camsys_main_clk CLK_CAM_M_CAMSV1>, <&camsys_main_clk CLK_CAM_M_CAMSV2>, <&camsys_main_clk CLK_CAM_M_CAMSV3>, <&camsys_main_clk CLK_CAM_M_LARB13>, <&camsys_main_clk CLK_CAM_M_LARB14>, <&camsys_main_clk CLK_CAM_M_SENINF>, <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>, <&camsys_rawa_clk CLK_CAM_RA_LARBX>, <&camsys_rawa_clk CLK_CAM_RA_CAM>, <&camsys_rawa_clk CLK_CAM_RA_CAMTG>, <&camsys_rawb_clk CLK_CAM_RB_LARBX>, <&camsys_rawb_clk CLK_CAM_RB_CAM>, <&camsys_rawb_clk CLK_CAM_RB_CAMTG>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "CAMSYS_CAM_CGPDN", "CAMSYS_CAMTG_CGPDN", "CAMSYS_CAMSV1_CGPDN", "CAMSYS_CAMSV2_CGPDN", "CAMSYS_CAMSV3_CGPDN", "CAMSYS_LARB13_CGPDN", "CAMSYS_LARB14_CGPDN", "CAMSYS_SENINF_CGPDN", "CAMSYS_MAIN_CAM2MM_GALS_CGPDN", "CAMSYS_RAWALARB16_CGPDN", "CAMSYS_RAWACAM_CGPDN", "CAMSYS_RAWATG_CGPDN", "CAMSYS_RAWBLARB17_CGPDN", "CAMSYS_RAWBCAM_CGPDN", "CAMSYS_RAWBTG_CGPDN", "TOPCKGEN_TOP_MUX_CAMTM"; }; cam1_legacy: cam1_legacy@1a030000 { /* non-v4l2 legacy camera */ compatible = "mediatek,cam1_legacy"; reg = <0 0x1a030000 0 0x8000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBA>; mediatek,larb = <&smi_larb16>; }; cam1_inner_legacy@1a038000 { /* non-v4l2 legacy camera */ compatible = "mediatek,cam1_inner_legacy"; reg = <0 0x1a038000 0 0x8000>; }; camsys_rawa_legacy: camsys_rawa_legacy@1a04f000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsys_rawa_legacy"; reg = <0 0x1a04f000 0 0x1000>; #clock-cells = <1>; }; cam2_legacy: cam2_legacy@1a050000 { /* non-v4l2 legacy camera */ compatible = "mediatek,cam2_legacy"; reg = <0 0x1a050000 0 0x8000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBB>; mediatek,larb = <&smi_larb17>; }; cam2_inner_legacy@1a058000 { /* non-v4l2 legacy camera */ compatible = "mediatek,cam2_inner_legacy"; reg = <0 0x1a058000 0 0x8000>; }; camsys_rawb_legacy: camsys_rawb_legacy@1a06f000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsys_rawb_legacy"; reg = <0 0x1a06f000 0 0x1000>; #clock-cells = <1>; }; /* Dummy */ cam3_legacy: cam3_legacy@1a070000 { /* non-v4l2 legacy camera */ compatible = "mediatek,cam3_legacy"; reg = <0 0x1a070000 0 0x8000>; }; /* Dummy */ cam3_inner_legacy@1a078000 { /* non-v4l2 legacy camera */ compatible = "mediatek,cam3_inner_legacy"; reg = <0 0x1a078000 0 0x8000>; }; /* Dummy */ camsys_rawc_legacy: camsys_rawc_legacy@1a08f000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsys_rawc_legacy"; reg = <0 0x1a08f000 0 0x1000>; #clock-cells = <1>; }; camsv2_legacy: camsv2_legacy@1a092000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsv2_legacy"; reg = <0 0x1a092000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; mediatek,larb = <&smi_larb13>; }; camsv3_legacy: camsv3_legacy@1a093000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsv3_legacy"; reg = <0 0x1a093000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; mediatek,larb = <&smi_larb13>; }; camsv4_legacy: camsv4_legacy@1a094000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsv4_legacy"; reg = <0 0x1a094000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; mediatek,larb = <&smi_larb13>; }; camsv5_legacy: camsv5_legacy@1a095000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsv5_legacy"; reg = <0 0x1a095000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; mediatek,larb = <&smi_larb13>; }; camsv6_legacy: camsv6_legacy@1a096000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsv6_legacy"; reg = <0 0x1a096000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; mediatek,larb = <&smi_larb13>; }; camsv7_legacy: camsv7_legacy@1a097000 { /* non-v4l2 legacy camera */ compatible = "mediatek,camsv7_legacy"; reg = <0 0x1a097000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; interrupts = ; mediatek,larb = <&smi_larb13>; }; apccci_mdo1: md_power_o1 { compatible = "mediatek,md_power_o1", "syscon"; reg = <0 0x1c001000 0 0x1000>; }; watchdog: watchdog@1c007000 { compatible = "mediatek,mt6835-wdt", "mediatek,mt6589-wdt", "syscon", "simple-mfd"; reg = <0 0x1c007000 0 0x100>; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x24>; mask = <0xf>; mode-charger = ; mode-recovery = ; mode-bootloader = ; mode-dm-verity-dev-corrupt = ; mode-kpoc = ; mode-ddr-reserve = ; mode-meta = ; mode-rpmbpk = ; }; }; keypad: kp@1c00e000 { compatible = "mediatek,kp"; reg = <0 0x1c00e000 0 0x1000>; interrupts = ; mediatek,key-debounce-ms = <1024>; mediatek,hw-map-num = <72>; mediatek,hw-init-map = <114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; clocks = <&clk26m>; clock-names = "kpd"; }; prize_board_id: prize_board_id{ compatible = "prize,board-id"; board_id_sel1 = <&pio 114 0x0>; board_id_sel2 = <&pio 113 0x0>; board_id_sel3 = <&pio 112 0x0>; }; /* prize liuyong, Add SIM card slot detection, 20240103, start */ sim_slot_state: sim_slot_state{ compatible = "prize,sim-slot-state"; gpio_state = <&pio 48 0x0>; }; /* prize liuyong, Add SIM card slot detection, 20240103, end */ regulator_vibrator: regulator-vibrator { compatible = "regulator-vibrator"; label = "vibrator"; //prize liuyong, modify vib voltage config min-volt = <3000000>; max-volt = <3000000>; }; dvfsrc: dvfsrc@1c00f000 { compatible = "mediatek,mt6835-dvfsrc"; reg = <0 0x1c00f000 0 0x1000>, <0 0x1c001000 0 0x1000>; reg-names = "dvfsrc", "spm"; #interconnect-cells = <1>; dvfsrc_vcore: dvfsrc-vcore { regulator-name = "dvfsrc-vcore"; regulator-min-microvolt = <550000>; regulator-max-microvolt = <725000>; regulator-always-on; }; dvfsrc_vscp: dvfsrc-vscp { regulator-name = "dvfsrc-vscp"; regulator-min-microvolt = <550000>; regulator-max-microvolt = <725000>; regulator-always-on; }; dvfsrc_freq_opp6: opp6 { opp-peak-KBps = <0>; }; dvfsrc_freq_opp5: opp5 { opp-peak-KBps = <2500000>; }; dvfsrc_freq_opp4: opp4 { opp-peak-KBps = <3800000>; }; dvfsrc_freq_opp3: opp3 { opp-peak-KBps = <5100000>; }; dvfsrc_freq_opp2: opp2 { opp-peak-KBps = <5900000>; }; dvfsrc_freq_opp1: opp1 { opp-peak-KBps = <7600000>; }; dvfsrc_freq_opp0: opp0 { opp-peak-KBps = <10200000>; }; dvfsrc_helper: dvfsrc-helper { compatible = "mediatek,dvfsrc-helper"; rc-vcore-supply = <&dvfsrc_vcore>; rc-vscp-supply = <&dvfsrc_vscp>; interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_HRT_DBGIF &dvfsrc MT6873_SLAVE_HRT_DDR_EMI>; interconnect-names = "icc-bw", "icc-perf-bw", "icc-hrt-bw"; required-opps = <&dvfsrc_freq_opp0>, <&dvfsrc_freq_opp1>, <&dvfsrc_freq_opp2>, <&dvfsrc_freq_opp3>, <&dvfsrc_freq_opp4>, <&dvfsrc_freq_opp5>; }; dvfsrc-met { rc-vcore-supply = <&dvfsrc_vcore>; interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_HRT_DBGIF &dvfsrc MT6873_SLAVE_HRT_DDR_EMI>; interconnect-names = "icc-bw", "icc-hrt-bw"; compatible = "mediatek,dvfsrc-met"; }; }; scp_clk_ctrl: scp-clk-ctrl@1c721000 { compatible = "mediatek,scp-clk-ctrl", "syscon"; reg = <0 0x1c721000 0 0x1000>; /* scp clk */ }; scp_dvfs: scp-dvfs { compatible = "mediatek,scp-dvfs"; clocks = <&vlp_cksys_clk CLK_VLP_CK_SCP_SEL>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>, <&topckgen_clk CLK_TOP_UNIVPLL_D4>, /* 624M */ <&topckgen_clk CLK_TOP_MMPLL_D4>, <&topckgen_clk CLK_TOP_MAINPLL_D3>, /* 728M */ <&topckgen_clk CLK_TOP_UNIVPLL_D6>, <&topckgen_clk CLK_TOP_MAINPLL_D6>, <&topckgen_clk CLK_TOP_MAINPLL_D4>, <&topckgen_clk CLK_TOP_MAINPLL_D7>, <&topckgen_clk CLK_TOP_OSC_D10>; clock-names = "clk_mux", "clk_pll_0", "clk_pll_1", /* 624M */ "clk_pll_2", "clk_pll_3", /* 728M */ "clk_pll_4", "clk_pll_5", "clk_pll_6", "clk_pll_7", "clk_pll_8"; scp-cores = <1>; vlpck-support; vlpck-bypass-phase1; pmic-sshub-support; no-pmic-rg-access; dvfsrc-vscp-supply = <&dvfsrc_vscp>; dvfs-opp = /* vcore vsram dvfsrc_vb_opp spm_vcore freq mux resource */ < 550000 750000 0x00 0x001 120 0 0x0>, < 550000 750000 0x00 0x001 180 0 0x0>, < 550000 750000 0x00 0x001 360 0 0x0>, < 600000 750000 0x01 0x102 400 0 0x0>, < 650000 750000 0x02 0x204 624 1 0x1>, < 650000 750000 0x02 0x204 728 3 0x3>; do-ulposc-cali; fmeter-clksys = <&vlp_cksys_clk>; ulposc-clksys = <&vlp_cksys_clk>; scp-clk-ctrl = <&scp_clk_ctrl>; scp-clk-hw-ver = "v1"; ulposc-cali-ver = "v2"; ulposc-cali-num = <2>; ulposc-cali-target = <360 400>; ulposc-cali-config = /* con0 con1 con2 */ <0x0056a940 0x2900 0x41>, <0x005ea940 0x2900 0x41>; clk-dbg-ver = "v2"; ccf-fmeter-support; secure-access = "enable"; scp-dvfs-flag = "enable"; /* turn on/off SCP DVFS */ }; mtk_ssc: mtk_ssc@1c01f000 { compatible = "mediatek,ssc"; ssc_disable = <0x1>; }; gce: gce@1e980000 { compatible = "mediatek,mt6835-gce"; reg = <0 0x1e980000 0 0x4000>; interrupts = ; #mbox-cells = <3>; #gce-event-cells = <1>; #gce-subsys-cells = <2>; default-tokens = /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 ; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; mediatek,smi = <&smi_mdp_subcommon0>; prebuilt-enable; cmdq-log-perf-off; mboxes = <&gce 13 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "gce","gce-timer"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_LARB21_GCE_DM>; dma-mask-bit = <34>; skip-poll-sleep; }; gce_sec: gce_mbox_sec@1e980000 { compatible = "mediatek,mailbox-gce-sec"; reg = <0 0x1e980000 0 0x4000>; #mbox-cells = <3>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; mboxes = <&gce 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>; clock-names = "gce"; }; gce_m: gce@1e990000 { compatible = "mediatek,mt6835-gce"; reg = <0 0x1e990000 0 0x4000>; interrupts = ; #mbox-cells = <3>; #gce-event-cells = <1>; #gce-subsys-cells = <2>; default-tokens = /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 ; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; mediatek,smi = <&smi_mdp_subcommon0>; prebuilt-enable; cmdq-log-perf-off; mboxes = <&gce_m 13 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "gce","gce-timer"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_LARB21_GCE_MM>; dma-mask-bit = <34>; skip-poll-sleep; }; gce_m_sec: gce_mbox_m_sec@1e990000 { compatible = "mediatek,mailbox-gce-sec"; reg = <0 0x1e990000 0 0x4000>; #mbox-cells = <3>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; mboxes = <&gce_m 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_M>; clock-names = "gce"; }; cmdq-test { compatible = "mediatek,cmdq-test"; mediatek,gce = <&gce_m>; mmsys_config = <&dispsys_config>; mediatek,gce-subsys = <99>, ; mboxes = <&gce_m 14 0 CMDQ_THR_PRIO_1>, <&gce 14 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>, <&gce_m_sec 9 0 CMDQ_THR_PRIO_1>; token-user0 = /bits/ 16 ; token-gpr-set4 = /bits/ 16 ; }; mdpsys_config: mdpsys-config@1f000000 { compatible = "mediatek,mdpsys_config"; reg = <0 0x1f000000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; clocks = <&mdpsys_config_clk CLK_MDP_FMM_IMG_DL_ASYNC0>, <&mdpsys_config_clk CLK_MDP_FMM_IMG_DL_ASYNC1>, <&mdpsys_config_clk CLK_MDP_FIMG_IMG_DL_ASYNC0>, <&mdpsys_config_clk CLK_MDP_FIMG_IMG_DL_ASYNC1>, <&mdpsys_config_clk CLK_MDP_APB_BUS>; clock-names = "MDP_IMG_DL_ASYNC0", "MDP_IMG_DL_ASYNC1", "MDP_IMG_DL_RELAY0_ASYNC0", "MDP_IMG_DL_RELAY1_ASYNC1", "MDP_APB_BUS"; iommus = <&disp_iommu M4U_PORT_L2_MDP_RDMA0>, <&disp_iommu M4U_PORT_L2_MDP_WROT0>, <&disp_iommu M4U_PORT_L2_MDP_WROT2>; dma-mask-bit = <35>; }; mdp: mdp@1f000000 { compatible = "mediatek,mdp"; reg = <0 0x1f000000 0 0x1000>; thread-count = <24>; mboxes = <&gce_m_sec 10 0 CMDQ_THR_PRIO_1>, <&gce_m 16 0 CMDQ_THR_PRIO_1>, <&gce_m 17 0 CMDQ_THR_PRIO_1>, <&gce_m 18 0 CMDQ_THR_PRIO_1>, <&gce_m 19 0 CMDQ_THR_PRIO_1>; mmsys-config = <&mdpsys_config>; mm-mutex = <&mdp_mutex0>; mdp-rdma0 = <&mdp_rdma0>; mdp-rsz0 = <&mdp_rsz0>; mdp-rsz2 = <&mdp_rsz2>; mdp-wrot0 = <&mdp_wrot0>; mdp-wrot2 = <&mdp_wrot2>; mdp-tdshp0 = <&mdp_tdshp0>; mdp-aal0 = <&mdp_aal0>; mdp-hdr0 = <&mdp_hdr0>; mediatek,larb = <&smi_larb2>; dip-cq-thread0-frame-done = ; dip-cq-thread1-frame-done = ; dip-cq-thread2-frame-done = ; dip-cq-thread3-frame-done = ; dip-cq-thread4-frame-done = ; dip-cq-thread5-frame-done = ; dip-cq-thread6-frame-done = ; dip-cq-thread7-frame-done = ; dip-cq-thread8-frame-done = ; dip-cq-thread9-frame-done = ; dip-cq-thread10-frame-done = ; dip-cq-thread11-frame-done = ; dip-cq-thread12-frame-done = ; dip-cq-thread13-frame-done = ; dip-cq-thread14-frame-done = ; dip-cq-thread15-frame-done = ; dip-cq-thread16-frame-done = ; dip-cq-thread17-frame-done = ; dip-cq-thread18-frame-done = ; mdp-rdma0-sof = ; mdp-wrot0-sof = ; mdp-tdshp-sof = ; mdp-wrot2-write-frame-done = ; mdp-wrot0-write-frame-done = ; mdp-tdshp-frame-done = ; mdp-rsz2-frame-done = ; mdp-rsz0-frame-done = ; mdp-rdma0-frame-done = ; mdp-hdr0-frame-done = ; mdp-aal-frame-done = ; stream-done-0 = ; stream-done-1 = ; stream-done-2 = ; stream-done-3 = ; stream-done-4 = ; stream-done-5 = ; stream-done-6 = ; stream-done-7 = ; stream-done-8 = ; stream-done-9 = ; stream-done-10 = ; stream-done-11 = ; stream-done-12 = ; stream-done-13 = ; stream-done-14 = ; stream-done-15 = ; mdp-wrot2-rst-done = ; mdp-wrot0-rst-done = ; mdp-rdma0-rst-done = ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMGI_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMGBI_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_DMGI_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_UFDI_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_LCEI_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_SMTI_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_SMTO_D2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_SMTO_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_CRZO_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_IMG3O_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_VIPI_D1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_SMTI_D5) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L9_TIMGO_D1) &mmqos SLAVE_COMMON(0)>; interconnect-names = "mdp_rdma0", "mdp_wrot0", "mdp_wrot2", "l9_img_imgi_d1", "l9_img_imgbi_d1", "l9_img_dmgi_d1", "l9_img_depi_d1", "l9_img_ice_d1", "l9_img_smti_d1", "l9_img_smto_d2", "l9_img_smto_d1", "l9_img_crzo_d1", "l9_img_img3o_d1", "l9_img_vipi_d1", "l9_img_smti_d5", "l9_img_timgo_d1"; operating-points-v2 = <&opp_table_mdp0>, <&opp_table_img>; mdp-opp = <&opp_table_mdp0>; isp-opp = <&opp_table_img>; mdp-dvfsrc-vcore-supply = <&dvfsrc_vcore>; isp-dvfsrc-vcore-supply = <&dvfsrc_vcore>; dre30-hist-sram-start = /bits/ 16 <1536>; pq-rb-thread-id = /bits/ 16 <19>; pq-rb-event-lock = /bits/ 16 ; pq-rb-event-unlock = /bits/ 16 ; }; mdp_mutex0: mdp-mutex0@1f001000 { compatible = "mediatek,mdp_mutex0"; reg = <0 0x1f001000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_MUTEX0>; clock-names = "MDP_MUTEX0"; }; mdp_rdma0: mdp-rdma0@1f003000 { compatible = "mediatek,mdp_rdma0"; reg = <0 0x1f003000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RDMA0>; clock-names = "MDP_RDMA0"; }; mdp_hdr0: mdp-hdr0@1f005000 { compatible = "mediatek,mdp_hdr0", "mediatek,mdp-tuning-mdp_hdr0"; reg = <0 0x1f005000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_HDR0>; clock-names = "MDP_HDR0"; }; mdp_aal0: mdp-aal0@1f007000 { compatible = "mediatek,mdp_aal0", "mediatek,mdp-tuning-mdp_aal0"; reg = <0 0x1f007000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_AAL0>; clock-names = "MDP_AAL0"; }; mdp_rsz0: mdp-rsz0@1f009000 { compatible = "mediatek,mdp_rsz0"; reg = <0 0x1f009000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RSZ0>; clock-names = "MDP_RSZ0"; }; mdp_tdshp0: mdp-tdshp0@1f00b000 { compatible = "mediatek,mdp_tdshp0", "mediatek,mdp-tuning-mdp_tdshp0"; reg = <0 0x1f00b000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_TDSHP0>; clock-names = "MDP_TDSHP0"; }; mdp_wrot0: mdp-wrot0@1f00f000 { compatible = "mediatek,mdp_wrot0"; reg = <0 0x1f00f000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_WROT0>; clock-names = "MDP_WROT0"; }; mdp_rsz2: mdp-rsz2@1f013000 { compatible = "mediatek,mdp_rsz2"; reg = <0 0x1f013000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RSZ2>; clock-names = "MDP_RSZ2"; }; mdp_wrot2: mdp-wrot2@1f015000 { compatible = "mediatek,mdp_wrot2"; reg = <0 0x1f015000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_WROT2>; clock-names = "MDP_WROT2"; }; usb_meta: usb-meta { compatible = "mediatek,usb-meta"; udc = <&ssusb>; }; ssusb: usb0@11201000 { compatible = "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; interrupts = ; phy-cells = <1>; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; clocks = <&pericfg_ao_clk CLK_PERAOP_USB_SYS>, <&pericfg_ao_clk CLK_PERAOP_USB_XHCI>, <&pericfg_ao_clk CLK_PERAOP_USB_FRMCNT>; clock-names = "sys_ck", "host_ck", "frmcnt_ck"; #address-cells = <2>; #size-cells = <2>; ranges; dr_mode = "otg"; maximum-speed = "high-speed"; mediatek,force-vbus; mediatek,clk-mgr; mediatek,usb3-drd; mediatek,hw-req-ctrl; mediatek,noise-still-tr; mediatek,u2-ip; usb-role-switch; cdp-block; mediatek,syscon-wakeup = <&pericfg_ao_clk 0x200 104>; wakeup-source; port { mtu3_drd_switch: endpoint@0 { remote-endpoint = <&usb_role>; }; }; usb_host: xhci0@11200000 { compatible = "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x1000>; reg-names = "mac"; interrupts = ; clocks = <&clk26m>; clock-names = "sys_ck"; status = "okay"; }; }; u3phy: usb-phy0@11e40000 { compatible = "mediatek,generic-tphy-v2"; #address-cells = <2>; #size-cells = <2>; ranges; u2port0: usb2-phy0@11e40000 { reg = <0 0x11e40000 0 0x700>; #phy-cells = <1>; usb2jtag = <&vlpcfg_bus 2>; /* pri liu yong modify usb eye, 20240816, start */ mediatek,eye-vrt = <6>; mediatek,eye-term = <6>; mediatek,rev4 = <1>; mediatek,rev6 = <2>; mediatek,discth = <0xf>; mediatek,rx-sqth = <5>; mediatek,eye-vrt-host = <6>; mediatek,eye-term-host = <4>; mediatek,rev6-host = <3>; /* pri liu yong modify usb eye, 20240816, start */ nvmem-cells = <&u2_phy_data>; nvmem-cell-names = "intr"; nvmem-cell-masks = <0x1f>; }; u3port0: usb3-phy0@11e40700 { reg = <0 0x11e40700 0 0x900>, <0 0x11203e00 0 0x0100>; #phy-cells = <1>; nvmem-cells = <&u3_phy_data>, <&u3_phy_data>, <&u3_phy_data>; nvmem-cell-names = "intr", "rx_imp", "tx_imp"; nvmem-cell-masks = <0x3f0000 0x1f00 0x1f>; }; }; u3fpgaphy: usb-phy { compatible = "mediatek,fpga-u3phy"; mediatek,ippc = <0x11203e00>; #address-cells = <2>; #size-cells = <2>; fpga_i2c_physical_base = <0x11ed1000>; status = "disabled"; u3fpgaport0: usb-phy@0 { chip-id= <0xa60931a>; port = <0>; pclk_phase = <23>; #phy-cells = <1>; }; }; usb_boost: usb-boost-manager { compatible = "mediatek,usb-boost", "mediatek,mt6835-usb_boost"; interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "icc-bw"; required-opps = <&dvfsrc_freq_opp0>; usb-audio; small-core = <1250000>; }; lvts: lvts@10315000 { compatible = "mediatek,mt6835-lvts"; #thermal-sensor-cells = <1>; reg = <0 0x10315000 0 0x1000>, /* AP domain */ <0 0x10316000 0 0x1000>; /* MCU domain */ interrupts = , /* AP domain */ ; /* MCU domain */ clocks = <&infracfg_ao_clk CLK_IFRAO_THERM>; clock-names = "lvts_clk"; resets = <&infracfg_rst 0>, /* AP domain */ <&infracfg_rst 1>; /* MCU domain */ nvmem-cells = <&lvts_e_data1 &lvts_e_data2>; nvmem-cell-names = "e_data1","e_data2"; }; ufs_ao_cfg: ufs_ao_cfg@112b8000 { compatible = "mediatek,ufs_ao_cfg", "syscon", "simple-mfd"; reg = <0 0x112b8000 0 0x1000>; ufsaocfg_rst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < /* ufs unipro reset */ 0x48 1 0x4c 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: unipro */ >; }; }; ufs_pdn_cfg: ufs_pdn_cfg@112bb000 { compatible = "mediatek,ufs_pdn_cfg", "syscon", "simple-mfd"; reg = <0 0x112bb000 0 0x1000>; ufspdncfg_rst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < /* ufs crypto/ufshci reset */ 0x48 2 0x4c 2 0 0 /* 2: ufs-crypto */ (ASSERT_SET | DEASSERT_SET | STATUS_NONE) 0x48 1 0x4c 1 0 0 /* 1: ufshci */ (ASSERT_SET | DEASSERT_SET | STATUS_NONE) >; }; }; ufshci: ufshci@112b0000 { compatible = "mediatek,mt8183-ufshci"; reg = <0 0x112b0000 0 0x2300>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>, <&topckgen_clk CLK_TOP_U_SEL>; clock-names = "aes_ufsfde_ck", "ufs_ck"; freq-table-hz = <0 0>, <0 0>; power-domains = <&scpsys MT6835_POWER_DOMAIN_UFS0_DORMANT>; resets = <&ufsaocfg_rst 0>, <&ufspdncfg_rst 0>, <&ufspdncfg_rst 1>; reset-names = "unipro_rst", "crypto_rst", "hci_rst"; bootmode = <&chosen>; mediatek,ufs-qos; }; smart_pa: smart_pa { }; afe: mt6835-afe-pcm@11050000 { compatible = "mediatek,mt6835-sound"; reg = <0 0x11050000 0 0x2000>; interrupts = ; topckgen = <&topckgen_clk>; apmixedsys = <&apmixedsys_clk>; infracfg = <&infracfg_ao_clk>; pericfg = <&pericfg_ao_clk>; power-domains = <&scpsys MT6835_POWER_DOMAIN_AUDIO>; clocks = <&afe_clk CLK_AFE_AFE>, <&afe_clk CLK_AFE_DAC>, <&afe_clk CLK_AFE_DAC_PREDIS>, <&afe_clk CLK_AFE_ADC>, <&afe_clk CLK_AFE_22M>, <&afe_clk CLK_AFE_24M>, <&afe_clk CLK_AFE_APLL_TUNER>, <&afe_clk CLK_AFE_APLL2_TUNER>, <&afe_clk CLK_AFE_TML>, <&afe_clk CLK_AFE_NLE>, <&afe_clk CLK_AFE_GENERAL3_ASRC>, <&afe_clk CLK_AFE_CONNSYS_I2S_ASRC>, <&afe_clk CLK_AFE_GENERAL1_ASRC>, <&afe_clk CLK_AFE_GENERAL2_ASRC>, <&afe_clk CLK_AFE_DAC_HIRES>, <&afe_clk CLK_AFE_ADC_HIRES>, <&afe_clk CLK_AFE_ADC_HIRES_TML>, <&afe_clk CLK_AFE_I2S1_BCLK>, <&afe_clk CLK_AFE_I2S2_BCLK>, <&afe_clk CLK_AFE_I2S3_BCLK>, <&afe_clk CLK_AFE_I2S4_BCLK>, <&afe_clk CLK_AFE_I2S5_BCLK>, <&apmixedsys_clk CLK_APMIXED_APLL1>, <&apmixedsys_clk CLK_APMIXED_APLL2>, <&topckgen_clk CLK_TOP_AUDIO_SEL>, <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>, <&topckgen_clk CLK_TOP_MAINPLL_D4_D4>, <&topckgen_clk CLK_TOP_AUD_1_SEL>, <&topckgen_clk CLK_TOP_APLL1>, <&topckgen_clk CLK_TOP_AUD_2_SEL>, <&topckgen_clk CLK_TOP_APLL2>, <&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>, <&topckgen_clk CLK_TOP_APLL1_D4>, <&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>, <&topckgen_clk CLK_TOP_APLL2_D4>, <&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S3_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV0>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV1>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV2>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV3>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV4>, <&topckgen_clk CLK_TOP_APLL12_CK_DIVB>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV5>, <&topckgen_clk CLK_TOP_AUDIO_H_SEL>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>, <&pericfg_ao_clk CLK_PERAO_AUDIO_SLV_CKP>, <&pericfg_ao_clk CLK_PERAO_AUDIO_MST_CKP>, <&pericfg_ao_clk CLK_PERAO_INTBUS_CKP>; clock-names = "aud_afe_clk", "aud_dac_clk", "aud_dac_predis_clk", "aud_adc_clk", "aud_apll22m_clk", "aud_apll24m_clk", "aud_apll1_tuner_clk", "aud_apll2_tuner_clk", "aud_tml_clk", "aud_nle", "aud_general3_asrc", "aud_connsys_i2s_asrc", "aud_general1_asrc", "aud_general2_asrc", "aud_dac_hires_clk", "aud_adc_hires_clk", "aud_adc_hires_tml", "aud_i2s1_bclk", "aud_i2s2_bclk", "aud_i2s3_bclk", "aud_i2s4_bclk", "aud_i2s5_bclk", "aud_clk_apmixed_apll1", "aud_clk_apmixed_apll2", "top_mux_audio", "top_mux_audio_int", "top_mainpll_d4_d4", "top_mux_aud_1", "top_apll1_ck", "top_mux_aud_2", "top_apll2_ck", "top_mux_aud_eng1", "top_apll1_d4", "top_mux_aud_eng2", "top_apll2_d4", "top_i2s0_m_sel", "top_i2s1_m_sel", "top_i2s2_m_sel", "top_i2s3_m_sel", "top_i2s4_m_sel", "top_i2s5_m_sel", "top_apll12_div0", "top_apll12_div1", "top_apll12_div2", "top_apll12_div3", "top_apll12_div4", "top_apll12_divb", "top_apll12_div5", "top_mux_audio_h", "top_clk26m_clk", "aud_slv_ck_peri", "aud_mst_ck_peri", "aud_intbus_ck_peri"; pinctrl-names = "aud_clk_mosi_off", "aud_clk_mosi_on", "aud_dat_mosi_off", "aud_dat_mosi_on", "aud_dat_miso0_off", "aud_dat_miso0_on", "aud_dat_miso1_off", "aud_dat_miso1_on", "aud_gpio_i2s0_off", "aud_gpio_i2s0_on", "aud_gpio_i2s3_off", "aud_gpio_i2s3_on", "vow_dat_miso_off", "vow_dat_miso_on", "vow_clk_miso_off", "vow_clk_miso_on"; pinctrl-0 = <&aud_clk_mosi_off>; pinctrl-1 = <&aud_clk_mosi_on>; pinctrl-2 = <&aud_dat_mosi_off>; pinctrl-3 = <&aud_dat_mosi_on>; pinctrl-4 = <&aud_dat_miso0_off>; pinctrl-5 = <&aud_dat_miso0_on>; pinctrl-6 = <&aud_dat_miso1_off>; pinctrl-7 = <&aud_dat_miso1_on>; pinctrl-8 = <&aud_gpio_i2s0_off>; pinctrl-9 = <&aud_gpio_i2s0_on>; pinctrl-10 = <&aud_gpio_i2s3_off>; pinctrl-11 = <&aud_gpio_i2s3_on>; pinctrl-12 = <&vow_dat_miso_off>; pinctrl-13 = <&vow_dat_miso_on>; pinctrl-14 = <&vow_clk_miso_off>; pinctrl-15 = <&vow_clk_miso_on>; }; audio_sram@11052000 { compatible = "mediatek,audio_sram"; reg = <0 0x11052000 0 0xd000>; prefer_mode = <0>; mode_size = <0x9c00 0xd000>; block_size = <0x1000>; }; btcvsd_snd: mtk-btcvsd-snd@18050000 { compatible = "mediatek,mtk-btcvsd-snd"; reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/ <0 0x18080000 0 0x10000>; /*SRAM_BANK2*/ interrupts = ; mediatek,infracfg = <&infracfg_ao_clk>; /*INFRA MISC, conn_bt_cvsd_mask*/ /*cvsd_mcu_read, write, packet_indicator*/ mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>; disable_write_silence = <1>; }; snd_scp_ultra: snd-scp-ultra { compatible = "mediatek,snd-scp-ultra"; scp-ultra-dl-memif-id = <0x7>; scp-ultra-ul-memif-id = <0xf>; }; scp_audio_mbox: scp_audio_mbox { compatible = "mediatek,scp_audio_mbox"; status = "okay"; reg = <0 0x1c7ff000 0 0x100>, /* Re-use scp hw mbox4 */ <0 0x1c7ff100 0 0x4>, <0 0x1c7ff10c 0 0x4>; reg-names = "mbox0_base", "mbox0_set", "mbox0_clr"; interrupts = ; interrupt-names = "mbox0"; }; snd_scp_audio: snd_scp_audio { compatible = "mediatek,snd_scp_audio"; /* feature : $enable $dl_mem $ul_mem $ref_mem $size */ scp-spk-process-enable = <0x0 0x4 0x10 0x15>; status = "okay"; }; sound: sound { compatible = "mediatek,mt6835-mt6377-sound"; /* mediatek,headset-codec = <&mt6368_accdet>; */ mediatek,platform = <&afe>; mediatek,scp-audio = <&snd_scp_audio>; }; wifi: wifi@18000000 { compatible = "mediatek,wifi"; reg = <0 0x18000000 0 0x100000>; interrupts = ; emi-addr = <0>; emi-size = <0x600000>; emi-alignment = <0x1000000>; emi-max-addr = <0xc0000000>; }; srclken_rc: srclken-rc@1c00d000 { compatible = "mediatek,srclken-rc"; reg = <0 0x1c00d000 0 0x100>, <0 0x1c00d100 0 0x700>; mediatek,subsys-ctl = "suspend", "md1", "md2", "md3", "rf", "ufs", "gps", "bt", "wf", "mcu", "spm", "nfc", "coant", "rsv"; suspend-ctl = "XO_BBCK1"; md1-ctl = "XO_RFCK2A"; gps-ctl = "XO_RFCK1A"; mcu-ctl = "XO_BBCK2"; nfc-ctl = "XO_BBCK4"; ufs-ctl = "XO_BBCK3"; mediatek,srclken-rc-broadcast; mediatek,enable; }; }; spmtwam: spmtwam@1c001000 { compatible = "mediatek,spmtwam"; reg = <0 0x1c001000 0 0x1000>; interrupts = ; spm_twam_con = <0xf80>; spm_twam_window_len = <0xf84>; spm_twam_idle_sel = <0xf88>; spm_irq_mask = <0xb4>; spm_irq_sta = <0x128>; spm_twam_last_sta0 = <0xf8c>; spm_twam_last_sta1 = <0xf90>; spm_twam_last_sta2 = <0xf94>; spm_twam_last_sta3 = <0xf98>; }; lk_charger: lk_charger { compatible = "mediatek,lk_charger"; enable_anime; /* enable_pe_plus; */ enable_pd20_reset; power_path_support; max_charger_voltage = <6500000>; fast_charge_voltage = <3100000>; /* charging current */ usb_charger_current = <500000>; ac_charger_current = <2050000>; ac_charger_input_current = <2000000>; non_std_ac_charger_current = <500000>; charging_host_charger_current = <1500000>; ta_ac_charger_current = <3000000>; pd_charger_current = <500000>; /* battery temperature protection */ temp_t4_threshold = <50>; temp_t3_threshold = <45>; temp_t1_threshold = <0>; /* enable check vsys voltage */ enable_check_vsys; }; pe: pe { compatible = "mediatek,charger,pe"; ta_12v_support; ta_9v_support; pe_ichg_level_threshold = <1000000>; /* uA */ ta_start_battery_soc = <0>; ta_stop_battery_soc = <85>; min_charger_voltage = <4600000>; ta_ac_12v_input_current = <3200000>; ta_ac_9v_input_current = <3200000>; ta_ac_7v_input_current = <3200000>; pe_charger_current = <3000000>; vbat_threshold = <4150>; }; pe2: pe2 { compatible = "mediatek,charger,pe2"; /* PE 2.0 */ pe20_ichg_level_threshold = <1000000>; /* uA */ ta_start_battery_soc = <0>; ta_stop_battery_soc = <85>; min_charger_voltage = <4600000>; /* cable measurement impedance */ cable_imp_threshold = <699>; vbat_cable_imp_threshold = <3900000>; /* uV */ /* single charger */ sc_input_current = <3200000>; sc_charger_current = <3000000>; /* dual charger in series*/ dcs_input_current = <3200000>; dcs_chg1_charger_current = <1500000>; dcs_chg2_charger_current = <1500000>; dual_polling_ieoc = <450000>; slave_mivr_diff = <100000>; vbat_threshold = <4150>; }; pdc: pdc { compatible = "mediatek,charger,pd"; min-charger-voltage = <4600000>; pd-vbus-low-bound = <5000000>; pd-vbus-upper-bound = <5000000>; vsys-watt = <5000000>; ibus-err = <14>; pd-stop-battery-soc = <80>; /* single charger */ sc-input-current = <3200000>; sc-charger-current = <3000000>; /* dual charger in series*/ dcs-input-current = <3200000>; dcs-chg1-charger-current = <1500000>; dcs-chg2-charger-current = <1500000>; /* dual charger */ dual-polling-ieoc = <450000>; slave-mivr-diff = <100000>; vbat-threshold = <4150>; /* rcable */ enable-inductor-protect = <1>; }; pe45: pe45 { compatible = "mediatek,charger,pe45"; min-charger-voltage = <4600000>; pe45-stop-battery-soc = <80>; high-temp-to-leave-pe45 = <46>; high-temp-to-enter-pe45 = <39>; low-temp-to-leave-pe45 = <10>; low-temp-to-enter-pe45 = <16>; ibus-err = <14>; /* PE 4.5 cable impedance (mohm) */ pe45-r-cable-1a-lower = <500>; pe45-r-cable-2a-lower = <351>; pe45-r-cable-3a-lower = <240>; pe45-r-cable-level = <200 300 400 500 500>; pe45-r-cable-voltage = <5000 5500 6000 6500 7000>; pe45-r-cable-current-limit = <3000 3000 3000 2500 2200>; /* single charger */ sc-input-current = <3200000>; sc-charger-current = <3000000>; /* dual charger in series*/ dcs-input-current = <3200000>; dcs-chg1-charger-current = <1500000>; dcs-chg2-charger-current = <1500000>; dual-polling-ieoc = <450000>; slave-mivr-diff = <100000>; vbat-threshold = <4150>; }; pe5: pe5 { compatible = "mediatek,charger,pe5"; polling_interval = <10000>; ta_cv_ss_repeat_tmin = <25>; vbat_cv = <4350>; start_soc_min = <0>; start_soc_max = <80>; start_vbat_max = <4300>; idvchg_term = <500>; idvchg_step = <50>; ita_level = <3000 2500 2000 1500>; rcable_level = <250 300 375 500>; ita_level_dual = <5000 3700 3400 3000>; rcable_level_dual = <230 350 450 550>; idvchg_ss_init = <1000>; idvchg_ss_step = <250>; idvchg_ss_step1 = <100>; idvchg_ss_step2 = <50>; idvchg_ss_step1_vbat = <4000>; idvchg_ss_step2_vbat = <4200>; ta_blanking = <400>; swchg_aicr = <0>; swchg_ichg = <1200>; swchg_aicr_ss_init = <400>; swchg_aicr_ss_step = <200>; swchg_off_vbat = <4250>; force_ta_cv_vbat = <4250>; chg_time_max = <5400>; tta_level_def = <0 0 0 0 25 50 60 70 80>; tta_curlmt = <0 0 0 0 0 300 600 900 (-1)>; tta_recovery_area = <3>; tbat_level_def = <0 0 0 5 25 40 43 46 50>; tbat_curlmt = <(-1) (-1) (-1) 300 0 600 900 1050 (-1)>; tbat_recovery_area = <3>; tdvchg_level_def = <0 0 0 5 25 55 60 65 70>; tdvchg_curlmt = <(-1) (-1) (-1) 300 0 300 600 900 (-1)>; tdvchg_recovery_area = <3>; tswchg_level_def = <0 0 0 5 25 65 70 75 80>; tswchg_curlmt = <(-1) (-1) (-1) 200 0 200 300 400 (-1)>; tswchg_recovery_area = <3>; ifod_threshold = <200>; rsw_min = <20>; ircmp_rbat = <40>; ircmp_vclamp = <0>; vta_cap_min = <6800>; vta_cap_max = <11000>; ita_cap_min = <1000>; support_ta = "pca_ta_pps", "pd_adapter"; allow_not_check_ta_status; vbat_threshold = <4150>; }; charger: charger { compatible = "mediatek,charger"; charger = <&upm6910_chg>; bootmode = <&chosen>; algorithm_name = "Basic"; charger_configuration= <0>; /* common */ battery_cv = <4464000>; max_charger_voltage = <6500000>; min_charger_voltage = <4500000>; /* sw jeita */ enable-vbat-mon = <0>; enable_sw_jeita; jeita_temp_above_t4_cv = <4150000>; jeita_temp_t3_to_t4_cv = <4150000>; jeita_temp_t2_to_t3_cv = <4464000>; jeita_temp_t1_to_t2_cv = <4464000>; jeita_temp_t0_to_t1_cv = <4464000>; jeita_temp_below_t0_cv = <4150000>; temp_t4_thres = <55>; temp_t4_thres_minus_x_degree = <51>; temp_t3_thres = <45>; temp_t3_thres_minus_x_degree = <42>; temp_t2_thres = <15>; temp_t2_thres_plus_x_degree = <16>; temp_t1_thres = <5>; temp_t1_thres_plus_x_degree = <6>; temp_t0_thres = <0>; temp_t0_thres_plus_x_degree = <0>; temp_neg_10_thres = <0>; /* battery temperature protection */ enable_min_charge_temp; min_charge_temp = <0>; min_charge_temp_plus_x_degree = <6>; max_charge_temp = <55>; max_charge_temp_minus_x_degree = <51>; /*prize LiuYong, modify for charging current config, 20231017 -start*/ jeita_temp_t0_to_t1_input_current = <2000000>; jeita_temp_t0_to_t1_charging_current = <2000000>; jeita_temp_t1_to_t2_input_current = <2000000>; jeita_temp_t1_to_t2_charging_current = <2100000>; jeita_temp_t2_to_t3_input_current = <2000000>; jeita_temp_t2_to_t3_charging_current = <2100000>; jeita_temp_t3_to_t4_input_current = <2000000>; jeita_temp_t3_to_t4_charging_current = <1500000>; temp_screen_on_input_current = <2000000>; temp_screen_on_charging_current = <1800000>; /*prize LiuYong, modify for charging current config, 20231017 -end*/ /* charging current */ usb_charger_current = <500000>; ac_charger_current = <2200000>; ac_charger_input_current = <2000000>; charging_host_charger_current = <1500000>; /* dynamic mivr */ enable_dynamic_mivr; /*prize LiuYong, modify for charging config, 20240725 -start*/ min_charger_voltage_1 = <4400000>; min_charger_voltage_2 = <4200000>; /*prize LiuYong, modify for charging config, 20240725 -end*/ max_dmivr_charger_current = <1800000>; /* fast charging algo support indicator */ enable_fast_charging_indicator; }; logstore: logstore { enabled = <1>; pmic-register = <0xa0d>; }; /* ATF logger */ atf_logger: atf_logger { compatible = "mediatek,tfa_debug"; }; cache-parity { compatible = "mediatek,mt6873-cache-parity"; ecc-irq-support = <1>; arm_dsu_ecc_hwirq = <32>; interrupts = , , , , , , , , ; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , , , ; clock-frequency = <13000000>; }; hwrng: hwrng { compatible = "arm,sec-rng"; methods = "smc"; method-fid = /bits/ 16 <0x26a>; quality = /bits/ 16 <900>; }; scp: scp@1c700000 { compatible = "mediatek,scp"; status = "okay"; reg = <0 0x1c400000 0 0x80000>, /* tcm */ <0 0x1c724000 0 0x1000>, /* cfg */ <0 0x1c721000 0 0x1000>, /* clk*/ <0 0x1c730000 0 0x1000>, /* cfg core0 */ <0 0x1c740000 0 0x1000>, /* cfg core1 */ <0 0x1c752000 0 0x1000>, /* bus tracker */ <0 0x1c760000 0 0x40000>, /* llc */ <0 0x1c7a5000 0 0x4>, /* cfg_sec */ <0 0x1c7fb000 0 0x100>, /* mbox0 base */ <0 0x1c7fb100 0 0x4>, /* mbox0 set */ <0 0x1c7fb10c 0 0x4>, /* mbox0 clr */ <0 0x1c7a5020 0 0x4>, /* mbox0 init */ <0 0x1c7fc000 0 0x100>, /* mbox1 base */ <0 0x1c7fc100 0 0x4>, /* mbox1 set */ <0 0x1c7fc10c 0 0x4>, /* mbox1 clr */ <0 0x1c7a5024 0 0x4>, /* mbox1 init */ <0 0x1c7fd000 0 0x100>, /* mbox2 base */ <0 0x1c7fd100 0 0x4>, /* mbox2 set */ <0 0x1c7fd10c 0 0x4>, /* mbox2 clr */ <0 0x1c7a5028 0 0x4>, /* mbox2 init */ <0 0x1c7fe000 0 0x100>, /* mbox3 base */ <0 0x1c7fe100 0 0x4>, /* mbox3 set */ <0 0x1c7fe10c 0 0x4>, /* mbox3 clr */ <0 0x1c7a502c 0 0x4>, /* mbox3 init */ <0 0x1c7ff000 0 0x100>, /* mbox4 base */ <0 0x1c7ff100 0 0x4>, /* mbox4 set */ <0 0x1c7ff10c 0 0x4>, /* mbox4 clr */ <0 0x1c7a5030 0 0x4>; /* mbox4 init */ reg-names = "scp_sram_base", "scp_cfgreg", "scp_clkreg", "scp_cfgreg_core0", "scp_cfgreg_core1", "scp_bus_tracker", "scp_l1creg", "scp_cfgreg_sec", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_init", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_init", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_init", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_init", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_init"; interrupts = , , , , , , ; interrupt-names = "ipc0", "ipc1", "mbox0", "mbox1", "mbox2", "mbox3", "mbox4"; core_0 = "enable"; scp_hwvoter = "disable"; scp_sramSize = <0x80000>; core_nums = <1>; /* core number */ twohart = <1>; /* two hart arch */ mbox_count = <4>; /* id, mbox, send_size*/ send_table = < 0 0 9>,/* IPI_OUT_AUDIO_VOW_1 */ <14 0 1>,/* IPI_OUT_DVFS_SET_FREQ_1 */ <15 0 2>,/* IPI_OUT_C_SLEEP_1 */ <16 0 1>,/* IPI_OUT_TEST_1 */ //<24 0 6>,/* IPI_OUT_SCP_MPOOL_1 */ <17 1 6>,/* IPI_OUT_LOGGER_CTRL */ <18 1 2>,/* IPI_OUT_SCPCTL_1 */ < 4 2 1>,/* IPI_OUT_DVFS_SET_FREQ_0 */ < 5 2 2>,/* IPI_OUT_C_SLEEP_0 */ < 6 2 1>,/* IPI_OUT_TEST_0 */ <41 2 2>,/* IPI_OUT_DEBUG_CMD */ //<11 2 6>,/* IPI_OUT_SCP_MPOOL_0 */ <33 2 16>,/* IPI_OUT_SCP_CONNSYS */ < 3 3 4>,/* IPI_OUT_APCCCI_0 */ <26 3 9>,/* IPI_OUT_AUDIO_ULTRA_SND_0 */ <35 3 2>,/* IPI_OUT_C_SCP_HWVOTER_DEBUG */ <29 3 16>,/* IPI_OUT_SENSOR_CTRL */ <31 3 7>;/* IPI_OUT_SENSOR_NOTIFY */ /* id, mbox, recv_size, recv_opt */ recv_table = < 1 0 2 0>,/* IPI_IN_AUDIO_VOW_ACK_1 */ < 2 0 26 0>,/* IPI_IN_AUDIO_VOW_1 */ <36 0 1 0>,/* IPI_IN_AUDIO_ACDDET_1 */ <15 0 1 1>,/* IPI_OUT_C_SLEEP_1 */ //<25 0 6 0>,/* IPI_IN_SCP_MPOOL_1 */ <20 1 10 0>,/* IPI_IN_SCP_ERROR_INFO_1 */ <21 1 6 0>,/* IPI_IN_LOGGER_CTRL */ <22 1 1 0>,/* IPI_IN_SCP_READY_1 */ < 5 2 1 1>,/* IPI_OUT_C_SLEEP_0 */ < 8 2 10 0>,/* IPI_IN_SCP_ERROR_INFO_0 */ //<12 2 6 0>,/* IPI_IN_SCP_MPOOL_0 */ <34 2 16 0>,/* IPI_IN_SCP_CONNSYS */ <42 2 8 0>,/* IPI_IN_RV_SPK_PROCESS */ < 7 3 2 0>,/* IPI_IN_APCCCI_0 */ <28 3 5 0>,/* IPI_IN_AUDIO_ULTRA_SND_0 */ <27 3 2 0>,/* IPI_IN_AUDIO_ULTRA_SND_ACK_0 */ <35 3 4 1>,/* IPI_OUT_C_SCP_HWVOTER_DEBUG */ <30 3 2 0>,/* IPI_IN_SENSOR_CTRL */ <32 3 7 0>;/* IPI_IN_SENSOR_NOTIFY */ //legacy_table =<11>, /* out_id_0 IPI_OUT_SCP_MPOOL_0 */ // <24>, /* out_id_1 IPI_OUT_SCP_MPOOL_1 */ // <12>, /* in_id_0 IPI_IN_SCP_MPOOL_0 */ // <12>, /* in_id_1 IPI_IN_SCP_MPOOL_0 */ // <6>, /* out_size */ // <6>; /* in_size */ /* feature, frequecy, coreid */ scp_feature_tbl = < 0 5 0>, /* vow */ < 1 0 0>, /* sensor */ < 2 26 0>, /* flp */ < 3 0 0>, /* rtos */ < 4 200 0>, /* speaker */ < 5 0 0>, /* vcore */ < 6 135 0>, /* barge in */ < 7 10 0>, /* vow dump */ < 8 80 0>, /* vow vendor M */ < 9 43 0>, /* vow vendor A */ <10 22 0>, /* vow vendor G */ <11 20 0>, /* vow dual mic */ <12 100 0>, /* vow dual mic barge in */ <13 200 0>, /* ultrasound */ <14 100 0>, /* spk process */ <15 728 0>; /* voice call */ scp-dram-region = "enable"; /* enable scp dram region manage */ scp-protect = "enable"; secure_dump = "enable"; /* enable dump via secure world */ secure_dump_size = <0x480000>; scp_mem_key = "mediatek,reserve-memory-scp_share"; /* feature ID, size, alignment */ scp-mem-tbl = <0 0x0 0x0>, /* secure dump */ /* its size is in secure_dump_size */ < 1 0xca700 0x0>, /* vow */ < 2 0x100000 0x0>, /* sensor main*/ < 3 0x180000 0x0>, /* logger */ < 4 0x200000 0x0>, /* audio 2M*/ < 5 0xa000 0x0>, /* vow bargein */ < 7 0x19000 0x0>, /* ultrasound*/ < 8 0x10000 0x0>, /* sensor supper*/ < 9 0x1000 0x0>, /* sensor list */ <10 0x2000 0x0>, /* sensor debug */ <11 0x100 0x0>, /* sensor custom writer */ <12 0x100 0x0>, /* sensor custom reader */ <14 0x19000 0x0>; /* 13: AOV, 14: rv spk */ memorydump = <0x80000>, /* l2tcm */ <0x03c000>, /* l1c */ <0x003c00>, /* regdump */ <0x000400>, /* trace buffer */ <0x300000>; /* dram */ scp-resource-dump = "enable"; /* enable dump scp related resource */ /* regulator */ scp-supply-num = <1>; /* total number of scp related regulator */ /* dump register */ /* cell means register info (address,size), not total reg num */ scp-resource-reg-dump-cell = <2>; scp-resource-reg-dump = <0x1c013008 0x4>, <0x1c001908 0x4>, <0x1c001818 0x4>; }; clk_ao: clk_ao { compatible = "simple-bus"; }; clkitg: clkitg { compatible = "simple-bus"; }; disable_unused: disable_unused { compatible = "simple-bus"; }; clocks { clk_null: clk_null { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; clk32k: clk32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; clk26m: clk26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clk13m: clk13m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <13000000>; }; ulposc: ulposc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <260000000>; }; }; topckgen_clk: syscon@10000000 { compatible = "mediatek,mt6835-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; }; fpsgo: fpsgo { compatible = "mediatek,fpsgo"; interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "fpsgo-perf-bw"; required-opps = <&dvfsrc_freq_opp0>; gcc_enable = <1>; fbt_cpu_mask = <255 192 63 63 192 63>; sbe_resceue_enable = <1>; }; infracfg_ao_clk: syscon@10001000 { compatible = "mediatek,mt6835-infracfg_ao", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; }; apmixedsys_clk: syscon@1000c000 { compatible = "mediatek,mt6835-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; #clock-cells = <1>; }; nemi_reg_clk: syscon@10219000 { compatible = "mediatek,mt6835-nemi_reg", "syscon"; reg = <0 0x10219000 0 0x1000>; #clock-cells = <1>; }; emi_bus_clk: syscon@10270000 { compatible = "mediatek,mt6835-emi_bus", "syscon"; reg = <0 0x10270000 0 0x1000>; }; pericfg_ao_clk: syscon@11036000 { compatible = "mediatek,mt6835-pericfg_ao", "syscon"; reg = <0 0x11036000 0 0x1000>; #clock-cells = <1>; }; afe_clk: syscon@11050000 { compatible = "mediatek,mt6835-afe", "syscon"; reg = <0 0x11050000 0 0x1000>; #clock-cells = <1>; }; imp_iic_wrap_c_clk: syscon@11282000 { compatible = "mediatek,mt6835-imp_iic_wrap_c", "syscon"; reg = <0 0x11282000 0 0x1000>; #clock-cells = <1>; }; imp_iic_wrap_ws_clk: syscon@11b22000 { compatible = "mediatek,mt6835-imp_iic_wrap_ws", "syscon"; reg = <0 0x11b22000 0 0x1000>; #clock-cells = <1>; }; imp_iic_wrap_s_clk: syscon@11db4000 { compatible = "mediatek,mt6835-imp_iic_wrap_s", "syscon"; reg = <0 0x11db4000 0 0x1000>; #clock-cells = <1>; }; imp_iic_wrap_en_clk: syscon@11ed4000 { compatible = "mediatek,mt6835-imp_iic_wrap_en", "syscon"; reg = <0 0x11ed4000 0 0x1000>; #clock-cells = <1>; }; mfg_top_config_clk: syscon@13fbf000 { compatible = "mediatek,mt6835-mfg", "syscon"; reg = <0 0x13fbf000 0 0x1000>; #clock-cells = <1>; }; dispsys_config_clk: syscon@14000000 { compatible = "mediatek,mt6835-dispsys_config", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; imgsys1_clk: syscon@15020000 { compatible = "mediatek,mt6835-imgsys1", "syscon"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; vdec_gcon_base_clk: syscon@1602f000 { compatible = "mediatek,mt6835-vdec_gcon_base", "syscon"; reg = <0 0x1602f000 0 0x1000>; #clock-cells = <1>; }; venc_gcon_clk: syscon@17000000 { compatible = "mediatek,mt6835-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; }; scpsys: power-controller@1c001000 { compatible = "mediatek,mt6835-scpsys", "syscon"; reg = <0 0x1c001000 0 0x1000>; #power-domain-cells = <1>; clocks = <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_DISP0_SEL>, <&topckgen_clk CLK_TOP_MDP0_SEL>, <&topckgen_clk CLK_TOP_MMINFRA_SEL>, <&topckgen_clk CLK_TOP_MMUP_SEL>, <&topckgen_clk CLK_TOP_IMG1_SEL>, <&topckgen_clk CLK_TOP_IPE_SEL>, <&topckgen_clk CLK_TOP_VDEC_SEL>, <&topckgen_clk CLK_TOP_VENC_SEL>, <&camsys_main_clk CLK_CAM_M_LARB13>, <&camsys_main_clk CLK_CAM_M_LARB14>, <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>, <&dispsys_config_clk CLK_MM_SMI_IOMMU>, <&mdpsys_config_clk CLK_MDP_SMI0>, <&imgsys1_clk CLK_IMGSYS1_LARB9>, <&imgsys1_clk CLK_IMGSYS1_GALS>, <&ipesys_clk CLK_IPE_SMI_SUBCOM>, <&ipesys_clk CLK_IPE_GALS>, <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>, <&camsys_rawa_clk CLK_CAM_RA_LARBX>, <&camsys_rawb_clk CLK_CAM_RB_LARBX>, <&pericfg_ao_clk CLK_PERAO_AUDIO_SLV_CKP>, <&pericfg_ao_clk CLK_PERAO_AUDIO_MST_CKP>, <&pericfg_ao_clk CLK_PERAO_INTBUS_CKP>; clock-names = "audio", "cam", "disp", "mdp", "mm_infra", "mmup", "dip1", "ipe", "vde", "ven", "cam-0", "cam-1", "cam_lp-0", "disp-0", "mdp_lp-0", "dip1-0", "dip1-1", "ipe-0", "ipe-1", "vde-0", "cam_suba-0", "cam_subb-0", "audio-0", "audio-1", "audio-2"; infracfg = <&infracfg_ao_clk>; emi_bus = <&emi_bus_clk>; vlpcfg = <&vlpcfg_bus>; cam_sub1_bus = <&cam_sub1_bus_clk>; cam_sub0_bus = <&cam_sub0_bus_clk>; }; vlpcfg_bus: syscon@1c00c000 { compatible = "mediatek,mt6835-vlpcfg_bus", "syscon"; reg = <0 0x1c00c000 0 0x1000>; }; vlp_cksys_clk: syscon@1c013000 { compatible = "mediatek,mt6835-vlp_cksys", "syscon"; reg = <0 0x1c013000 0 0x1000>; #clock-cells = <1>; }; camsys_main_clk: syscon@1a000000 { compatible = "mediatek,mt6835-camsys_main", "syscon"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; cam_sub1_bus_clk: syscon@1a00c000 { compatible = "mediatek,mt6835-cam_sub1_bus", "syscon"; reg = <0 0x1a00c000 0 0x1000>; }; cam_sub0_bus_clk: syscon@1a00d000 { compatible = "mediatek,mt6835-cam_sub0_bus", "syscon"; reg = <0 0x1a00d000 0 0x1000>; }; camsys_rawa_clk: syscon@1a04f000 { compatible = "mediatek,mt6835-camsys_rawa", "syscon"; reg = <0 0x1a04f000 0 0x1000>; #clock-cells = <1>; }; camsys_rawb_clk: syscon@1a06f000 { compatible = "mediatek,mt6835-camsys_rawb", "syscon"; reg = <0 0x1a06f000 0 0x1000>; #clock-cells = <1>; }; ipesys_clk: syscon@1b000000 { compatible = "mediatek,mt6835-ipesys", "syscon"; reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; aie@1b001000 { compatible = "mediatek,mt6835-aie", "mediatek,aie-hw2.0"; reg = <0 0x1b001000 0 0x1000>; interrupts = ; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_IPE>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; clocks = <&ipesys_clk CLK_IPE_FD>, <&ipesys_clk CLK_IPE_LARB20>; clock-names = "aie", "FDVT_CLK_IPE_LARB20"; mboxes = <&gce_m 20 0 CMDQ_THR_PRIO_1>, <&gce_m_sec 11 0 CMDQ_THR_PRIO_1>; iommus = <&disp_iommu M4U_PORT_L20_FDVT_RDA>, <&disp_iommu M4U_PORT_L20_FDVT_RDB>, <&disp_iommu M4U_PORT_L20_FDVT_WRA>, <&disp_iommu M4U_PORT_L20_FDVT_WRB>; fdvt_frame_done = ; mediatek,larb = <&smi_larb20>; }; sramrc_apb_clk: syscon@1c01f000 { compatible = "mediatek,mt6835-sramrc_apb", "syscon"; reg = <0 0x1c01f000 0 0x1000>; #clock-cells = <1>; }; scp_iic_clk: syscon@1c7b7000 { compatible = "mediatek,mt6835-scp_iic", "syscon"; reg = <0 0x1c7b7000 0 0x1000>; #clock-cells = <1>; }; mminfra_config_clk: syscon@1e800000 { compatible = "mediatek,mt6835-mminfra_config", "syscon"; reg = <0 0x1e800000 0 0x1000>; #clock-cells = <1>; }; mdpsys_config_clk: syscon@1f000000 { compatible = "mediatek,mt6835-mdpsys", "syscon"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; }; touch_panel0: touch-panel0 { compatible = "mediatek,touch-panel"; }; opp_table_disp0: opp-table-disp0 { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <218000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <725000>; }; }; opp_table_mminfra: opp-table-mminfra { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <218000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <725000>; }; }; opp_table_mdp0: opp-table-mdp0 { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <229000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <344000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <436000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <594000000>; opp-microvolt = <725000>; }; }; opp_table_venc: opp-table-venc { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <250000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <364000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <459000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <725000>; }; }; opp_table_vdec: opp-table-vdec { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <218000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <725000>; }; }; opp_table_cam: opp-table-cam { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <286000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <393000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <725000>; }; }; opp_table_img: opp-table-img { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <229000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <344000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <458000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <725000>; }; }; opp_table_ipe: opp-table-ipe { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <229000000>; opp-microvolt = <550000>; }; opp-1 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <725000>; }; }; disp-sec { compatible = "mediatek,disp-sec"; sw-sync-token-tzmp-disp-wait = ; sw-sync-token-tzmp-disp-set = ; mboxes = <&gce_sec 8 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_4>; }; mmdvfs-debug { compatible = "mediatek,mmdvfs-debug"; dvfsrc-vcore-supply = <&dvfsrc_vcore>; force-step0 = <0>; release-step0 = <1>; }; mmdvfs: mmdvfs { compatible = "mediatek,mmdvfs"; operating-points-v2 = <&opp_table_disp0>; mediatek,support-mux = "disp0", "mminfra", "mdp0", "venc", "vdec", "cam", "img", "ipe"; mediatek,mux-disp0 = "TOP_MAINPLL_D5_D2", "TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6", "TOP_MAINPLL_D4"; mediatek,mux-mminfra = "TOP_MAINPLL_D5_D2", "TOP_MAINPLL_D7", "TOP_UNIVPLL_D6", "TOP_MAINPLL_D4"; mediatek,mux-mdp0 = "TOP_MMPLL_D6_D2", "TOP_MMPLL_D4_D2", "TOP_MAINPLL_D5", "TOP_TVDPLL"; mediatek,mux-venc = "TOP_UNIVPLL_D5_D2", "TOP_MAINPLL_D6", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4"; mediatek,mux-vdec = "TOP_MAINPLL_D5_D2", "TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6", "TOP_MAINPLL_D4"; mediatek,mux-cam = "TOP_IMGPLL", "TOP_MMPLL_D7", "TOP_MAINPLL_D4", "TOP_UNIVPLL_D4"; mediatek,mux-img = "TOP_MMPLL_D6_D2", "TOP_MMPLL_D4_D2", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4"; mediatek,mux-ipe = "TOP_MMPLL_D6_D2", "TOP_UNIVPLL_D4_D2", "TOP_UNIVPLL_D6", "TOP_MAINPLL_D4"; dvfsrc-vcore-supply = <&dvfsrc_vcore>; clocks = <&topckgen_clk CLK_TOP_DISP0_SEL>, /* 0 */ <&topckgen_clk CLK_TOP_MMINFRA_SEL>, /* 2 */ <&topckgen_clk CLK_TOP_MDP0_SEL>, /* 3 */ <&topckgen_clk CLK_TOP_VENC_SEL>, /* 4 */ <&topckgen_clk CLK_TOP_VDEC_SEL>, /* 5 */ <&topckgen_clk CLK_TOP_CAM_SEL>, /* 6 */ <&topckgen_clk CLK_TOP_IMG1_SEL>, /* 7 */ <&topckgen_clk CLK_TOP_IPE_SEL>, /* 8 */ <&topckgen_clk CLK_TOP_MAINPLL_D5_D2>, /* 9 */ <&topckgen_clk CLK_TOP_UNIVPLL_D4_D2>, /* 10 */ <&topckgen_clk CLK_TOP_UNIVPLL_D6>, /* 11 */ <&topckgen_clk CLK_TOP_MAINPLL_D4>, /* 12 */ <&topckgen_clk CLK_TOP_MAINPLL_D7>, /* 13 */ <&topckgen_clk CLK_TOP_MMPLL_D6_D2>, /* 14 */ <&topckgen_clk CLK_TOP_MMPLL_D4_D2>, /* 15 */ <&topckgen_clk CLK_TOP_MAINPLL_D5>, /* 16 */ <&topckgen_clk CLK_TOP_TVDPLL>, /* 17 */ <&topckgen_clk CLK_TOP_UNIVPLL_D5_D2>, /* 18 */ <&topckgen_clk CLK_TOP_MAINPLL_D6>, /* 19 */ <&topckgen_clk CLK_TOP_MMPLL_D6>, /* 20 */ <&topckgen_clk CLK_TOP_UNIVPLL_D4>, /* 21 */ <&topckgen_clk CLK_TOP_IMGPLL>, /* 22 */ <&topckgen_clk CLK_TOP_MMPLL_D7>; clock-names = "disp0", /* 0 */ "mminfra", /* 2 */ "mdp0", /* 3 */ "venc", /* 4 */ "vdec", /* 5 */ "cam", /* 6 */ "img", /* 7 */ "ipe", /* 8 */ "TOP_MAINPLL_D5_D2", /* 9 */ "TOP_UNIVPLL_D4_D2", /* 10 */ "TOP_UNIVPLL_D6", /* 11 */ "TOP_MAINPLL_D4", /* 12 */ "TOP_MAINPLL_D7", /* 13 */ "TOP_MMPLL_D6_D2", /* 14 */ "TOP_MMPLL_D4_D2", /* 15 */ "TOP_MAINPLL_D5", /* 16 */ "TOP_TVDPLL", /* 17 */ "TOP_UNIVPLL_D5_D2", /* 18 */ "TOP_MAINPLL_D6", /* 19 */ "TOP_MMPLL_D6", /* 20 */ "TOP_UNIVPLL_D4", /* 21 */ "TOP_IMGPLL", /* 22 */ "TOP_MMPLL_D7"; }; mcusys_config_reg_clk: syscon@c53c000 { compatible = "mediatek,mt6835-mcusys_config_reg", "syscon"; reg = <0 0xc53c000 0 0x1000>; #clock-cells = <1>; }; smi_infra_disp_subcommon0: smi_infra_disp_subcomm0@1e807000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e807000 0 0x1000>; mediatek,common-id = <1>; init-power-on; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_infra_disp_subcommon1: smi_infra_disp_subcomm1@1e808000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e808000 0 0x1000>; mediatek,common-id = <2>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_disp_common: smi_disp_comm@1e801000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon"; reg = <0 0x1e801000 0 0x1000>; mediatek,smi = <&smi_infra_disp_subcommon0 &smi_infra_disp_subcommon1>; mediatek,common-id = <0>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; smi-common; operating-points-v2 = <&opp_table_mminfra>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_mdp_subcommon0: smi_mdp_sub_comm0@1e809000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e809000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,common-id = <3>; mediatek,dump-with-comm = <0>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_mdp_subcommon1: smi_mdp_sub_comm1@1e80a000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e80a000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,common-id = <4>; mediatek,dump-with-comm = <0>; power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_cam_mm_subcommon0: smi_cam_sub_comm0@1a00d000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1a00d000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,common-id = <7>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAM>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_cam_mm_subcommon2: smi_cam_sub_comm2@1a00c000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1a00c000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,common-id = <8>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAM>, <&camsys_main_clk CLK_CAM_M_CAM>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_img_subcommon: smi_img_subcommon@1502f000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1502f000 0 0x1000>; mediatek,smi = <&smi_mdp_subcommon1>; mediatek,common-id = <5>; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_DIP1>; clocks = <&imgsys1_clk CLK_IMGSYS1_LARB9>, <&imgsys1_clk CLK_IMGSYS1_LARB9>, <&imgsys1_clk CLK_IMGSYS1_LARB9>, <&imgsys1_clk CLK_IMGSYS1_LARB9>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_ipe_subcommon: smi_ipe_subcommon@1b00e000 { compatible = "mediatek,mt6835-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1b00e000 0 0x1000>; mediatek,smi = <&smi_mdp_subcommon1>; mediatek,common-id = <6>; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_IPE>; clocks = <&ipesys_clk CLK_IPE_SMI_SUBCOM>, <&ipesys_clk CLK_IPE_SMI_SUBCOM>, <&ipesys_clk CLK_IPE_SMI_SUBCOM>, <&ipesys_clk CLK_IPE_SMI_SUBCOM>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_pd_dip1: smi_pd_dip1 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_subcommon1>; mediatek,suspend-check-port = <0x2>; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_DIP1>; suspend-check; }; smi_pd_ipe: smi_pd_ipe { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_subcommon1>; mediatek,suspend-check-port = <0x1>; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_IPE>; suspend-check; }; smi_pd_cam_main: smi_pd_cam_main { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common>; mediatek,suspend-check-port = <0xc0>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>; suspend-check; }; smi_pd_cam_suba: smi_pd_cam_suba { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_cam_mm_subcommon2>; mediatek,suspend-check-port = <0x2>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBA>; suspend-check; }; smi_pd_cam_subb: smi_pd_cam_subb { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_cam_mm_subcommon0>; mediatek,suspend-check-port = <0x2>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBB>; suspend-check; }; smi_pd_ven0: smi_pd_ven0 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common>; mediatek,suspend-check-port = <0x10>; power-domains = <&scpsys MT6835_POWER_DOMAIN_VEN0>; suspend-check; }; smi_pd_vde0: smi_pd_vde0 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common>; mediatek,suspend-check-port = <0x20>; power-domains = <&scpsys MT6835_POWER_DOMAIN_VDE0>; suspend-check; }; smi_pd_disp: smi_pd_disp { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common &smi_mdp_subcommon0>; mediatek,suspend-check-port = <0x3 0x2>; power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>; init-power-on; suspend-check; }; smi_larb0: smi_larb0@14021000 { compatible = "mediatek,smi_larb0", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x14021000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,larb-id = <0>; init-power-on; power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>; clocks = <&dispsys_config_clk CLK_MM_SMI_IOMMU>, <&dispsys_config_clk CLK_MM_SMI_IOMMU>; clock-names = "apb", "smi"; }; smi_larb1: smi_larb1@14022000 { compatible = "mediatek,smi_larb1", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x14022000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,larb-id = <1>; power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>; clocks = <&dispsys_config_clk CLK_MM_SMI_IOMMU>, <&dispsys_config_clk CLK_MM_SMI_IOMMU>; clock-names = "apb", "smi"; }; smi-test { compatible = "mediatek,smi-testcase"; mediatek,larbs = <&smi_larb2>; }; smi_larb2: smi_larb2@1f002000 { compatible = "mediatek,smi_larb2", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x1f002000 0 0x1000>; mediatek,smi = <&smi_mdp_subcommon0>; mediatek,larb-id = <2>; power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>; clocks = <&mdpsys_config_clk CLK_MDP_SMI0>, <&mdpsys_config_clk CLK_MDP_SMI0>; clock-names = "apb", "smi"; }; smi_larb4: smi_larb4@1602e000 { compatible = "mediatek,smi_larb4", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x1602e000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,larb-id = <4>; power-domains = <&scpsys MT6835_POWER_DOMAIN_VDE0>; clocks = <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>, <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>; clock-names = "apb", "smi"; }; smi_larb7: smi_larb7@17010000 { compatible = "mediatek,smi_larb7", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x17010000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,larb-id = <7>; power-domains = <&scpsys MT6835_POWER_DOMAIN_VEN0>; clocks = <&venc_gcon_clk CLK_VEN1_CKE0_LARB>, <&venc_gcon_clk CLK_VEN1_CKE1_VENC>; clock-names = "apb", "smi"; }; smi_larb9: smi_larb9@1502e000 { compatible = "mediatek,smi_larb9", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x1502e000 0 0x1000>; mediatek,smi = <&smi_img_subcommon>; mediatek,larb-id = <9>; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_DIP1>; clocks = <&imgsys1_clk CLK_IMGSYS1_LARB9>, <&imgsys1_clk CLK_IMGSYS1_LARB9>; clock-names = "apb", "smi"; }; smi_larb13: smi_larb13@1a001000 { compatible = "mediatek,smi_larb13", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a001000 0 0x1000>; mediatek,smi = <&smi_cam_mm_subcommon0>; mediatek,larb-id = <13>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_M_LARB13>, <&camsys_main_clk CLK_CAM_M_LARB13>; clock-names = "apb", "smi"; }; smi_larb16: smi_larb16@1a00f000 { compatible = "mediatek,smi_larb16", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a00f000 0 0x1000>; mediatek,smi = <&smi_cam_mm_subcommon2>; mediatek,larb-id = <16>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBA>; clocks = <&camsys_rawa_clk CLK_CAM_RA_LARBX>, <&camsys_rawa_clk CLK_CAM_RA_CAM>; clock-names = "apb", "smi"; }; smi_larb17: smi_larb17@1a010000 { compatible = "mediatek,smi_larb17", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a010000 0 0x1000>; mediatek,smi = <&smi_cam_mm_subcommon0>; mediatek,larb-id = <17>; power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBB>; clocks = <&camsys_rawb_clk CLK_CAM_RB_LARBX>, <&camsys_rawb_clk CLK_CAM_RB_CAM>; clock-names = "apb", "smi"; }; smi_larb20: smi_larb20@1b00f000 { compatible = "mediatek,smi_larb20", "mediatek,mt6835-smi-larb", "mediatek,smi-larb"; reg = <0 0x1b00f000 0 0x1000>; mediatek,smi = <&smi_ipe_subcommon>; mediatek,larb-id = <20>; power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_IPE>; clocks = <&ipesys_clk CLK_IPE_LARB20>, <&ipesys_clk CLK_IPE_LARB20>; clock-names = "apb", "smi"; }; mmqos_wrapper { compatible = "mediatek,mt6835-mmqos-wrapper"; }; mmqos: interconnect { compatible = "mediatek,mt6835-mmqos"; #mtk-interconnect-cells = <1>; mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2 &smi_larb4 &smi_larb7 &smi_larb9 &smi_larb13 &smi_larb16 &smi_larb17 &smi_larb20>; mediatek,commons = <&smi_disp_common>; clocks = <&topckgen_clk CLK_TOP_MMINFRA_SEL>; clock-names = "mm"; interconnects = <&dvfsrc MT6873_MASTER_MMSYS &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_HRT_MMSYS &dvfsrc MT6873_SLAVE_HRT_DDR_EMI>; interconnect-names = "icc-bw", "icc-hrt-bw"; }; fusb304: fusb304 { compatible = "mediatek,fusb304"; status = "disable"; }; extcon_usb: extcon_usb { compatible = "mediatek,extcon-usb"; /*vbus-supply = <&mt6375_otg_vbus>;*/ //pri liuyong,modify 20231016 vbus-voltage = <5000000>; vbus-current = <1800000>; charger = <&upm6910_chg>; tcpc = "type_c_port0"; mediatek,bypss-typec-sink = <1>; mediatek,u2; port { usb_role: endpoint@0 { remote-endpoint = <&mtu3_drd_switch>; }; }; }; rt-pd-manager { compatible = "mediatek,rt-pd-manager"; }; typec_mux_switch: typec_mux_switch { compatible = "mediatek,typec_mux_switch"; status = "disabled"; }; mrdump_ext_rst: mrdump_ext_rst { compatible = "mediatek, mrdump_ext_rst-eint"; mode = "IRQ"; status = "okay"; }; /* prize added for swtp start */ swtp: swtp { compatible = "mediatek, swtp-eint"; }; /* prize added for swtp end */ pd_adapter: pd_adapter { compatible = "mediatek,pd_adapter"; boot_mode = <&chosen>; adapter_name = "pd_adapter"; force_cv; phys = <&u2port0 PHY_TYPE_USB2>; phy-names = "usb2-phy"; }; flashlight_core: flashlight_core { compatible = "mediatek,flashlight_core"; }; //prize add by linchong 20231018 start flashlights_aw3641e_gpio: flashlights_aw3641e_gpio { compatible = "mediatek,flashlights_aw3641e_gpio"; decouple = <1>; channel@1 { type = <0>; ct = <0>; part = <0>; }; }; //prize add by linchong 20231018 end mtk_composite_v4l2_1: mtk_composite_v4l2_1 { compatible = "mediatek,mtk_composite_v4l2_1"; }; camera_af_hw_node: camera_af_hw_node { compatible = "mediatek,camera_af_lens"; }; mtk_ctd: mtk_ctd { compatible = "mediatek,mtk_ctd"; bc12 = <&upm6910_chg>; bc12_sel = <0>; }; subpmic_pmu_eint: subpmic_pmu_eint { }; pmic_oc_debug: pmic-oc-debug { compatible = "mediatek,mt6835-oc-debug"; interrupts = <54 IRQ_TYPE_NONE>, <55 IRQ_TYPE_NONE>; interrupt-names = "LVSYS_R", "LVSYS_F"; status = "okay"; }; low_battery_throttling { compatible = "mediatek,low_battery_throttling"; hv-thd-volt = <3300>; lv1-thd-volt = <3150>; lv2-thd-volt = <3000>; }; gps: gps@18c00000 { compatible = "mediatek,gps"; emi-region = <29>; emi-offset = <0x650000>; emi-size = <0xfffff>; emi-domain-ap = <0>; emi-domain-conn = <2>; }; pbm: pbm { compatible = "mediatek,pbm"; }; mdpm: mdpm { compatible = "mediatek,mt6835-mdpm"; }; cpu_power_throttling: cpu_power_throttling { compatible = "mediatek,cpu-power-throttling"; lbat_cpu_limit = <900000 900000 1300000>; oc_cpu_limit = <900000 900000 1300000>; }; md_power_throttling: md_power_throttling { compatible = "mediatek,md-power-throttling"; lbat_md_reduce_tx = <6>; oc_md_reduce_tx = <6>; }; bp_thl: bp_thl { compatible = "mediatek,mtk-bp-thl"; soc_limit = <15>; soc_limit_ext = <20>; soc_limit_ext_release = <25>; }; swpm: swpm { compatible = "mediatek,mtk-swpm"; pmu-boundary-num = <0>; pmu-dsu-support = <0>; pmu-dsu-type = <9>; }; mtk_lpm: mtk_lpm { compatible = "mediatek,mtk-lpm"; #address-cells = <2>; #size-cells = <2>; ranges; lpm-kernel-suspend = <0>; suspend-method = "enable"; logger-enable-states = "mcusysoff", "system_mem", "system_pll", "system_bus"; irq-remain = <&edge_keypad>, <&level_btif_tx &level_btif_rx>, <&level_usb_host>; resource-ctrl = <&bus26m &infra &syspll>, <&dram_s0 &dram_s1>; constraints = <&rc_bus26m &rc_syspll &rc_dram>, <&rc_cpu_buck_ldo>; spm-cond = <&spm_cond_cg &spm_cond_pll>; cg-shift = <0>; /* cg blocking index */ pll-shift = <16>; /* pll blocking index */ power-gs = <0>; mcusys-cnt-chk = <1>; cpupm_sysram: cpupm-sysram@11b000 { compatible = "mediatek,cpupm-sysram"; reg = <0 0x0011b000 0 0x500>; }; lpm_sysram: lpm_sysram@11b500 { compatible = "mediatek,lpm-sysram"; reg = <0 0x0011b500 0 0x300>; }; mcusys_ctrl: mcusys-ctrl@c53a000 { compatible = "mediatek,mcusys-ctrl"; reg = <0 0x0c53a000 0 0x1000>; }; irq-remain-list { edge_keypad: edge_keypad { target = <&keypad>; value = <1 0 0 0x4>; }; level_btif_tx: level_btif_tx { target = <&btif>; value = <0 1 0 0>; }; level_btif_rx: level_btif_rx { target = <&btif>; value = <0 2 0 0>; }; level_usb_host: level_usb_host { target = <&usb_host>; value = <0 0 0 0>; }; }; resource-ctrl-list { bus26m: bus26m { id = <0x00000000>; value = <0>; }; infra: infra { id = <0x00000001>; value = <0>; }; syspll: syspll { id = <0x00000002>; value = <0>; }; dram_s0: dram_s0 { id = <0x00000003>; value = <0>; }; dram_s1: dram_s1 { id = <0x00000004>; value = <0>; }; }; constraint-list { rc_bus26m: rc_bus26m { rc-name = "bus26m"; id = <0x00000000>; value = <1>; cond-info = <1>; }; rc_syspll: rc_syspll { rc-name = "syspll"; id = <0x00000001>; value = <1>; cond-info = <1>; }; rc_dram: rc_dram { rc-name = "dram"; id = <0x00000002>; value = <1>; cond-info = <1>; }; rc_cpu_buck_ldo: rc_cpu_buck_ldo{ rc-name = "cpu-buck-ldo"; id = <0x00000003>; value = <1>; cond-info = <0>; }; }; spm-cond-list { spm_cond_cg: spm_cond_cg { cg-name = "MTCMOS_0", "MTCMOS_1", "INFRA_0", "INFRA_1", "PERI_0", "PERI_1", "MMSYS_0", "MMSYS_1", "MDPSYS_0"; }; spm_cond_pll: spm_cond_pll { pll-name = "TVDPLL", "UNIVPLL", "MSDCPLL", "IMGPLL", "MFGPLL", "APLL1", "APLL2"; }; }; power-gs-list { /* FIXME */ }; }; clock_buffer_ctrl: clock_buffer_ctrl { compatible = "mediatek,clock_buffer_ctrl"; mediatek,xo-buf-hwbblpm-mask = <1 0 0 0 0>, <0 0 0>, <0 0 0>, <0 0>; mediatek,xo-buf-hwbblpm-bypass = <0 0 0 0 0>, <0 0 0>, <0 0 0>, <0 0>; mediatek,xo-bbck4 = <0>; mediatek,enable; pmif = <&spmi 0>; pmif_version = <2>; srclken_rc = <&srclken_rc>; // consys = <&consys>; // pcie = <&pcie_ckm_xtal_ck>; }; speech_usip_mem: speech-usip-mem { compatible = "mediatek,speech-usip-mem"; adsp-phone-call-enh-enable = <0x5>; }; met { met_emi: met-emi { compatible = "mediatek,met_emi"; emi-num = <1>; dram-num = <2>; dramc-ver = <2>; /* 0: dram ebg, 1:emi_freq, 2: DRAMC_DCM_CTRL 3:chn_emi_low_effi */ /* 4: SLC */ met-emi-support-list = <0x1>; cen-emi-reg-base = <0x10219000 0x1021d000>; cen-emi-reg-size = <0x1000>; chn-emi-reg-base = <0x10235000 0x10245000 0x10255000 0x10265000>; chn-emi-reg-size = <0xa90>; dramc-nao-reg-base = <0x10234000 0x10244000 0x10254000 0x10264000>; dramc-nao-reg-size = <0xb6c>; dramc-ao-reg-base = <0x10230000 0x10240000 0x10250000 0x10260000>; dramc-ao-reg-size = <0x2000>; ddrphy-ao-reg-base = <0x10238000 0x10248000 0x10258000 0x10268000>; ddrphy-ao-reg-size = <0x1650>; ddrphy-ao-misc-cg-ctrl0 = <0x4ec>; ddrphy-ao-misc-cg-ctrl2 = <0x4f4>; dram-freq-default = <6400>; ddr-ratio-default = <8>; dram-type-default = <8>; apmixedsys-reg-base = <0x1000c000>; apmixedsys-reg-size = <0x410>; slc-pmu-reg-base = <0x10342000 0x10343000>; slc-pmu-reg-size = <0x1000>; }; met-res-ram { compatible = "mediatek,met_res_ram"; met-res-ram-sspm { size = <0x400000>; /* 4M: only reserve on userdebug/eng load */ start = <0x0>; /* start addr of reserved ram*/ }; met-res-ram-mcupm { size = <0x0>; /* 0M: disable ondiemet in mcupm*/ start = <0x0>; /* start addr of reserved ram*/ }; }; mcupm_rts_header: mcupm-rts-header { node-0 = "MCUPM_MET_UNIT_TEST", "test"; node-1 = "__MCUPM_MET_L3CTL__", "op_policy,ct_portion,nct_portion,cpuqos_mode,dnth0,dnth1,upth0,upth1"; }; sspm_rts_header: sspm-rts-header { node-0 = "SSPM_PTPOD", "_id,voltage"; node-1 = "SSPM_MET_UNIT_TEST", "test"; node-2 = "SSPM_QOS_BOUND_STATE", "ver,apu_num,idx,state,num,event,emibw_mon_total,", "emibw_mon_cpu,emibw_mon_gpu,emibw_mon_mm,", "emibw_mon_md,smibw_mon_gpu,smibw_mon_apu"; node-3 = "SSPM_CM_MGR_NON_WFX", "non_wfx_0,non_wfx_1,non_wfx_2,non_wfx_3,", "non_wfx_4,non_wfx_5,non_wfx_6,non_wfx_7"; node-4 = "SSPM_CM_MGR_LOADING", "ratio,cps"; node-5 = "SSPM_CM_MGR_POWER", "c_up_array_0,c_up_array_1,c_down_array_0,c_down_array_1,", "c_up_0,c_up_1,c_down_0,c_down_1,c_up,", "c_down,v_up,v_down,v2f_0,v2f_1"; node-6 = "SSPM_CM_MGR_OPP", "v_dram_opp,v_dram_opp_cur,c_opp_cur_0,c_opp_cur_1,d_times_up,", "d_times_down"; node-7 = "SSPM_CM_MGR_RATIO", "ratio_0,ratio_1,ratio_2,ratio_3,ratio_4,", "ratio_5,ratio_6,ratio_7"; node-8 = "SSPM_CM_MGR_BW", "total_bw"; node-9 = "SSPM_CM_MGR_CP_RATIO", "up0,up1,up2,up3,up4,up5,", "down0,down1,down2,down3,down4,down5"; node-10 = "SSPM_CM_MGR_VP_RATIO", "up0,up1,up2,up3,up4,up5,", "down0,down1,down2,down3,down4,down5"; node-11 = "SSPM_CM_MGR_DE_TIMES", "up0,up1,up2,up3,up4,up5,", "down0,down1,down2,down3,down4,down5,reset"; node-12 = "SSPM_CM_MGR_DSU_DVFS_PWR", "up_L,up_B,up_BB,up_DSU,cur_L,cur_B,cur_BB,cur_DSU,down_L,down_B,", "down_BB,down_DSU,total_up,total_cur,total_down"; node-13 = "SSPM_CM_MGR_DSU_DVFS_ACT_STALL_PWR", "up_L_a,up_B_a,up_BB_a,cur_L_a,cur_B_a,", "cur_BB_a,down_L_a,down_B_a,down_BB_a,", "up_L_s,up_B_s,up_BB_s,cur_L_s,cur_B_s,", "cur_BB_s,down_L_s,down_B_s,down_BB_s"; node-14 = "SSPM_CM_MGR_DSU_DVFS_STALL", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,l3_bw_val"; node-15 = "SSPM_CM_MGR_DSU_DVFS_ACTIVE", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-16 = "SSPM_CM_MGR_DSU_DVFS_OPP", "map_opp_50,map_opp_70,final,", "orig,L3_vote_opp,debounce_up,debounce_down"; node-17 = "SSPM_CM_MGR_DSU_DVFS_THRESHOLD_FLAG", "up_L,up_B,up_BB,down_L,down_B,down_BB,", "up_L_flag,up_B_flag,up_BB_flag,", "down_L_flag,down_B_flag,down_BB_flag"; node-18 = "SSPM_SWPM_CPU__CORE_ACTIVE_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-19 = "SSPM_SWPM_CPU__CORE_IDLE_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-20 = "SSPM_SWPM_CPU__CORE_OFF_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-21 = "SSPM_SWPM_CPU__CORE_STALL_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-22 = "SSPM_SWPM_CPU__CORE_PMU_L3DC", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-23 = "SSPM_SWPM_CPU__CORE_PMU_INST_SPEC", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-24 = "SSPM_SWPM_CPU__CORE_PMU_CYCLES", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-25 = "SSPM_SWPM_CPU__CORE_NON_WFX_CTR", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-26 = "SSPM_SWPM_CPU__DSU_STATE_RATIO", "active,idle,dormant,off"; node-27 = "SSPM_SWPM_CPU__DSU_L3_BW", "L3_BW"; node-28 = "SSPM_SWPM_CPU__MCUSYS_STATE_RATIO", "active,idle,off"; node-29 = "SSPM_SWPM_CPU__MCUSYS_EMI_BW", "cpu_emi_bw"; node-30 = "SSPM_SWPM_CPU__DVFS", "vproc2,vproc1,cpuL_freq,cpuB_freq,", "cpu_L_opp,cpu_B_opp,cci_volt,cci_freq,cci_opp"; node-31 = "SSPM_SWPM_CPU__LKG_POWER", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,dsu"; node-32 = "SSPM_SWPM_CPU__POWER", "cpu_L,cpu_B,dsu,mcusys"; node-33 = "SSPM_SWPM_GPU__GPU_STATE_RATIO", "active,idle,off"; node-34 = "SSPM_SWPM_GPU__LOADING", "loading"; node-35 = "SSPM_SWPM_GPU__DVFS", "vgpu,gpu_freq"; node-36 = "SSPM_SWPM_GPU__URATE", "alu_fma,alu_cvt,alu_sfu,tex,lsc,l2c,vary,tiler,rast"; node-37 = "SSPM_SWPM_GPU__THERMAL", "thermal,lkg"; node-38 = "SSPM_SWPM_GPU__COUNTER", "GPU_ACTIVE,EXEC_INSTR_FMA,EXEC_INSTR_CVT,EXEC_INSTR_SFU,", "TEX,VARY_SLOT,L20,L21,L22,L23"; node-39 = "SSPM_SWPM_GPU__POWER", "gpu"; node-40 = "SSPM_SWPM_CORE__CAM_STATE_RATIO", "RAW_A_active,RAW_B_active,RAW_C_active,idle,off"; node-41 = "SSPM_SWPM_CORE__IMG_STATE_RATIO", "P2_active,P2_idle,MFB_active,WPE_active,off"; node-42 = "SSPM_SWPM_CORE__IPE_STATE_RATIO", "FDVT_active,DVP_active,DVS_active,DV_idle,off"; node-43 = "SSPM_SWPM_CORE__MDP_STATE_RATIO", "active,off"; node-44 = "SSPM_SWPM_CORE__DISP_STATE_RATIO", "active,off"; node-45 = "SSPM_SWPM_CORE__ADSP_STATE_RATIO", "active,off"; node-46 = "SSPM_SWPM_CORE__VENC_STATE_RATIO", "active,idle,off"; node-47 = "SSPM_SWPM_CORE__VDEC_STATE_RATIO", "active,idle,off"; node-48 = "SSPM_SWPM_CORE__INFRA_STATE_RATIO", "dact,cact,idle,dcm"; node-49 = "SSPM_SWPM_CORE__VDO_CODING_TYPE", "venc,vdec"; node-50 = "SSPM_SWPM_CORE__DVFS", "vcore,ddr_freq,vcore_opp,ddr_opp"; node-51 = "SSPM_SWPM_CORE__POWER", "dramc,infra_top,aphy_vcore"; node-52 = "SSPM_SWPM_CORE__LKG_POWER", "infra_top,dramc,thermal"; node-53 = "SSPM_SWPM_DRAM__MEM_IDX", "read_bw_0,write_bw_0,", "srr_pct,ssr_pct,pdir_pct_0,", "phr_pct_0,util_0,", "trans_0,mr4,ddr_freq,ddr_opp"; node-54 = "SSPM_SWPM_DRAM__DVFS", "ddr_freq"; node-55 = "SSPM_SWPM_DRAM__POWER", "aphy_vddq_0p6v,aphy_vm_0p75v,aphy_vio_1p2v,dram_vddq_0p6v,", "dram_vdd2_1p25v,dram_vdd1_1p8v"; node-56 = "SSPM_SWPM_ME__POWER", "disp,mdp,venc,vdec"; node-57 = "SSPM_SWPM_ME__IDX", "vdec_fps,venc_fps,disp_fps,disp_resolution"; node-58 = "SSPM_SWPM_VPU__VPU0_STATE_RATIO", "active,idle,off"; node-59 = "SSPM_SWPM_VPU__VPU1_STATE_RATIO", "active,idle,off"; node-60 = "__SSPM_GPU_APU_SSC_CNT__", "APU_0_R,APU_0_W,GPU_0_R,GPU_0_W,", "APU_1_R,APU_1_W,GPU_1_R,", "GPU_1_W"; node-61 = "SSPM_SLBC_SLOT", "enable,force,done,buffer_used,f_buffer,cached_used,force_size"; node-62 = "SSPM_SLBC_REF", "venc,hifi3,sh_p2,sh_apu,mml,ainr,disp"; node-63 = "SSPM_SLBC_BW", "mm,apu,mm_est"; node-64 = "SSPM_SLBC_PMU", "hit,miss"; node-65 = "SSPM_SLBC_WAY", "venc,hifi3,sh_p2,sh_apu,mml,ainr,disp,slb,cpu,gpu,slc,left"; node-66 = "SSPM_SWPM_CPU__DSU_PMU", "dsu_cycles"; node-67 = "SSPM_SWPM_CPU__CORE_TEMP", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-68 = "SSPM_SWPM_SOC__SMAP", "i2max,imax"; node-69 = "SSPM_SWPM_CPU__PMU_TIMES", "idx_cnt,lock,idx_rechk,lock_rechk,valid,off_hint,diff_us"; node-70 = "SSPM_SWPM_CORE__MEM_RAW_IDX", "diff_us,data_rate,ddr_ratio,emi_freq,s1_ratio,", "wact_0,bcnt_0,", "dcm_ctrl_0,", "stb_0_0,stb_0_1,stb_1_0,stb_1_1,", "pd_0_0,pd_0_1,pd_1_0,pd_1_1"; node-71 = "SSPM_SPM_RES__DDREN_REQ", "mcu,mcupm,md,scp,sspm"; node-72 = "SSPM_SPM_RES__APSRC_REQ", "mcupm,md,scp,sspm"; node-73 = "SSPM_SPM_DBG__PWR_OFF", "dsu,mcu,gpu,venc,vdec,mmsys,cam,img,mminfra"; node-74 = "SSPM_SPM_DBG__PWR_ACT", "scp,mmup"; node-75 = "SSPM_SPM_DBG__SYS_STA", "s0,s1"; node-76 = "SSPM_SWPM_DRAM__MEM_RAW_IDX", "diff_us,data_rate,ddr_ratio,emi_freq,s1_ratio,", "wact_0,bact_0,bcnt_0,tact_0,", "pgh_0,pgh_1,", "pgm_0,pgm_1,", "intb_0,intb_1,", "stb_0_0,stb_0_1,stb_1_0,stb_1_1,", "mr4_idx_0_0,mr4_idx_0_1,mr4_idx_1_0,mr4_idx_1_1"; node-77 = "SSPM_SWPM_CORE__SLC_IDX", "pmu_17,pmu_18,pmu_19,pmu_20,pmu_21,pmu_22,pmu_23,pmu_24,", "pmu_25,pmu_26,pmu_27,pmu_28,pmu_29"; node-78 = "SSPM_GPU_BM", "bw,bw_max,predict,ctx,freq,frame,job_id"; }; }; gpu_qos: gpu-qos { compatible = "mediatek,gpu_qos"; qos-sysram-support = <0>; qos-mode = <0>; qos-value = <0>; }; }; #include "mediatek/mt6685.dtsi" &mt6685_mfd { mt6685_clock_buffer: mt6685_clock_buffer { mediatek,xo-buf-support = <1 1 1 1 1> /* BBCK */, <1 1 0> /* RFCK1 */, <1 1 0> /* RFCK2 */, <0 0> /* CONCK */; mediatek,bblpm-support; mediatek,xo-voter-support; mediatek,dcxo-spmi-rw; mediatek,pmrc-en-support; clkbuf_ctl = <&clock_buffer_ctrl>; mediatek,enable; }; }; &mt6685_rtc { status = "okay"; }; &i2c5 { clock-frequency = <1000000>; upm6910_chg:upm6910_chg@6b { compatible = "upm,upm6910_charger"; reg = <0x6b>; charger_name = "primary_chg"; upm,intr_gpio_num = <3>; /* direct defined GPIO num */ upm,intr_gpio = <&pio 3 0x0>; /* GPIO */ upm,chg-en-gpio = <&pio 148 0>; upm,upm6910,usb-vreg = <4450>; upm,upm6910,usb-ichg = <2000>; /* prize liuyong, Increase the pre-charging current 180 to 480mA*/ upm,upm6910,precharge-current = <480>; upm,upm6910,termination-current = <240>; upm,upm6910,boost-voltage = <5000>; upm,upm6910,boost-current = <1200>; upm,upm6910,vac-ovp-threshold = <10500>; bootmode = <&chosen>; ssusb = <&ssusb>; /*prize liuyong, get usb state, 20231125*/ status = "okay"; phys = <&u2port0 PHY_TYPE_USB2>; phy-names = "usb2-phy"; }; usb_type_c_aw35616: usb_type_c_aw35616@60 { compatible = "awinic,usb_type_c_aw35616"; reg = <0x60>; aw35616,irq-gpio = <&pio 9 0x0>; aw35616-tcpc,name = "type_c_port0"; aw35616-tcpc,role_def = <5>; /* 1: SNK Only, 2: SRC Only, 3: DRP, 4: Try.SRC, 5: Try.SNK */ aw35616,rp_level = <0>; /* 0: Default, 1: 1.5, 2: 3.0 */ aw35616-tcpc,notifier_supply_num = <3>; /* the number of notifier supply */ aw35616_acc_support = <0>; /* 0:support, 1:No support */ aw35616_toggle_cycle = <0>; /* 0:Disable, 1:40ms, 2:80ms, 3:160ms */ status = "okay"; }; // aw35615_pd: aw35615_pd@22 { // compatible = "awinic,aw35615"; // reg = <0x22>; // awinic,int_n = <&pio 9 0>; // aw35615,snk_pdo_size = <1>; /* set sink pdo num*/ // aw35615,snk_pdo_vol = <5000>; /* set sink pdo voltage mV*/ // aw35615,snk_pdo_cur = <2000>; /* set sink pdo current mA*/ // aw35615,src_pdo_size = <1>; /* set source pdo num*/ // aw35615,src_pdo_vol = <5000>; /* set source pdo voltage mV*/ // aw35615,src_pdo_cur = <1000>; /* set source pdo current mA*/ // aw35615,snk_tog_time = <0x38>; /* set toggle sink time */ // aw35615,src_tog_time = <0x24>; /* set toggle source time */ // status = "okay"; // }; mt6375: mt6375@34 { compatible = "mediatek,mt6375"; reg = <0x34>; status = "okay"; interrupt-parent = <&pio>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; wakeup-source; mt6375_adc: adc { compatible = "mediatek,mt6375-adc"; #io-channel-cells = <1>; interrupts = ; interrupt-names = "adc_donei"; }; mt6375_chg: chg { compatible = "mediatek,mt6375-chg"; interrupts = , , , , , , , , , ; interrupt-names = "fl_pwr_rdy", "fl_detach", "fl_vbus_ov", "fl_chg_tout", "fl_wdt", "fl_bc12_dn", "fl_aicc_done", "fl_pe_done", "fl_batpro_done", "adc_vbat_mon_ov"; io-channels = <&mt6375_adc MT6375_ADC_CHGVIN>, <&mt6375_adc MT6375_ADC_VSYS>, <&mt6375_adc MT6375_ADC_VBAT>, <&mt6375_adc MT6375_ADC_IBUS>, <&mt6375_adc MT6375_ADC_IBAT>, <&mt6375_adc MT6375_ADC_TEMPJC>, <&mt6375_adc MT6375_ADC_USBDP>, <&mt6375_adc MT6375_ADC_USBDM>; chg_name = "primary_chg"; aicr = <500>; mivr = <4400>; cv = <4200>; ichg = <2000>; ieoc = <150>; wdt = <40000>; /* wdt_en; */ te_en; vbus_ov = <14500>; vrec = <100>; otg_lbp = <2800>; ircmp_r = <16700>; ircmp_v = <32>; chg_tmr = <10>; chg_tmr_en; dcdt_sel = <600>; bc12_sel = <&mtk_ctd>; boot_mode = <&chosen>; phys = <&u2port0 PHY_TYPE_USB2>; phy-names = "usb2-phy"; usb = <&ssusb>; //usb_killer_detect; mt6375_otg_vbus: otg { regulator-compatible = "mt6375,otg-vbus"; regulator-name = "usb-otg-vbus"; regulator-min-microvolt = <4850000>; regulator-max-microvolt = <5500000>; regulator-min-microamp = <500000>; regulator-max-microamp = <2400000>; }; }; mt6375_typec: tcpc { compatible = "mediatek,mt6375-tcpc"; interrupts = ; interrupt-names = "pd_evt"; /* tcpc_device's name */ tcpc,name = "type_c_port0"; /* 0: Unknown, 1: SNK, 2: SRC, 3: DRP, 4: Try.SRC, 5: Try.SNK */ tcpc,role_def = <5>; /* 0: Default, 1: 1.5, 2: 3.0 */ tcpc,rp_level = <0>; /* 0: Never, 1: Always, 2: EMarkOnly, 3: StartOnly */ tcpc,vconn_supply = <1>; /* the number of notifier supply */ tcpc,notifier_supply_num = <3>; io-channels = <&mt6375_adc MT6375_ADC_SBU1>, <&mt6375_adc MT6375_ADC_SBU2>; charger = <&mt6375_chg>; boot_mode = <&chosen>; tcpc,en_wd; tcpc,en_wd_sbu_polling; tcpc,en_wd_polling_only; tcpc,en_ctd; tcpc,en_fod; tcpc,en_typec_otp; //tcpc,en_floatgnd; wd,sbu_calib_init = <1200>; /* mV */ wd,sbu_pl_bound = <200>; /* mV */ wd,sbu_pl_lbound_c2c = <1100>; /* mV */ wd,sbu_pl_ubound_c2c = <2600>; /* mV */ wd,sbu_ph_auddev = <100>; /* mV */ wd,sbu_ph_lbound = <888>; /* mV */ wd,sbu_ph_lbound1_c2c = <2850>; /* mV */ wd,sbu_ph_ubound1_c2c = <3150>; /* mV */ wd,sbu_ph_ubound2_c2c = <3800>; /* mV */ wd,sbu_aud_ubound = <1600>; /* mV */ /* 0:16x, 1:128x, 2:512x, 3:1024x */ wd,wd0_tsleep = <1>; /* 0:400us, 1:1ms, 2:2ms, 3:4ms, 4:10ms, 5:40ms, 6:100ms, 7:400ms */ wd,wd0_tdet = <3>; /* example wd0_tsleep = 512x, wd0_tdet = 4ms, wd0 polling time = 512*4ms */ pd-data { pd,vid = <0x29cf>; pd,pid = <0x6375>; pd,source-cap-ext = <0x637529cf 0x00000000 0x00000000 0x00000000 0x00000000 0x07010000 >; pd,mfrs = "RichtekTCPC"; /* * VSAFE5V = 0, MAX_POWER = 1, CUSTOM = 2, * MAX_POWER_LV = 0x21, MAX_POWER_LVIC = 0x31 * MAX_POWER_HV = 0x41, MAX_POWER_HVIC = 0x51 */ pd,charging_policy= <0x21>; /* * Fixed 5V, 500 mA <0x00019032> * Fixed 5V, 1A <0x00019064> * Fixed 5V, 2A <0x000190c8> * Fixed 5V, 3A <0x0001912c> * Fixed 9V, 500 mA <0x0002d032> * Fixed 9V, 1A <0x0002d064> * Fixed 5V, 1.5A <0x00019096> * Fixed 9V, 2A <0x0002d0c8> * Fixed 9V, 3A <0x0002d12c> * Variable 5-9V, 1A <0x8642d064> * Variable 5-9V, 2A <0x8642d0c8> * Variable 5-9V, 3A <0x8642d12c> * PPS 3V~5.9V, 3A <0xc0761e3c> */ pd,source-pdo-size = <1>; pd,source-pdo-data = <0x00019032>; /* 5V, 500 mA */ pd,sink-pdo-size = <2>; pd,sink-pdo-data = <0x000190c8 0x000190c8> ; /* 0x0002d0c8 : 9V, 2A<0x04019032 0x04019064> */ /* * No DP, host + device * pd,id-vdo-size = <3>; * pd,id-vdo-data = <0xd00029cf 0x0 0x00010000>; * With DP * pd,id-vdo-size = <4>; * pd,id-vdo-data = * <0xec0029cf 0x0 0x00010000 0x11000001>; */ pd,id-vdo-size = <4>; pd,id-vdo-data = <0xec0029cf 0x0 0x00010000 0x11000001>; bat,nr = <1>; pd,country_nr = <0>; bat-info0 { bat,vid = <0x29cf>; bat,pid = <0x6375>; bat,mfrs = "bat1"; bat,design_cap = <3000>; }; }; dpm_caps { local_dr_power; local_dr_data; // local_ext_power; local_usb_comm; // local_usb_suspend; // local_high_cap; // local_give_back; local_no_suspend; local_vconn_supply; // attempt_discover_cable_dfp; attempt_enter_dp_mode; attempt_discover_cable; attempt_discover_id; /* 0: disable, 1: prefer_snk, 2: prefer_src */ pr_check = <0>; // pr_reject_as_source; // pr_reject_as_sink; // pr_check_gp_source; // pr_check_gp_sink; /* 0: disable, 1: prefer_ufp, 2: prefer_dfp */ dr_check = <0>; // dr_reject_as_dfp; // dr_reject_as_ufp; }; displayport { /* connection type = "both", "ufp_d", "dfp_d" */ 1st_connection = "dfp_d"; 2nd_connection = "dfp_d"; signal,dp_v13; //signal,dp_gen2; usbr20_not_used; typec,receptacle; ufp_d { //pin_assignment,mode_a; //pin_assignment,mode_b; //pin_assignment,mode_c; //pin_assignment,mode_d; //pin_assignment,mode_e; }; dfp_d { /* Only support mode C & D */ //pin_assignment,mode_a; //pin_assignment,mode_b; pin_assignment,mode_c; pin_assignment,mode_d; pin_assignment,mode_e; pin_assignment,mode_f; }; }; }; dbg { compatible = "mediatek,mt6375-dbg"; }; }; }; &i2c6 { ps5169: ps5169@28 { compatible = "parade,ps5169"; reg = <0x28>; status = "disable"; }; gate_ic: gate_ic@11 { compatible = "mediatek,gate-ic-i2c"; gate-power-gpios = <&pio 150 0>; reg = <0x11>; id = <6>; status = "okay"; }; }; &i2c7 { clock-frequency = <400000>; upm6910_slave_chg: upm6910_slave_chg@6b { compatible = "upm,upm6910_slave"; reg = <0x6b>; charger_name = "secondary_chg"; upm,intr_gpio_num = <4>; /* direct defined GPIO num */ upm,intr_gpio = <&pio 4 0x0>; /* GPIO */ upm,chg-en-gpio = <&pio 12 0>; upm,upm6910_slave,usb-vreg = <4450>; upm,upm6910_slave,usb-ichg = <2000>; upm,upm6910_slave,precharge-current = <180>; upm,upm6910_slave,termination-current = <300>; upm,upm6910_slave,boost-voltage = <5000>; upm,upm6910_slave,boost-current = <1200>; upm,upm6910_slave,vac-ovp-threshold = <10500>; status = "okay"; }; }; #include "mediatek/rt5133.dtsi" #include "mediatek/trusty.dtsi" &rt5133 { interrupts-extended = <&pio 20 0x0>; enable-gpio = <&pio 23 0x0>; }; #include "mediatek/mt6835-clkitg.dtsi" #include "mediatek/mt6835-disable-unused.dtsi" /* AUDIO GPIO standardization start */ &pio { aud_clk_mosi_off: aud_clk_mosi_off { pins_cmd0_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_clk_mosi_on: aud_clk_mosi_on { pins_cmd0_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_mosi_off: aud_dat_mosi_off { pins_cmd0_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_mosi_on: aud_dat_mosi_on { pins_cmd0_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_miso0_off: aud_dat_miso0_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_miso0_on: aud_dat_miso0_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_miso1_off: aud_dat_miso1_off { pins_cmd1_dat { pinmux = ; input-enable; bias-disable; }; }; aud_dat_miso1_on: aud_dat_miso1_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; vow_dat_miso_off: vow_dat_miso_off { pins-cmd1-dat { pinmux = ; input-enable; bias-pull-down; }; }; vow_dat_miso_on: vow_dat_miso_on { pins-cmd1-dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; vow_clk_miso_off: vow_clk_miso_off { pins-cmd1-dat { pinmux = ; input-enable; bias-pull-down; }; }; vow_clk_miso_on: vow_clk_miso_on { pins-cmd1-dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_nle_mosi_off: aud_nle_mosi_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_nle_mosi_on: aud_nle_mosi_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s0_off: aud_gpio_i2s0_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s0_on: aud_gpio_i2s0_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s3_off: aud_gpio_i2s3_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd3_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s3_on: aud_gpio_i2s3_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd3_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; }; /* AUDIO GPIO standardization end */