// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2020 MediaTek Inc. */

#include <dt-bindings/clock/mt8195-clk.h>

&seninf_top {

		seninf_csi_port_0: seninf_csi_port_0 {
			compatible = "mediatek,seninf";
			csi-port = "0";
			nvmem-cells = <&csi_efuse0>;
			nvmem-cell-names = "rg_csi";
			port {
				seninf_csi_port_0_in: endpoint {
					remote-endpoint = <&sensor0_out>;
				};
			};
		};

		seninf_csi_port_1: seninf_csi_port_1 {
			compatible = "mediatek,seninf";
			csi-port = "1";
			nvmem-cells = <&csi_efuse1>;
			nvmem-cell-names = "rg_csi";
			port {
				seninf_csi_port_1_in: endpoint {
					remote-endpoint = <&sensor1_out>;
				};
			};
		};

		seninf_csi_port_2: seninf_csi_port_2 {
			compatible = "mediatek,seninf";
			csi-port = "2";
			nvmem-cells = <&csi_efuse2>;
			nvmem-cell-names = "rg_csi";
			port {
				seninf_csi_port_2_in: endpoint {
					remote-endpoint = <&sensor2_out>;
				};
			};
		};

};

/* CAMERA GPIO standardization */
&pio {
	camera_pins_cam0_rst_0: cam0@0 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO128__FUNC_GPIO128>;
			output-low;
		};
	};
	camera_pins_cam0_rst_1: cam0@1 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO128__FUNC_GPIO128>;
			output-high;
		};
	};
	camera_pins_cam1_rst_0: cam1@0 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
			output-low;
		};
	};
	camera_pins_cam1_rst_1: cam1@1 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
			output-high;
		};
	};
	camera_pins_cam2_rst_0: cam2@0 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO134__FUNC_GPIO134>;
			output-low;
		};
	};
	camera_pins_cam2_rst_1: cam2@1 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO134__FUNC_GPIO134>;
			output-high;
		};
	};
	camera_pins_cam0_vcamd_0: cam0@vcam0 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO60__FUNC_GPIO60>;
			output-low;
		};
	};
	camera_pins_cam0_vcamd_1: cam0@vcam1 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO60__FUNC_GPIO60>;
			output-high;
		};
	};
	camera_pins_cam1_vcamd_0: cam1@vcam0 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO60__FUNC_GPIO60>;
			output-low;
		};
	};
	camera_pins_cam1_vcamd_1: cam1@vcam1 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO60__FUNC_GPIO60>;
			output-high;
		};
	};
	camera_pins_cam2_vcamd_0: cam2@vcam0 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO59__FUNC_GPIO59>;
			output-low;
		};
	};
	camera_pins_cam2_vcamd_1: cam2@vcam1 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO59__FUNC_GPIO59>;
			output-high;
		};
	};
	camera_pins_cam2_vcama_0: cam2@vcam2 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO68__FUNC_GPIO68>;
			output-low;
		};
	};
	camera_pins_cam2_vcama_1: cam2@vcam3 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO68__FUNC_GPIO68>;
			output-high;
		};
	};
	camera_pins_cam0_mclk_off: camera_pins_cam0_mclk_off {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO22__FUNC_GPIO22>;
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};
	camera_pins_cam0_mclk_2ma: camera_pins_cam0_mclk_2ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO22__FUNC_CMMCLK0>;
			drive-strength = <MTK_DRIVE_2mA>;
		};
	};
	camera_pins_cam0_mclk_4ma: camera_pins_cam0_mclk_4ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO22__FUNC_CMMCLK0>;
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};
	camera_pins_cam0_mclk_6ma: camera_pins_cam0_mclk_6ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO22__FUNC_CMMCLK0>;
			drive-strength = <MTK_DRIVE_6mA>;
		};
	};
	camera_pins_cam0_mclk_8ma: camera_pins_cam0_mclk_8ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO22__FUNC_CMMCLK0>;
			drive-strength = <MTK_DRIVE_8mA>;
		};
	};
	camera_pins_cam1_mclk_off: camera_pins_cam1_mclk_off {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO23__FUNC_GPIO23>;
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};
	camera_pins_cam1_mclk_2ma: camera_pins_cam1_mclk_2ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO23__FUNC_CMMCLK1>;
			drive-strength = <MTK_DRIVE_2mA>;
		};
	};
	camera_pins_cam1_mclk_4ma: camera_pins_cam1_mclk_4ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO23__FUNC_CMMCLK1>;
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};
	camera_pins_cam1_mclk_6ma: camera_pins_cam1_mclk_6ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO23__FUNC_CMMCLK1>;
			drive-strength = <MTK_DRIVE_6mA>;
		};
	};
	camera_pins_cam1_mclk_8ma: camera_pins_cam1_mclk_8ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO23__FUNC_CMMCLK1>;
			drive-strength = <MTK_DRIVE_8mA>;
		};
	};
	camera_pins_cam2_mclk_off: camera_pins_cam2_mclk_off {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO24__FUNC_GPIO24>;
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};
	camera_pins_cam2_mclk_2ma: camera_pins_cam2_mclk_2ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO24__FUNC_CMMCLK2>;
			drive-strength = <MTK_DRIVE_2mA>;
		};
	};
	camera_pins_cam2_mclk_4ma: camera_pins_cam2_mclk_4ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO24__FUNC_CMMCLK2>;
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};
	camera_pins_cam2_mclk_6ma: camera_pins_cam2_mclk_6ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO24__FUNC_CMMCLK2>;
			drive-strength = <MTK_DRIVE_6mA>;
		};
	};
	camera_pins_cam2_mclk_8ma: camera_pins_cam2_mclk_8ma {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO24__FUNC_CMMCLK2>;
			drive-strength = <MTK_DRIVE_8mA>;
		};
	};
	camera_pins_default: camdefault {
	};
};
/* CAMERA GPIO end */

&i2c0 {
	sensor0 {
		compatible = "mediatek,imgsensor";
		reg = <0x1a>;

		pinctrl-names = "mclk_off",
				"mclk_2mA",
				"mclk_4mA",
				"mclk_6mA",
				"mclk_8mA",
				"rst_low",
				"rst_high",
				"dvdd_off",
				"dvdd_on";
		pinctrl-0 = <&camera_pins_cam0_mclk_off>;
		pinctrl-1 = <&camera_pins_cam0_mclk_2ma>;
		pinctrl-2 = <&camera_pins_cam0_mclk_4ma>;
		pinctrl-3 = <&camera_pins_cam0_mclk_6ma>;
		pinctrl-4 = <&camera_pins_cam0_mclk_8ma>;
		pinctrl-5 = <&camera_pins_cam0_rst_0>;
		pinctrl-6 = <&camera_pins_cam0_rst_1>;
		pinctrl-7 = <&camera_pins_cam0_vcamd_0>;
		pinctrl-8 = <&camera_pins_cam0_vcamd_1>;
		dovdd-supply = <&mt6359_vcamio_reg>;
		avdd-supply = <&mt6359_vfe28_reg>;

		clocks = <&topckgen CLK_TOP_UNIVPLL_192M_D32>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D16>,
			 <&topckgen CLK_TOP_CLK26M_D2>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D8>,
			 <&topckgen CLK_TOP_UNIVPLL_D6_D16>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D4>,
			 <&topckgen CLK_TOP_UNIVPLL_D6_D8>,
			 <&topckgen CLK_TOP_CAMTG_SEL>;
		clock-names = "6", "12", "13", "24", "26", "48", "52", "mclk";
		status = "okay";

		port {
			sensor0_out: endpoint {
				remote-endpoint = <&seninf_csi_port_0_in>;
			};
		};
	};

	sensor1 {
		compatible = "mediatek,imgsensor";
		reg = <0x10>;
		pinctrl-names = "mclk_off",
				"mclk_2mA",
				"mclk_4mA",
				"mclk_6mA",
				"mclk_8mA",
				"rst_low",
				"rst_high",
				"dvdd_off",
				"dvdd_on";
		pinctrl-0 = <&camera_pins_cam1_mclk_off>;
		pinctrl-1 = <&camera_pins_cam1_mclk_2ma>;
		pinctrl-2 = <&camera_pins_cam1_mclk_4ma>;
		pinctrl-3 = <&camera_pins_cam1_mclk_6ma>;
		pinctrl-4 = <&camera_pins_cam1_mclk_8ma>;
		pinctrl-5 = <&camera_pins_cam1_rst_0>;
		pinctrl-6 = <&camera_pins_cam1_rst_1>;
		pinctrl-7 = <&camera_pins_cam1_vcamd_0>;
		pinctrl-8 = <&camera_pins_cam1_vcamd_1>;
		dovdd-supply = <&mt6359_vcamio_reg>;
		avdd-supply = <&mt6359_vfe28_reg>;

		clocks = <&topckgen CLK_TOP_UNIVPLL_192M_D32>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D16>,
			 <&topckgen CLK_TOP_CLK26M_D2>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D8>,
			 <&topckgen CLK_TOP_UNIVPLL_D6_D16>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D4>,
			 <&topckgen CLK_TOP_UNIVPLL_D6_D8>,
			 <&topckgen CLK_TOP_CAMTG2_SEL>;
		clock-names = "6", "12", "13", "24", "26", "48", "52", "mclk";
		status = "okay";

		port {
			sensor1_out: endpoint {
				remote-endpoint = <&seninf_csi_port_1_in>;
			};
		};
	};

	mtk_camera_eeprom0:camera_eeprom0@50 {
		compatible = "mediatek,camera_eeprom";
		reg = <0x50>;
		status = "okay";
	};

	mtk_camera_eeprom1:camera_eeprom1@51 {
		compatible = "mediatek,camera_eeprom";
		reg = <0x51>;
		status = "okay";
	};
};

&i2c1 {
	sensor2 {
		compatible = "mediatek,imgsensor";
		reg = <0x10>;
		pinctrl-names = "mclk_off",
				"mclk_2mA",
				"mclk_4mA",
				"mclk_6mA",
				"mclk_8mA",
				"rst_low",
				"rst_high",
				"dvdd_off",
				"dvdd_on",
				"avdd_off",
				"avdd_on";
		pinctrl-0 = <&camera_pins_cam2_mclk_off>;
		pinctrl-1 = <&camera_pins_cam2_mclk_2ma>;
		pinctrl-2 = <&camera_pins_cam2_mclk_4ma>;
		pinctrl-3 = <&camera_pins_cam2_mclk_6ma>;
		pinctrl-4 = <&camera_pins_cam2_mclk_8ma>;
		pinctrl-5 = <&camera_pins_cam2_rst_0>;
		pinctrl-6 = <&camera_pins_cam2_rst_1>;
		pinctrl-7 = <&camera_pins_cam2_vcamd_0>;
		pinctrl-8 = <&camera_pins_cam2_vcamd_1>;
		pinctrl-9 = <&camera_pins_cam2_vcama_0>;
		pinctrl-10 = <&camera_pins_cam2_vcama_1>;
		dovdd-supply = <&mt6359_vrf18_reg>;
		afvdd-supply = <&mt6359_vcamio_reg>;

		clocks = <&topckgen CLK_TOP_UNIVPLL_192M_D32>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D16>,
			 <&topckgen CLK_TOP_CLK26M_D2>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D8>,
			 <&topckgen CLK_TOP_UNIVPLL_D6_D16>,
			 <&topckgen CLK_TOP_UNIVPLL_192M_D4>,
			 <&topckgen CLK_TOP_UNIVPLL_D6_D8>,
			 <&topckgen CLK_TOP_CAMTG3_SEL>;
		clock-names = "6", "12", "13", "24", "26", "48", "52", "mclk";
		status = "okay";

		port {
			sensor2_out: endpoint {
				remote-endpoint = <&seninf_csi_port_2_in>;
			};
		};
	};

	mtk_camera_eeprom2:camera_eeprom2@50 {
		compatible = "mediatek,camera_eeprom";
		reg = <0x50>;
		status = "okay";
	};
};