/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2021 MediaTek Inc. */ #ifndef __LINUX_REGULATOR_MT6373_H #define __LINUX_REGULATOR_MT6373_H enum { MT6373_ID_VBUCK0, MT6373_ID_VBUCK1, MT6373_ID_VBUCK2, MT6373_ID_VBUCK3, MT6373_ID_VBUCK4, MT6373_ID_VBUCK4_UFS, MT6373_ID_VBUCK5, MT6373_ID_VBUCK6, MT6373_ID_VBUCK7, MT6373_ID_VBUCK8, MT6373_ID_VBUCK9, MT6373_ID_VUSB, MT6373_ID_VAUX18, MT6373_ID_VRF13_AIF, MT6373_ID_VRF18_AIF, MT6373_ID_VRFIO18_AIF, MT6373_ID_VRF09_AIF, MT6373_ID_VRF12_AIF, MT6373_ID_VANT18, MT6373_ID_VSRAM_DIGRF_AIF, MT6373_ID_VIBR, MT6373_ID_VIO28, MT6373_ID_VFP, MT6373_ID_VTP, MT6373_ID_VMCH, MT6373_ID_VMC, MT6373_ID_VAUD18, MT6373_ID_VCN33_1, MT6373_ID_VCN33_2, MT6373_ID_VCN33_3, MT6373_ID_VCN18IO, MT6373_ID_VEFUSE, MT6373_ID_VMCH_EINT_HIGH, MT6373_ID_VMCH_EINT_LOW, MT6373_MAX_REGULATOR, }; /* Register */ #define MT6373_BUCK_TOP_KEY_PROT_LO 0x142a #define MT6373_TOP_CFG_ELR5 0x147 #define MT6373_PMIC_RG_BUCK_VBUCK0_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK0_EN_SHIFT 0 #define MT6373_PMIC_RG_BUCK_VBUCK1_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK1_EN_SHIFT 1 #define MT6373_PMIC_RG_BUCK_VBUCK2_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK2_EN_SHIFT 2 #define MT6373_PMIC_RG_BUCK_VBUCK3_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK3_EN_SHIFT 3 #define MT6373_PMIC_RG_BUCK_VBUCK4_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK4_EN_SHIFT 4 #define MT6373_PMIC_RG_BUCK_VBUCK5_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK5_EN_SHIFT 5 #define MT6373_PMIC_RG_BUCK_VBUCK6_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK6_EN_SHIFT 6 #define MT6373_PMIC_RG_BUCK_VBUCK7_EN_ADDR 0x240 #define MT6373_PMIC_RG_BUCK_VBUCK7_EN_SHIFT 7 #define MT6373_PMIC_RG_BUCK_VBUCK8_EN_ADDR 0x243 #define MT6373_PMIC_RG_BUCK_VBUCK8_EN_SHIFT 0 #define MT6373_PMIC_RG_BUCK_VBUCK9_EN_ADDR 0x243 #define MT6373_PMIC_RG_BUCK_VBUCK9_EN_SHIFT 1 #define MT6373_PMIC_RG_BUCK_VBUCK0_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK0_LP_SHIFT 0 #define MT6373_PMIC_RG_BUCK_VBUCK1_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK1_LP_SHIFT 1 #define MT6373_PMIC_RG_BUCK_VBUCK2_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK2_LP_SHIFT 2 #define MT6373_PMIC_RG_BUCK_VBUCK3_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK3_LP_SHIFT 3 #define MT6373_PMIC_RG_BUCK_VBUCK4_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK4_LP_SHIFT 4 #define MT6373_PMIC_RG_BUCK_VBUCK5_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK5_LP_SHIFT 5 #define MT6373_PMIC_RG_BUCK_VBUCK6_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK6_LP_SHIFT 6 #define MT6373_PMIC_RG_BUCK_VBUCK7_LP_ADDR 0x246 #define MT6373_PMIC_RG_BUCK_VBUCK7_LP_SHIFT 7 #define MT6373_PMIC_RG_BUCK_VBUCK8_LP_ADDR 0x249 #define MT6373_PMIC_RG_BUCK_VBUCK8_LP_SHIFT 0 #define MT6373_PMIC_RG_BUCK_VBUCK9_LP_ADDR 0x249 #define MT6373_PMIC_RG_BUCK_VBUCK9_LP_SHIFT 1 #define MT6373_PMIC_RG_BUCK_VBUCK0_VOSEL_ADDR 0x24c #define MT6373_PMIC_RG_BUCK_VBUCK0_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK1_VOSEL_ADDR 0x24d #define MT6373_PMIC_RG_BUCK_VBUCK1_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK2_VOSEL_ADDR 0x24e #define MT6373_PMIC_RG_BUCK_VBUCK2_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK3_VOSEL_ADDR 0x24f #define MT6373_PMIC_RG_BUCK_VBUCK3_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK4_VOSEL_ADDR 0x250 #define MT6373_PMIC_RG_BUCK_VBUCK4_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK5_VOSEL_ADDR 0x251 #define MT6373_PMIC_RG_BUCK_VBUCK5_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK6_VOSEL_ADDR 0x252 #define MT6373_PMIC_RG_BUCK_VBUCK6_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK7_VOSEL_ADDR 0x253 #define MT6373_PMIC_RG_BUCK_VBUCK7_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK8_VOSEL_ADDR 0x254 #define MT6373_PMIC_RG_BUCK_VBUCK8_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_BUCK_VBUCK9_VOSEL_ADDR 0x255 #define MT6373_PMIC_RG_BUCK_VBUCK9_VOSEL_MASK 0xFF #define MT6373_PMIC_RG_VBUCK8_FCCM_ADDR 0x199d #define MT6373_PMIC_RG_VBUCK8_FCCM_SHIFT 6 #define MT6373_PMIC_RG_VBUCK9_FCCM_ADDR 0x199d #define MT6373_PMIC_RG_VBUCK9_FCCM_SHIFT 7 #define MT6373_PMIC_RG_VBUCK0_FCCM_ADDR 0x1a32 #define MT6373_PMIC_RG_VBUCK0_FCCM_SHIFT 0 #define MT6373_PMIC_RG_VBUCK1_FCCM_ADDR 0x1a32 #define MT6373_PMIC_RG_VBUCK1_FCCM_SHIFT 1 #define MT6373_PMIC_RG_VBUCK2_FCCM_ADDR 0x1a32 #define MT6373_PMIC_RG_VBUCK2_FCCM_SHIFT 2 #define MT6373_PMIC_RG_VBUCK3_FCCM_ADDR 0x1a32 #define MT6373_PMIC_RG_VBUCK3_FCCM_SHIFT 3 #define MT6373_PMIC_RG_VBUCK4_FCCM_ADDR 0x1ab2 #define MT6373_PMIC_RG_VBUCK4_FCCM_SHIFT 0 #define MT6373_PMIC_RG_VBUCK5_FCCM_ADDR 0x1ab2 #define MT6373_PMIC_RG_VBUCK5_FCCM_SHIFT 1 #define MT6373_PMIC_RG_VBUCK6_FCCM_ADDR 0x1ab2 #define MT6373_PMIC_RG_VBUCK6_FCCM_SHIFT 2 #define MT6373_PMIC_RG_VBUCK7_FCCM_ADDR 0x1ab2 #define MT6373_PMIC_RG_VBUCK7_FCCM_SHIFT 3 #define MT6373_PMIC_RG_LDO_VSRAM_DIGRF_AIF_VOSEL_ADDR 0x1b39 #define MT6373_PMIC_RG_LDO_VSRAM_DIGRF_AIF_VOSEL_MASK 0x7F #define MT6373_PMIC_RG_LDO_VAUD18_EN_ADDR 0x1b87 #define MT6373_PMIC_RG_LDO_VAUD18_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VAUD18_LP_ADDR 0x1b87 #define MT6373_PMIC_RG_LDO_VAUD18_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VUSB_EN_ADDR 0x1b95 #define MT6373_PMIC_RG_LDO_VUSB_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VUSB_LP_ADDR 0x1b95 #define MT6373_PMIC_RG_LDO_VUSB_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VAUX18_EN_ADDR 0x1ba3 #define MT6373_PMIC_RG_LDO_VAUX18_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VAUX18_LP_ADDR 0x1ba3 #define MT6373_PMIC_RG_LDO_VAUX18_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VRF13_AIF_EN_ADDR 0x1bb1 #define MT6373_PMIC_RG_LDO_VRF13_AIF_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VRF13_AIF_LP_ADDR 0x1bb1 #define MT6373_PMIC_RG_LDO_VRF13_AIF_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VRF18_AIF_EN_ADDR 0x1bbf #define MT6373_PMIC_RG_LDO_VRF18_AIF_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VRF18_AIF_LP_ADDR 0x1bbf #define MT6373_PMIC_RG_LDO_VRF18_AIF_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VRFIO18_AIF_EN_ADDR 0x1bcd #define MT6373_PMIC_RG_LDO_VRFIO18_AIF_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VRFIO18_AIF_LP_ADDR 0x1bcd #define MT6373_PMIC_RG_LDO_VRFIO18_AIF_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VCN33_1_EN_ADDR 0x1c07 #define MT6373_PMIC_RG_LDO_VCN33_1_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VCN33_1_LP_ADDR 0x1c07 #define MT6373_PMIC_RG_LDO_VCN33_1_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VCN33_2_EN_ADDR 0x1c15 #define MT6373_PMIC_RG_LDO_VCN33_2_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VCN33_2_LP_ADDR 0x1c15 #define MT6373_PMIC_RG_LDO_VCN33_2_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VCN33_3_EN_ADDR 0x1c23 #define MT6373_PMIC_RG_LDO_VCN33_3_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VCN33_3_LP_ADDR 0x1c23 #define MT6373_PMIC_RG_LDO_VCN33_3_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VCN18IO_EN_ADDR 0x1c31 #define MT6373_PMIC_RG_LDO_VCN18IO_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VCN18IO_LP_ADDR 0x1c31 #define MT6373_PMIC_RG_LDO_VCN18IO_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VRF09_AIF_EN_ADDR 0x1c3f #define MT6373_PMIC_RG_LDO_VRF09_AIF_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VRF09_AIF_LP_ADDR 0x1c3f #define MT6373_PMIC_RG_LDO_VRF09_AIF_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VRF12_AIF_EN_ADDR 0x1c4d #define MT6373_PMIC_RG_LDO_VRF12_AIF_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VRF12_AIF_LP_ADDR 0x1c4d #define MT6373_PMIC_RG_LDO_VRF12_AIF_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VANT18_EN_ADDR 0x1c87 #define MT6373_PMIC_RG_LDO_VANT18_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VANT18_LP_ADDR 0x1c87 #define MT6373_PMIC_RG_LDO_VANT18_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VEFUSE_EN_ADDR 0x1ca3 #define MT6373_PMIC_RG_LDO_VEFUSE_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VEFUSE_LP_ADDR 0x1ca3 #define MT6373_PMIC_RG_LDO_VEFUSE_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VMCH_EN_ADDR 0x1cb1 #define MT6373_PMIC_RG_LDO_VMCH_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VMCH_LP_ADDR 0x1cb1 #define MT6373_PMIC_RG_LDO_VMCH_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VMC_EN_ADDR 0x1cc0 #define MT6373_PMIC_RG_LDO_VMC_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VMC_LP_ADDR 0x1cc0 #define MT6373_PMIC_RG_LDO_VMC_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VIBR_EN_ADDR 0x1cce #define MT6373_PMIC_RG_LDO_VIBR_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VIBR_LP_ADDR 0x1cce #define MT6373_PMIC_RG_LDO_VIBR_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VIO28_EN_ADDR 0x1d07 #define MT6373_PMIC_RG_LDO_VIO28_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VIO28_LP_ADDR 0x1d07 #define MT6373_PMIC_RG_LDO_VIO28_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VFP_EN_ADDR 0x1d15 #define MT6373_PMIC_RG_LDO_VFP_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VFP_LP_ADDR 0x1d15 #define MT6373_PMIC_RG_LDO_VFP_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VTP_EN_ADDR 0x1d23 #define MT6373_PMIC_RG_LDO_VTP_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VTP_LP_ADDR 0x1d23 #define MT6373_PMIC_RG_LDO_VTP_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VSIM1_EN_ADDR 0x1d31 #define MT6373_PMIC_RG_LDO_VSIM1_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VSIM1_LP_ADDR 0x1d31 #define MT6373_PMIC_RG_LDO_VSIM1_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VSIM2_EN_ADDR 0x1d40 #define MT6373_PMIC_RG_LDO_VSIM2_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VSIM2_LP_ADDR 0x1d40 #define MT6373_PMIC_RG_LDO_VSIM2_LP_SHIFT 1 #define MT6373_PMIC_RG_LDO_VSRAM_DIGRF_AIF_EN_ADDR 0x1d87 #define MT6373_PMIC_RG_LDO_VSRAM_DIGRF_AIF_EN_SHIFT 0 #define MT6373_PMIC_RG_LDO_VSRAM_DIGRF_AIF_LP_ADDR 0x1d87 #define MT6373_PMIC_RG_LDO_VSRAM_DIGRF_AIF_LP_SHIFT 1 #define MT6373_PMIC_RG_VAUX18_VOCAL_ADDR 0x1e08 #define MT6373_PMIC_RG_VAUX18_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VAUX18_VOSEL_ADDR 0x1e09 #define MT6373_PMIC_RG_VAUX18_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VUSB_VOCAL_ADDR 0x1e0c #define MT6373_PMIC_RG_VUSB_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VUSB_VOSEL_ADDR 0x1e0d #define MT6373_PMIC_RG_VUSB_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VCN33_1_VOCAL_ADDR 0x1e10 #define MT6373_PMIC_RG_VCN33_1_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VCN33_1_VOSEL_ADDR 0x1e11 #define MT6373_PMIC_RG_VCN33_1_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VCN33_2_VOCAL_ADDR 0x1e14 #define MT6373_PMIC_RG_VCN33_2_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VCN33_2_VOSEL_ADDR 0x1e15 #define MT6373_PMIC_RG_VCN33_2_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VCN33_3_VOCAL_ADDR 0x1e18 #define MT6373_PMIC_RG_VCN33_3_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VCN33_3_VOSEL_ADDR 0x1e19 #define MT6373_PMIC_RG_VCN33_3_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VMCH_VOCAL_ADDR 0x1e1c #define MT6373_PMIC_RG_VMCH_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VMCH_VOSEL_ADDR 0x1e1d #define MT6373_PMIC_RG_VMCH_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VEFUSE_VOCAL_ADDR 0x1e20 #define MT6373_PMIC_RG_VEFUSE_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VEFUSE_VOSEL_ADDR 0x1e21 #define MT6373_PMIC_RG_VEFUSE_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VMC_VOCAL_ADDR 0x1e24 #define MT6373_PMIC_RG_VMC_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VMC_VOSEL_ADDR 0x1e25 #define MT6373_PMIC_RG_VMC_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VIBR_VOCAL_ADDR 0x1e28 #define MT6373_PMIC_RG_VIBR_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VIBR_VOSEL_ADDR 0x1e29 #define MT6373_PMIC_RG_VIBR_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VIO28_VOCAL_ADDR 0x1e2c #define MT6373_PMIC_RG_VIO28_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VIO28_VOSEL_ADDR 0x1e2d #define MT6373_PMIC_RG_VIO28_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VFP_VOCAL_ADDR 0x1e30 #define MT6373_PMIC_RG_VFP_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VFP_VOSEL_ADDR 0x1e31 #define MT6373_PMIC_RG_VFP_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VTP_VOCAL_ADDR 0x1e34 #define MT6373_PMIC_RG_VTP_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VTP_VOSEL_ADDR 0x1e35 #define MT6373_PMIC_RG_VTP_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VSIM1_VOCAL_ADDR 0x1e38 #define MT6373_PMIC_RG_VSIM1_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VSIM1_VOSEL_ADDR 0x1e39 #define MT6373_PMIC_RG_VSIM1_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VSIM2_VOCAL_ADDR 0x1e3c #define MT6373_PMIC_RG_VSIM2_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VSIM2_VOSEL_ADDR 0x1e3d #define MT6373_PMIC_RG_VSIM2_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VAUD18_VOCAL_ADDR 0x1e88 #define MT6373_PMIC_RG_VAUD18_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VAUD18_VOSEL_ADDR 0x1e89 #define MT6373_PMIC_RG_VAUD18_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VRF18_AIF_VOCAL_ADDR 0x1e8c #define MT6373_PMIC_RG_VRF18_AIF_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VRF18_AIF_VOSEL_ADDR 0x1e8d #define MT6373_PMIC_RG_VRF18_AIF_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VCN18IO_VOCAL_ADDR 0x1e90 #define MT6373_PMIC_RG_VCN18IO_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VCN18IO_VOSEL_ADDR 0x1e91 #define MT6373_PMIC_RG_VCN18IO_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VRFIO18_AIF_VOCAL_ADDR 0x1e94 #define MT6373_PMIC_RG_VRFIO18_AIF_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VRFIO18_AIF_VOSEL_ADDR 0x1e95 #define MT6373_PMIC_RG_VRFIO18_AIF_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VANT18_VOCAL_ADDR 0x1e98 #define MT6373_PMIC_RG_VANT18_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VANT18_VOSEL_ADDR 0x1e99 #define MT6373_PMIC_RG_VANT18_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VRF13_AIF_VOCAL_ADDR 0x1f08 #define MT6373_PMIC_RG_VRF13_AIF_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VRF13_AIF_VOSEL_ADDR 0x1f09 #define MT6373_PMIC_RG_VRF13_AIF_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VRF12_AIF_VOCAL_ADDR 0x1f0c #define MT6373_PMIC_RG_VRF12_AIF_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VRF12_AIF_VOSEL_ADDR 0x1f0d #define MT6373_PMIC_RG_VRF12_AIF_VOSEL_MASK 0xF #define MT6373_PMIC_RG_VRF09_AIF_VOCAL_ADDR 0x1f88 #define MT6373_PMIC_RG_VRF09_AIF_VOCAL_MASK 0xF #define MT6373_PMIC_RG_VRF09_AIF_VOSEL_ADDR 0x1f89 #define MT6373_PMIC_RG_VRF09_AIF_VOSEL_MASK 0xF #define MT6373_LDO_VMCH_EINT 0x1cbf #define MT6373_PMIC_RG_LDO_VMCH_EINT_EN_MASK 0x1 #define MT6373_PMIC_RG_LDO_VMCH_EINT_POL_MASK 0x4 #define MT6373_PMIC_RG_LDO_VMCH_EINT_DB_MASK 0x10 #endif /* __LINUX_REGULATOR_MT6373_H */