/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2022 MediaTek Inc.
 */

#ifndef __MFD_MT6377_CORE_H__
#define __MFD_MT6377_CORE_H__

#define MT6377_REG_WIDTH 8

enum mt6377_irq_top_status_shift {
	MT6377_BUCK_TOP = 0,
	MT6377_LDO_TOP,
	MT6377_PSC_TOP,
	MT6377_MISC_TOP,
	MT6377_HK_TOP,
	MT6377_SCK_TOP,
	MT6377_BM_TOP,
	MT6377_AUD_TOP,
};

enum mt6377_irq_numbers {
	MT6377_IRQ_VBUCK1_OC = 0,
	MT6377_IRQ_VBUCK2_OC,
	MT6377_IRQ_VBUCK3_OC,
	MT6377_IRQ_VBUCK4_OC,
	MT6377_IRQ_VBUCK5_OC,
	MT6377_IRQ_VBUCK6_OC,
	MT6377_IRQ_VS1_OC,
	MT6377_IRQ_VS2_OC,
	MT6377_IRQ_VPA_OC,
	MT6377_IRQ_VA12_OC = 16,
	MT6377_IRQ_VAUD18_OC,
	MT6377_IRQ_VAUD28_OC,
	MT6377_IRQ_VAUX18_OC,
	MT6377_IRQ_VBIF28_OC,
	MT6377_IRQ_VCN33_1_OC,
	MT6377_IRQ_VCN33_2_OC,
	MT6377_IRQ_VCN18_OC,
	MT6377_IRQ_VRFCK_OC,
	MT6377_IRQ_VBBCK_OC,
	MT6377_IRQ_VXO22_OC,
	MT6377_IRQ_VM18_OC,
	MT6377_IRQ_VMDDR_OC,
	MT6377_IRQ_VMDDQ_OC,
	MT6377_IRQ_VEFUSE_OC,
	MT6377_IRQ_VEMC_OC,
	MT6377_IRQ_VUFS_OC,
	MT6377_IRQ_VIO18_OC,
	MT6377_IRQ_VSRAM_MD_OC,
	MT6377_IRQ_VRF18_OC,
	MT6377_IRQ_VRF12_OC,
	MT6377_IRQ_VRF09_OC,
	MT6377_IRQ_VRFVA12_OC,
	MT6377_IRQ_VRFIO18_OC,
	MT6377_IRQ_VMCH_OC,
	MT6377_IRQ_VMC_OC,
	MT6377_IRQ_VSIM1_OC,
	MT6377_IRQ_VSIM2_OC,
	MT6377_IRQ_VSRAM_PROC1_OC,
	MT6377_IRQ_VSRAM_PROC2_OC,
	MT6377_IRQ_VSRAM_OTHERS_OC,
	MT6377_IRQ_VUSB_OC,
	MT6377_IRQ_VIBR_OC,
	MT6377_IRQ_VIO28_OC,
	MT6377_IRQ_VFP_OC,
	MT6377_IRQ_VTP_OC,
	MT6377_IRQ_PWRKEY = 56,
	MT6377_IRQ_HOMEKEY,
	MT6377_IRQ_PWRKEY_R,
	MT6377_IRQ_HOMEKEY_R,
	MT6377_IRQ_NI_LBAT_INT,
	MT6377_IRQ_CHRDET,
	MT6377_IRQ_CHRDET_EDGE,
	MT6377_IRQ_VCDT_HV_DET,
	MT6377_IRQ_RCS0 = 64,
	MT6377_IRQ_SPMI_CMD_ALERT,
	MT6377_IRQ_SPMI_P_CMD_ALERT,
	MT6377_IRQ_AUD_PROTREG = 69,
	MT6377_IRQ_BM_PROTREG,
	MT6377_IRQ_VRC_PROTREG,
	MT6377_IRQ_BUCK_PROTREG = 72,
	MT6377_IRQ_LDO_PROTREG,
	MT6377_IRQ_PSC_PROTREG,
	MT6377_IRQ_PLT_PROTREG,
	MT6377_IRQ_HK_PROTREG,
	MT6377_IRQ_SCK_PROTREG,
	MT6377_IRQ_XPP_PROTREG,
	MT6377_IRQ_TOP_PROTREG,
	MT6377_IRQ_BAT_H = 80,
	MT6377_IRQ_BAT_L,
	MT6377_IRQ_BAT2_H,
	MT6377_IRQ_BAT2_L,
	MT6377_IRQ_BAT_TEMP_H,
	MT6377_IRQ_BAT_TEMP_L,
	MT6377_IRQ_THR_H,
	MT6377_IRQ_THR_L,
	MT6377_IRQ_AUXADC_IMP = 88,
	MT6377_IRQ_NAG_C_DLTV,
	MT6377_IRQ_RTC = 96,
	MT6377_IRQ_FG_BAT_H = 104,
	MT6377_IRQ_FG_BAT_L,
	MT6377_IRQ_FG_CUR_H,
	MT6377_IRQ_FG_CUR_L,
	MT6377_IRQ_FG_ZCV,
	MT6377_IRQ_FG_N_CHARGE_L = 111,
	MT6377_IRQ_FG_IAVG_H = 112,
	MT6377_IRQ_FG_IAVG_L,
	MT6377_IRQ_FG_DISCHARGE = 115,
	MT6377_IRQ_FG_CHARGE = 116,
	MT6377_IRQ_BATON_LV = 120,
	MT6377_IRQ_BATON_BAT_IN = 122,
	MT6377_IRQ_BATON_BAT_OUT,
	MT6377_IRQ_BIF,
	MT6377_IRQ_AUDIO = 128,
	MT6377_IRQ_ACCDET,
	MT6377_IRQ_ACCDET_EINT0,
	MT6377_IRQ_ACCDET_EINT1,
	MT6377_IRQ_NR = 132,
};

#define MT6377_IRQ_BUCK_BASE MT6377_IRQ_VBUCK1_OC
#define MT6377_IRQ_LDO_BASE MT6377_IRQ_VA12_OC
#define MT6377_IRQ_PSC_BASE MT6377_IRQ_PWRKEY
#define MT6377_IRQ_MISC_BASE MT6377_IRQ_RCS0
#define MT6377_IRQ_HK_BASE MT6377_IRQ_BAT_H
#define MT6377_IRQ_SCK_BASE MT6377_IRQ_RTC
#define MT6377_IRQ_BM_BASE MT6377_IRQ_FG_BAT_H
#define MT6377_IRQ_AUD_BASE MT6377_IRQ_AUDIO

#define MT6377_IRQ_BUCK_BITS \
	(MT6377_IRQ_VPA_OC - MT6377_IRQ_BUCK_BASE + 1)
#define MT6377_IRQ_LDO_BITS \
	(MT6377_IRQ_VTP_OC - MT6377_IRQ_LDO_BASE + 1)
#define MT6377_IRQ_PSC_BITS \
	(MT6377_IRQ_VCDT_HV_DET - MT6377_IRQ_PSC_BASE + 1)
#define MT6377_IRQ_MISC_BITS \
	(MT6377_IRQ_TOP_PROTREG - MT6377_IRQ_MISC_BASE + 1)
#define MT6377_IRQ_HK_BITS \
	(MT6377_IRQ_NAG_C_DLTV - MT6377_IRQ_HK_BASE + 1)
#define MT6377_IRQ_SCK_BITS \
	(MT6377_IRQ_RTC - MT6377_IRQ_SCK_BASE + 1)
#define MT6377_IRQ_BM_BITS \
	(MT6377_IRQ_BIF - MT6377_IRQ_BM_BASE + 1)
#define MT6377_IRQ_AUD_BITS \
	(MT6377_IRQ_ACCDET_EINT1 - MT6377_IRQ_AUD_BASE + 1)

#define MT6377_TOP_GEN(sp) \
{ \
	.hwirq_base = MT6377_IRQ_##sp##_BASE, \
	.num_int_regs =	((MT6377_IRQ_##sp##_BITS - 1) / MT6377_REG_WIDTH) + 1, \
	.en_reg = MT6377_##sp##_TOP_INT_CON0, \
	.en_reg_shift = 0x3, \
	.sta_reg = MT6377_##sp##_TOP_INT_STATUS0, \
	.sta_reg_shift = 0x1, \
	.top_offset = MT6377_##sp##_TOP, \
}

#endif /* __MFD_MT6377_CORE_H__ */