/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Yong Liang <yong.liang@mediatek.com>
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
#define _DT_BINDINGS_RESET_CONTROLLER_MT8188

#define MT8188_TOPRGU_APU_SW_RST		2
#define MT8188_TOPRGU_AFE_SW_RST		5
#define MT8188_TOPRGU_INFRA_SW_RST		6
#define MT8188_TOPRGU_SLICE_SW_RST		7
#define MT8188_TOPRGU_MFG_SW_RST		8
#define MT8188_TOPRGU_VENC_SW_RST		9
#define MT8188_TOPRGU_VDEC_SW_RST		10
#define MT8188_TOPRGU_SCP_SW_RST		12
#define MT8188_TOPRGU_APMIXEDSYS_SW_RST	13
#define MT8188_TOPRGU_AUDIO_SW_RST		14
#define MT8188_TOPRGU_CAMSYS_SW_RST		15
#define MT8188_TOPRGU_EDPTX_SW_RST		16
#define MT8188_TOPRGU_PCIE_SW_RST		19
#define MT8188_TOPRGU_ADSPSYS_SW_RST	21
#define MT8188_TOPRGU_DPTX_SW_RST		22
#define MT8188_TOPRGU_SPMI_SW_RST		23

#define MT8188_TOPRGU_SW_RST_NUM		24

#endif