/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2022 MediaTek Inc.
 * Author: Chong-ming Wei <chong-ming.wei@mediatek.com>
 */

#ifndef _DT_BINDINGS_POWER_MT6886_POWER_H
#define _DT_BINDINGS_POWER_MT6886_POWER_H

/* GPU_EB_RPC */
#define MT6886_POWER_DOMAIN_MFG1			0
#define MT6886_POWER_DOMAIN_MFG2			1
#define MT6886_POWER_DOMAIN_MFG9			2
#define MT6886_POWER_DOMAIN_MFG10			3
#define MT6886_POWER_DOMAIN_MFG11			4
#define MT6886_POWER_DOMAIN_MFG12			5
#define MT6886_GPU_EB_RPC_POWER_DOMAIN_NR		6

/* SPM */
#define MT6886_POWER_DOMAIN_MD				0
#define MT6886_POWER_DOMAIN_CONN			1
#define MT6886_POWER_DOMAIN_UFS0_SHUTDOWN		2
#define MT6886_POWER_DOMAIN_UFS0_PHY			3
#define MT6886_POWER_DOMAIN_AUDIO			4
#define MT6886_POWER_DOMAIN_ADSP_TOP_DORMANT		5
#define MT6886_POWER_DOMAIN_ADSP_INFRA			6
#define MT6886_POWER_DOMAIN_ISP_MAIN			7
#define MT6886_POWER_DOMAIN_ISP_DIP1			8
#define MT6886_POWER_DOMAIN_ISP_VCORE			9
#define MT6886_POWER_DOMAIN_VDE0			10
#define MT6886_POWER_DOMAIN_VEN0			11
#define MT6886_POWER_DOMAIN_CAM_MAIN			12
#define MT6886_POWER_DOMAIN_CAM_MRAW			13
#define MT6886_POWER_DOMAIN_CAM_SUBA			14
#define MT6886_POWER_DOMAIN_CAM_SUBB			15
#define MT6886_POWER_DOMAIN_CAM_VCORE			16
#define MT6886_POWER_DOMAIN_MDP0			17
#define MT6886_POWER_DOMAIN_DISP			18
#define MT6886_POWER_DOMAIN_MM_INFRA			19
#define MT6886_POWER_DOMAIN_MM_PROC_DORMANT		20
#define MT6886_POWER_DOMAIN_APU				21
#define MT6886_SPM_POWER_DOMAIN_NR			22


#endif /* _DT_BINDINGS_POWER_MT6886_POWER_H */