/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2022 MediaTek Inc. * Author: Chong-ming Wei */ #ifndef _DT_BINDINGS_CLK_MT6886_H #define _DT_BINDINGS_CLK_MT6886_H /* TOPCKGEN */ #define CLK_TOP_AXI_SEL 0 #define CLK_TOP_P_AXI_SEL 1 #define CLK_TOP_U_HAXI_SEL 2 #define CLK_TOP_BUS_AXIMEM_SEL 3 #define CLK_TOP_DISP0_SEL 4 #define CLK_TOP_MDP0_SEL 5 #define CLK_TOP_MMINFRA_SEL 6 #define CLK_TOP_MMUP_SEL 7 #define CLK_TOP_DSP_SEL 8 #define CLK_TOP_CAMTG_SEL 9 #define CLK_TOP_CAMTG2_SEL 10 #define CLK_TOP_CAMTG3_SEL 11 #define CLK_TOP_CAMTG4_SEL 12 #define CLK_TOP_CAMTG5_SEL 13 #define CLK_TOP_CAMTG6_SEL 14 #define CLK_TOP_UART_SEL 15 #define CLK_TOP_SPI_SEL 16 #define CLK_TOP_MSDC_MACRO_SEL 17 #define CLK_TOP_MSDC30_1_SEL 18 #define CLK_TOP_MSDC30_2_SEL 19 #define CLK_TOP_AUDIO_SEL 20 #define CLK_TOP_AUD_INTBUS_SEL 21 #define CLK_TOP_ATB_SEL 22 #define CLK_TOP_DISP_PWM_SEL 23 #define CLK_TOP_USB_TOP_SEL 24 #define CLK_TOP_USB_XHCI_SEL 25 #define CLK_TOP_I2C_SEL 26 #define CLK_TOP_SENINF_SEL 27 #define CLK_TOP_SENINF1_SEL 28 #define CLK_TOP_SENINF2_SEL 29 #define CLK_TOP_SENINF3_SEL 30 #define CLK_TOP_AUD_ENGEN1_SEL 31 #define CLK_TOP_AUD_ENGEN2_SEL 32 #define CLK_TOP_AES_UFSFDE_SEL 33 #define CLK_TOP_U_SEL 34 #define CLK_TOP_U_MBIST_SEL 35 #define CLK_TOP_AUD_1_SEL 36 #define CLK_TOP_AUD_2_SEL 37 #define CLK_TOP_ADSP_SEL 38 #define CLK_TOP_DPMAIF_MAIN_SEL 39 #define CLK_TOP_VENC_SEL 40 #define CLK_TOP_VDEC_SEL 41 #define CLK_TOP_PWM_SEL 42 #define CLK_TOP_AUDIO_H_SEL 43 #define CLK_TOP_MCUPM_SEL 44 #define CLK_TOP_MEM_SUB_SEL 45 #define CLK_TOP_P_MEM_SEL 46 #define CLK_TOP_U_MEM_SEL 47 #define CLK_TOP_EMI_N_SEL 48 #define CLK_TOP_DSI_OCC_SEL 49 #define CLK_TOP_CCU_AHB_SEL 50 #define CLK_TOP_AP2CONN_HOST_SEL 51 #define CLK_TOP_IMG1_SEL 52 #define CLK_TOP_IPE_SEL 53 #define CLK_TOP_CAM_SEL 54 #define CLK_TOP_CCUSYS_SEL 55 #define CLK_TOP_CAMTM_SEL 56 #define CLK_TOP_MCU_ACP_SEL 57 #define CLK_TOP_CSI_OCC_SCAN_SEL 58 #define CLK_TOP_IPSWEST_SEL 59 #define CLK_TOP_IPSNORTH_SEL 60 #define CLK_TOP_AXI_L3GIC_SEL 61 #define CLK_TOP_APLL_I2S0_MCK_SEL 62 #define CLK_TOP_APLL_I2S1_MCK_SEL 63 #define CLK_TOP_APLL_I2S2_MCK_SEL 64 #define CLK_TOP_APLL_I2S3_MCK_SEL 65 #define CLK_TOP_APLL_I2S4_MCK_SEL 66 #define CLK_TOP_APLL_I2S5_MCK_SEL 67 #define CLK_TOP_APLL_I2S6_MCK_SEL 68 #define CLK_TOP_APLL_I2S7_MCK_SEL 69 #define CLK_TOP_APLL_I2S8_MCK_SEL 70 #define CLK_TOP_APLL_I2S9_MCK_SEL 71 #define CLK_TOP_APLL_ETDM_IN1_MCK_SEL 72 #define CLK_TOP_APLL_ETDM_OUT1_MCK_SEL 73 #define CLK_TOP_APLL12_CK_DIV0 74 #define CLK_TOP_APLL12_CK_DIV1 75 #define CLK_TOP_APLL12_CK_DIV2 76 #define CLK_TOP_APLL12_CK_DIV3 77 #define CLK_TOP_APLL12_CK_DIV4 78 #define CLK_TOP_APLL12_CK_DIVB 79 #define CLK_TOP_APLL12_CK_DIV5 80 #define CLK_TOP_APLL12_CK_DIV6 81 #define CLK_TOP_APLL12_CK_DIV7 82 #define CLK_TOP_APLL12_CK_DIV8 83 #define CLK_TOP_APLL12_CK_DIV9 84 #define CLK_TOP_APLL12_CK_DIV_ETDM_IN1 85 #define CLK_TOP_APLL12_CK_DIV_ETDM_OUT1 86 #define CLK_TOP_CLKRTC 87 #define CLK_TOP_TCK_26M_MX9 88 #define CLK_TOP_F26M_CK_D2 89 #define CLK_TOP_MMPLL_D4 90 #define CLK_TOP_MMPLL_D4_D2 91 #define CLK_TOP_MMPLL_D5_D2 92 #define CLK_TOP_MMPLL_D6 93 #define CLK_TOP_MMPLL_D6_D2 94 #define CLK_TOP_MMPLL_D7 95 #define CLK_TOP_MMPLL_D9 96 #define CLK_TOP_MAINPLL_D3 97 #define CLK_TOP_MAINPLL_D4 98 #define CLK_TOP_MAINPLL_D4_D2 99 #define CLK_TOP_MAINPLL_D4_D4 100 #define CLK_TOP_MAINPLL_D4_D8 101 #define CLK_TOP_MAINPLL_D4_D16 102 #define CLK_TOP_MAINPLL_D5 103 #define CLK_TOP_MAINPLL_D5_D2 104 #define CLK_TOP_MAINPLL_D5_D4 105 #define CLK_TOP_MAINPLL_D5_D8 106 #define CLK_TOP_MAINPLL_D6 107 #define CLK_TOP_MAINPLL_D6_D2 108 #define CLK_TOP_MAINPLL_D6_D4 109 #define CLK_TOP_MAINPLL_D7 110 #define CLK_TOP_MAINPLL_D7_D2 111 #define CLK_TOP_MAINPLL_D7_D4 112 #define CLK_TOP_MAINPLL_D7_D8 113 #define CLK_TOP_MAINPLL_D9 114 #define CLK_TOP_UNIVPLL_D3 115 #define CLK_TOP_UNIVPLL_D4 116 #define CLK_TOP_UNIVPLL_D4_D2 117 #define CLK_TOP_UNIVPLL_D4_D4 118 #define CLK_TOP_UNIVPLL_D4_D8 119 #define CLK_TOP_UNIVPLL_D5 120 #define CLK_TOP_UNIVPLL_D5_D2 121 #define CLK_TOP_UNIVPLL_D5_D4 122 #define CLK_TOP_UNIVPLL_D6 123 #define CLK_TOP_UNIVPLL_D6_D2 124 #define CLK_TOP_UNIVPLL_D6_D4 125 #define CLK_TOP_UNIVPLL_D6_D8 126 #define CLK_TOP_UNIVPLL_D6_D16 127 #define CLK_TOP_UNIVPLL_D7 128 #define CLK_TOP_UNIVPLL_D7_D2 129 #define CLK_TOP_UNIVPLL_192M 130 #define CLK_TOP_UNIVPLL_192M_D2 131 #define CLK_TOP_UNIVPLL_192M_D4 132 #define CLK_TOP_UNIVPLL_192M_D8 133 #define CLK_TOP_UNIVPLL_192M_D10 134 #define CLK_TOP_UNIVPLL_192M_D16 135 #define CLK_TOP_UNIVPLL_192M_D32 136 #define CLK_TOP_MSDCPLL 137 #define CLK_TOP_MSDCPLL_D2 138 #define CLK_TOP_APLL1 139 #define CLK_TOP_APLL1_D2 140 #define CLK_TOP_APLL1_D4 141 #define CLK_TOP_APLL1_D8 142 #define CLK_TOP_APLL2 143 #define CLK_TOP_APLL2_D2 144 #define CLK_TOP_APLL2_D4 145 #define CLK_TOP_APLL2_D8 146 #define CLK_TOP_ADSPPLL 147 #define CLK_TOP_EMIPLL 148 #define CLK_TOP_IMGPLL_D2 149 #define CLK_TOP_IMGPLL_D5 150 #define CLK_TOP_UFSPLL_D2 151 #define CLK_TOP_OSC 152 #define CLK_TOP_ULPOSC 153 #define CLK_TOP_OSC_D2 154 #define CLK_TOP_OSC_D2P5 155 #define CLK_TOP_OSC_D3 156 #define CLK_TOP_OSC_D4 157 #define CLK_TOP_OSC_D5 158 #define CLK_TOP_OSC_D7 159 #define CLK_TOP_OSC_D8 160 #define CLK_TOP_OSC_D16 161 #define CLK_TOP_OSC_D10 162 #define CLK_TOP_OSC_D20 163 #define CLK_TOP_OSC2_D4 164 #define CLK_TOP_F26M 165 #define CLK_TOP_AXI 166 #define CLK_TOP_P_AXI 167 #define CLK_TOP_DISP0 168 #define CLK_TOP_MDP0 169 #define CLK_TOP_MMINFRA 170 #define CLK_TOP_DSP 171 #define CLK_TOP_UART 172 #define CLK_TOP_SPI 173 #define CLK_TOP_MSDC30_1 174 #define CLK_TOP_AUDIO 175 #define CLK_TOP_AUD_INTBUS 176 #define CLK_TOP_DISP_PWM 177 #define CLK_TOP_USB_TOP 178 #define CLK_TOP_USB_XHCI 179 #define CLK_TOP_I2C 180 #define CLK_TOP_AUD_ENGEN1 181 #define CLK_TOP_AUD_ENGEN2 182 #define CLK_TOP_AES_UFSFDE 183 #define CLK_TOP_UFS 184 #define CLK_TOP_AUD_1 185 #define CLK_TOP_DPMAIF_MAIN 186 #define CLK_TOP_VENC 187 #define CLK_TOP_VDEC 188 #define CLK_TOP_PWM 189 #define CLK_TOP_AUDIO_H 190 #define CLK_TOP_CCU_AHB 191 #define CLK_TOP_IMG1 192 #define CLK_TOP_IPE 193 #define CLK_TOP_CAM 194 #define CLK_TOP_CCUSYS 195 #define CLK_TOP_CAMTM 196 #define CLK_TOP_IMGAVS 197 #define CLK_TOP_I2C_PSEUDO 198 #define CLK_TOP_ARMPLL_DIVIDER_PLL1_CK_EN 199 #define CLK_TOP_ARMPLL_DIVIDER_PLL2_CK_EN 200 #define CLK_TOP_U_SAP_CFG_CK_EN 201 #define CLK_TOP_MD_32K 202 #define CLK_TOP_NR_CLK 203 /* INFRACFG_AO */ #define CLK_IFRAO_I2C_DUMMY 0 #define CLK_IFRAO_THERM 1 #define CLK_IFRAO_CQ_DMA_FPC 2 #define CLK_IFRAO_CCIF1_AP 3 #define CLK_IFRAO_CCIF1_MD 4 #define CLK_IFRAO_CCIF_AP 5 #define CLK_IFRAO_CCIF_MD 6 #define CLK_IFRAO_CLDMA_BCLK 7 #define CLK_IFRAO_CQ_DMA 8 #define CLK_IFRAO_CCIF5_MD 9 #define CLK_IFRAO_CCIF2_AP 10 #define CLK_IFRAO_CCIF2_MD 11 #define CLK_IFRAO_DPMAIF_MAIN 12 #define CLK_IFRAO_CCIF4_MD 13 #define CLK_IFRAO_RG_MMW_DPMAIF26M 14 #define CLK_IFRAO_NR_CLK 15 /* APMIXEDSYS */ #define CLK_APMIXED_MAINPLL 0 #define CLK_APMIXED_UNIVPLL 1 #define CLK_APMIXED_MSDCPLL 2 #define CLK_APMIXED_MMPLL 3 #define CLK_APMIXED_ADSPPLL 4 #define CLK_APMIXED_UFSPLL 5 #define CLK_APMIXED_APLL1 6 #define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_MPLL 8 #define CLK_APMIXED_EMIPLL 9 #define CLK_APMIXED_IMGPLL 10 #define CLK_APMIXED_NR_CLK 11 /* PERICFG_AO */ #define CLK_PERAO_UART0 0 #define CLK_PERAO_UART1 1 #define CLK_PERAO_PWM_H 2 #define CLK_PERAO_PWM_B 3 #define CLK_PERAO_PWM_FB1 4 #define CLK_PERAO_PWM_FB2 5 #define CLK_PERAO_PWM_FB3 6 #define CLK_PERAO_PWM_FB4 7 #define CLK_PERAO_BTIF_B 8 #define CLK_PERAO_DISP_PWM0 9 #define CLK_PERAO_SPI0_B 10 #define CLK_PERAO_SPI1_B 11 #define CLK_PERAO_SPI2_B 12 #define CLK_PERAO_SPI3_B 13 #define CLK_PERAO_SPI4_B 14 #define CLK_PERAO_SPI5_B 15 #define CLK_PERAO_SPI6_B 16 #define CLK_PERAO_SPI7_B 17 #define CLK_PERAO_APDMA 18 #define CLK_PERAO_USB_SYS 19 #define CLK_PERAO_USB_XHCI 20 #define CLK_PERAO_USB_BUS 21 #define CLK_PERAO_MSDC1 22 #define CLK_PERAO_MSDC1_H 23 #define CLK_PERAO_AUDIO_SLV_CKP 24 #define CLK_PERAO_AUDIO_MST_CKP 25 #define CLK_PERAO_INTBUS_CKP 26 #define CLK_PERAO_AUDIO_MST_IDLE_EN 27 #define CLK_PERAO_NR_CLK 28 /* AFE */ #define CLK_AFE_AFE 0 #define CLK_AFE_22M 1 #define CLK_AFE_24M 2 #define CLK_AFE_APLL2_TUNER 3 #define CLK_AFE_APLL_TUNER 4 #define CLK_AFE_TDM 5 #define CLK_AFE_ADC 6 #define CLK_AFE_DAC 7 #define CLK_AFE_DAC_PREDIS 8 #define CLK_AFE_TML 9 #define CLK_AFE_NLE 10 #define CLK_AFE_GENERAL3_ASRC 11 #define CLK_AFE_CONNSYS_I2S_ASRC 12 #define CLK_AFE_GENERAL1_ASRC 13 #define CLK_AFE_GENERAL2_ASRC 14 #define CLK_AFE_DAC_HIRES 15 #define CLK_AFE_ADC_HIRES 16 #define CLK_AFE_ADC_HIRES_TML 17 #define CLK_AFE_ADDA6_ADC 18 #define CLK_AFE_ADDA6_ADC_HIRES 19 #define CLK_AFE_3RD_DAC 20 #define CLK_AFE_3RD_DAC_PREDIS 21 #define CLK_AFE_3RD_DAC_TML 22 #define CLK_AFE_3RD_DAC_HIRES 23 #define CLK_AFE_I2S5_BCLK 24 #define CLK_AFE_I2S6_BCLK 25 #define CLK_AFE_I2S7_BCLK 26 #define CLK_AFE_I2S8_BCLK 27 #define CLK_AFE_I2S9_BCLK 28 #define CLK_AFE_ETDM_IN0_BCLK 29 #define CLK_AFE_ETDM_OUT0_BCLK 30 #define CLK_AFE_I2S1_BCLK 31 #define CLK_AFE_I2S2_BCLK 32 #define CLK_AFE_I2S3_BCLK 33 #define CLK_AFE_I2S4_BCLK 34 #define CLK_AFE_ETDM_IN1_BCLK 35 #define CLK_AFE_ETDM_OUT1_BCLK 36 #define CLK_AFE_NR_CLK 37 /* IMP_IIC_WRAP_C */ #define CLK_IMPC_I2C5 0 #define CLK_IMPC_I2C6 1 #define CLK_IMPC_I2C10 2 #define CLK_IMPC_I2C11 3 #define CLK_IMPC_NR_CLK 4 /* UFSCFG_AO */ #define CLK_UFSAO_UNIPRO_TX_SYM 0 #define CLK_UFSAO_UNIPRO_RX_SYM0 1 #define CLK_UFSAO_UNIPRO_RX_SYM1 2 #define CLK_UFSAO_UNIPRO_SYS 3 #define CLK_UFSAO_UNIPRO_PHY_SAP 4 #define CLK_UFSAO_NR_CLK 5 /* UFSCFG_PDN */ #define CLK_UFSPDN_UFSHCI_UFS 0 #define CLK_UFSPDN_UFSHCI_AES 1 #define CLK_UFSPDN_NR_CLK 2 /* IMP_IIC_WRAP_ES */ #define CLK_IMPES_I2C2 0 #define CLK_IMPES_I2C4 1 #define CLK_IMPES_I2C9 2 #define CLK_IMPES_NR_CLK 3 /* IMP_IIC_WRAP_W */ #define CLK_IMPW_I2C0 0 #define CLK_IMPW_I2C1 1 #define CLK_IMPW_NR_CLK 2 /* IMP_IIC_WRAP_E */ #define CLK_IMPE_I2C3 0 #define CLK_IMPE_I2C7 1 #define CLK_IMPE_I2C8 2 #define CLK_IMPE_NR_CLK 3 /* MFGPLL_PLL_CTRL */ #define CLK_MFG_AO_MFGPLL 0 #define CLK_MFG_AO_NR_CLK 1 /* MFGSCPLL_PLL_CTRL */ #define CLK_MFGSC_AO_MFGSCPLL 0 #define CLK_MFGSC_AO_NR_CLK 1 /* DISPSYS_CONFIG */ #define CLK_MM_DISP_MUTEX0 0 #define CLK_MM_DISP_OVL0 1 #define CLK_MM_DISP_MERGE0 2 #define CLK_MM_DISP_FAKE_ENG0 3 #define CLK_MM_INLINEROT0 4 #define CLK_MM_DISP_WDMA0 5 #define CLK_MM_DISP_FAKE_ENG1 6 #define CLK_MM_DISP_OVL0_2L_NW 7 #define CLK_MM_DISP_RDMA0 8 #define CLK_MM_DISP_RDMA1 9 #define CLK_MM_DISP_RSZ0 10 #define CLK_MM_DISP_COLOR0 11 #define CLK_MM_DISP_CCORR0 12 #define CLK_MM_DISP_CCORR1 13 #define CLK_MM_DISP_AAL0 14 #define CLK_MM_DISP_GAMMA0 15 #define CLK_MM_DISP_POSTMASK0 16 #define CLK_MM_DISP_DITHER0 17 #define CLK_MM_DISP_CM0 18 #define CLK_MM_DISP_SPR0 19 #define CLK_MM_DISP_DSC_WRAP0 20 #define CLK_MM_FMM_DISP_DSI0 21 #define CLK_MM_DISP_UFBC_WDMA0 22 #define CLK_MM_DISP_WDMA1 23 #define CLK_MM_APB_BUS 24 #define CLK_MM_DISP_C3D0 25 #define CLK_MM_DISP_Y2R0 26 #define CLK_MM_DISP_CHIST0 27 #define CLK_MM_DISP_CHIST1 28 #define CLK_MM_DISP_OVL0_2L 29 #define CLK_MM_DISP_DLI_ASYNC3 30 #define CLK_MM_DISP_DLO_ASYNC3 31 #define CLK_MM_DISP_OVL1_2L 32 #define CLK_MM_DISP_OVL1_2L_NW 33 #define CLK_MM_SMI_COMMON 34 #define CLK_MM_DISP_DSI0 35 #define CLK_MM_SIG_EMI 36 #define CLK_MM_NR_CLK 37 /* IMGSYS_MAIN */ #define CLK_IMG_FDVT 0 #define CLK_IMG_ME 1 #define CLK_IMG_MMG 2 #define CLK_IMG_LARB12 3 #define CLK_IMG_LARB9 4 #define CLK_IMG_TRAW0 5 #define CLK_IMG_TRAW1 6 #define CLK_IMG_VCORE_GALS 7 #define CLK_IMG_DIP0 8 #define CLK_IMG_WPE0 9 #define CLK_IMG_IPE 10 #define CLK_IMG_WPE1 11 #define CLK_IMG_WPE2 12 #define CLK_IMG_AVS 13 #define CLK_IMG_GALS 14 #define CLK_IMG_NR_CLK 15 /* DIP_TOP_DIP1 */ #define CLK_DIP_TOP_DIP1_LARB10 0 #define CLK_DIP_TOP_DIP1_DIP_TOP 1 #define CLK_DIP_TOP_DIP1_NR_CLK 2 /* DIP_NR1_DIP1 */ #define CLK_DIP_NR1_DIP1_LARB 0 #define CLK_DIP_NR1_DIP1_DIP_NR1 1 #define CLK_DIP_NR1_DIP1_NR_CLK 2 /* DIP_NR2_DIP1 */ #define CLK_DIP_NR2_DIP1_LARB15 0 #define CLK_DIP_NR2_DIP1_DIP_NR 1 #define CLK_DIP_NR2_DIP1_NR_CLK 2 /* WPE1_DIP1 */ #define CLK_WPE1_DIP1_LARB11 0 #define CLK_WPE1_DIP1_WPE 1 #define CLK_WPE1_DIP1_NR_CLK 2 /* WPE2_DIP1 */ #define CLK_WPE2_DIP1_LARB11 0 #define CLK_WPE2_DIP1_WPE 1 #define CLK_WPE2_DIP1_NR_CLK 2 /* WPE3_DIP1 */ #define CLK_WPE3_DIP1_LARB11 0 #define CLK_WPE3_DIP1_WPE 1 #define CLK_WPE3_DIP1_NR_CLK 2 /* TRAW_DIP1 */ #define CLK_TRAW_DIP1_LARB28 0 #define CLK_TRAW_DIP1_TRAW 1 #define CLK_TRAW_DIP1_NR_CLK 2 /* VDEC_GCON_BASE */ #define CLK_VDE2_LARB1_CKEN 0 #define CLK_VDE2_LAT_CKEN 1 #define CLK_VDE2_LAT_ACTIVE 2 #define CLK_VDE2_MINI_MDP_EN 3 #define CLK_VDE2_VDEC_CKEN 4 #define CLK_VDE2_VDEC_ACTIVE 5 #define CLK_VDE2_NR_CLK 6 /* VENC_GCON */ #define CLK_VEN_CKE0_LARB 0 #define CLK_VEN_CKE1_VENC 1 #define CLK_VEN_CKE2_JPGENC 2 #define CLK_VEN_CKE5_GALS 3 #define CLK_VEN_CKE6_GALS_SRAM 4 #define CLK_VEN_NR_CLK 5 /* VLP_CKSYS */ #define CLK_VLP_CK_SCP_VLP_SEL 0 #define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1 #define CLK_VLP_CK_26M_GPT_VLP_SEL 2 #define CLK_VLP_CK_DXCC_VLP_SEL 3 #define CLK_VLP_CK_SPMI_P_MST_SEL 4 #define CLK_VLP_CK_SPMI_M_MST_SEL 5 #define CLK_VLP_CK_DVFSRC_SEL 6 #define CLK_VLP_CK_PWM_VLP_SEL 7 #define CLK_VLP_CK_AXI_VLP_SEL 8 #define CLK_VLP_CK_DBG_26M_VLP_SEL 9 #define CLK_VLP_CK_STMR26M_VLP_SEL 10 #define CLK_VLP_CK_SSPM_VLP_SEL 11 #define CLK_VLP_CK_SSPM_F26M_SEL 12 #define CLK_VLP_CK_SRCK_SEL 13 #define CLK_VLP_CK_SCP_SPI_SEL 14 #define CLK_VLP_CK_SCP_IIC_SEL 15 #define CLK_VLP_CK_PSVLP_SEL 16 #define CLK_VLP_CK_NR_CLK 17 /* SCP */ #define CLK_SCP_SPI0 0 #define CLK_SCP_SPI1 1 #define CLK_SCP_SPI2 2 #define CLK_SCP_SPI3 3 #define CLK_SCP_SET_SPI0 4 #define CLK_SCP_SET_SPI1 5 #define CLK_SCP_SET_SPI2 6 #define CLK_SCP_SET_SPI3 7 #define CLK_SCP_NR_CLK 8 /* SCP_IIC */ #define CLK_SCP_IIC_I2C0 0 #define CLK_SCP_IIC_I2C1 1 #define CLK_SCP_IIC_I2C2 2 #define CLK_SCP_IIC_I2C3 3 #define CLK_SCP_IIC_I2C4 4 #define CLK_SCP_IIC_I2C5 5 #define CLK_SCP_IIC_I2C6 6 #define CLK_SCP_IIC_NR_CLK 7 /* CAMSYS_MAIN */ #define CLK_CAM_MAIN_LARB13_CON_0 0 #define CLK_CAM_MAIN_LARB14_CON_0 1 #define CLK_CAM_MAIN_LARB27_CON_0 2 #define CLK_CAM_MAIN_LARB29_CON_0 3 #define CLK_CAM_MAIN_CAM_CON_0 4 #define CLK_CAM_MAIN_CAM_SUBA_CON_0 5 #define CLK_CAM_MAIN_CAM_SUBB_CON_0 6 #define CLK_CAM_MAIN_CAM_SUBC_CON_0 7 #define CLK_CAM_MAIN_CAM_MRAW_CON_0 8 #define CLK_CAM_MAIN_CAMTG_CON_0 9 #define CLK_CAM_MAIN_SENINF_CON_0 10 #define CLK_CAM_MAIN_CAMSV_TOP_CON_0 11 #define CLK_CAM_MAIN_ADLRD_CON_0 12 #define CLK_CAM_MAIN_ADLWR_CON_0 13 #define CLK_CAM_MAIN_UISP_CON_0 14 #define CLK_CAM_MAIN_FAKE_ENG_CON_0 15 #define CLK_CAM_MAIN_CAM2MM0_GALS_CON_0 16 #define CLK_CAM_MAIN_CAM2MM1_GALS_CON_0 17 #define CLK_CAM_MAIN_CAM2SYS_GALS_CON_0 18 #define CLK_CAM_MAIN_CAM2MM2_GALS_CON_0 19 #define CLK_CAM_MAIN_CCUSYS_CON_0 20 #define CLK_CAM_MAIN_IPS_CON_0 21 #define CLK_CAM_MAIN_CAMSV_A_CON_1 22 #define CLK_CAM_MAIN_CAMSV_B_CON_1 23 #define CLK_CAM_MAIN_CAMSV_C_CON_1 24 #define CLK_CAM_MAIN_CAMSV_D_CON_1 25 #define CLK_CAM_MAIN_CAMSV_E_CON_1 26 #define CLK_CAM_MAIN_CAMSV_CON_1 27 #define CLK_CAM_M_NR_CLK 28 /* CAMSYS_RAWA */ #define CLK_CAM_RA_LARBX 0 #define CLK_CAM_RA_CAM 1 #define CLK_CAM_RA_CAMTG 2 #define CLK_CAM_RA_NR_CLK 3 /* CAMSYS_YUVA */ #define CLK_CAM_YA_LARBX 0 #define CLK_CAM_YA_CAM 1 #define CLK_CAM_YA_CAMTG 2 #define CLK_CAM_YA_NR_CLK 3 /* CAMSYS_RAWB */ #define CLK_CAM_RB_LARBX 0 #define CLK_CAM_RB_CAM 1 #define CLK_CAM_RB_CAMTG 2 #define CLK_CAM_RB_NR_CLK 3 /* CAMSYS_YUVB */ #define CLK_CAM_YB_LARBX 0 #define CLK_CAM_YB_CAM 1 #define CLK_CAM_YB_CAMTG 2 #define CLK_CAM_YB_NR_CLK 3 /* CAMSYS_MRAW */ #define CLK_CAM_MR_LARBX 0 #define CLK_CAM_MR_CAMTG 1 #define CLK_CAM_MR_MRAW0 2 #define CLK_CAM_MR_MRAW1 3 #define CLK_CAM_MR_MRAW2 4 #define CLK_CAM_MR_MRAW3 5 #define CLK_CAM_MR_PDA0 6 #define CLK_CAM_MR_PDA1 7 #define CLK_CAM_MR_NR_CLK 8 /* CCU_MAIN */ #define CLK_CCU_LARB19 0 #define CLK_CCU_AHB 1 #define CLK_CCUSYS_CCU0 2 #define CLK_CCUSYS_DPE 3 #define CLK_CCU_NR_CLK 4 /* MMINFRA_CONFIG */ #define CLK_MMINFRA_GCE_D 0 #define CLK_MMINFRA_GCE_M 1 #define CLK_MMINFRA_GCE_26M 2 #define CLK_MMINFRA_CONFIG_NR_CLK 3 /* MDPSYS_CONFIG */ #define CLK_MDP_MUTEX0 0 #define CLK_MDP_APB_BUS 1 #define CLK_MDP_SMI0 2 #define CLK_MDP_RDMA0 3 #define CLK_MDP_HDR0 4 #define CLK_MDP_AAL0 5 #define CLK_MDP_RSZ0 6 #define CLK_MDP_TDSHP0 7 #define CLK_MDP_COLOR0 8 #define CLK_MDP_WROT0 9 #define CLK_MDP_FAKE_ENG0 10 #define CLK_MDP_DL_RELAY0 11 #define CLK_MDP_DL_RELAY1 12 #define CLK_MDP_RDMA1 13 #define CLK_MDP_HDR1 14 #define CLK_MDP_AAL1 15 #define CLK_MDP_RSZ1 16 #define CLK_MDP_TDSHP1 17 #define CLK_MDP_COLOR1 18 #define CLK_MDP_WROT1 19 #define CLK_MDP_DLO_ASYNC0 20 #define CLK_MDP_DLO_ASYNC1 21 #define CLK_MDP_HRE_TOP_MDPSYS 22 #define CLK_MDP_NR_CLK 23 /* CCIPLL_PLL_CTRL */ #define CLK_CCIPLL 0 #define CLK_CCI_NR_CLK 1 /* ARMPLL_LL_PLL_CTRL */ #define CLK_CPU_LL_ARMPLL_LL 0 #define CLK_CPU_LL_NR_CLK 1 /* ARMPLL_BL_PLL_CTRL */ #define CLK_CPU_BL_ARMPLL_BL 0 #define CLK_CPU_BL_NR_CLK 1 /* PTPPLL_PLL_CTRL */ #define CLK_PTPPLL 0 #define CLK_PTP_NR_CLK 1 #endif /* _DT_BINDINGS_CLK_MT6886_H */