/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2022 MediaTek Inc.
 * Author: Chong-ming Wei <chong-ming.wei@mediatek.com>
 */

#ifndef _CLK_MT6886_FMETER_H
#define _CLK_MT6886_FMETER_H

/* generate from clock_table.xlsx from TOPCKGEN DE */

/* CKGEN Part */
#define FM_AXI_CK				1
#define FM_AXI_CK_2				2
#define FM_U_HAXI_CK				3
#define FM_BUS_AXIMEM_CK			4
#define FM_DISP0_CK				5
#define FM_MDP0_CK				6
#define FM_MMINFRA_CK				7
#define FM_MMUP_CK				8
#define FM_DSP_CK				9
#define FM_DSP1_CK				10
#define FM_DSP2_CK				11
#define FM_DSP3_CK				12
#define FM_DSP4_CK				13
#define FM_DSP5_CK				14
#define FM_DSP6_CK				15
#define FM_DSP7_CK				16
#define FM_CAMTG_CK				17
#define FM_CAMTG2_CK				18
#define FM_CAMTG3_CK				19
#define FM_CAMTG4_CK				20
#define FM_CAMTG5_CK				21
#define FM_CAMTG6_CK				22
#define FM_UART_CK				23
#define FM_SPI_CK				24
#define FM_MSDC_MACRO_CK			25
#define FM_MSDC30_1_CK				26
#define FM_MSDC30_2_CK				27
#define FM_AUDIO_CK				28
#define FM_AUD_INTBUS_CK			29
#define FM_ATB_CK				30
#define FM_DISP_PWM_CK				31
#define FM_USB_CK				32
#define FM_USB_XHCI_CK				33
#define FM_USB_1P_CK				34
#define FM_USB_XHCI_1P_CK			35
#define FM_I2C_CK				36
#define FM_SENINF_CK				37
#define FM_SENINF1_CK				38
#define FM_SENINF2_CK				39
#define FM_SENINF3_CK				40
#define FM_DXCC_CK				41
#define FM_AUD_ENGEN1_CK			42
#define FM_AUD_ENGEN2_CK			43
#define FM_AES_UFSFDE_CK			44
#define FM_U_CK					45
#define FM_U_MBIST_CK				46
#define FM_PEXTP_MBIST_CK			47
#define FM_AUD_1_CK				48
#define FM_AUD_2_CK				49
#define FM_ADSP_CK				50
#define FM_DPMAIF_MAIN_CK			51
#define FM_VENC_CK				52
#define FM_VDEC_CK				53
#define FM_PWM_CK				54
#define FM_AUDIO_H_CK				55
#define FM_MCUPM_CK				56
#define FM_MEM_SUB_CK				57
#define FM_MEM_CK				58
#define FM_U_MEM_CK				59
#define FM_EMI_N_CK				60
#define FM_DSI_OCC_CK				61
#define FM_CCU_AHB_CK				62
#define FM_AP2CONN_HOST_CK			63
#define FM_IMG1_CK				64
#define FM_IPE_CK				65
#define FM_CAM_CK				66
#define FM_CCUSYS_CK				67
#define FM_CAMTM_CK				68
#define FM_MCU_ACP_CK				69
#define FM_CSI_OCC_SCAN_CK			70
#define FM_IPSWEST_CK				71
#define FM_IPSNORTH_CK				72
#define FM_MCU_ATB_CK				73
#define FM_AXI_L3GIC_CK				74
#define FM_DUMMY_1_CK				75
#define FM_DUMMY_2_CK				76
#define FM_CKGEN_NUM				77
/* ABIST Part */
#define FM_LVTS_CKMON_LM			2
#define FM_LVTS_CKMON_L8			4
#define FM_LVTS_CKMON_L7			5
#define FM_LVTS_CKMON_L6			6
#define FM_LVTS_CKMON_L5			7
#define FM_LVTS_CKMON_L4			8
#define FM_LVTS_CKMON_L3			9
#define FM_LVTS_CKMON_L2			10
#define FM_LVTS_CKMON_L1			11
#define FM_RCLRPLL_DIV4_CHC			16
#define FM_RPHYPLL_DIV4_CHC			17
#define FM_RCLRPLL_DIV4_CHA			24
#define FM_RPHYPLL_DIV4_CHA			25
#define FM_ADSPPLL_CK				28
#define FM_APLL1_CK				29
#define FM_APLL2_CK				30
#define FM_APPLLGP_MON_FM_CK			31
#define FM_UNIVPLL_DIV3_CK			32
#define FM_UNIVPLL_DIV4_CK			33
#define FM_UNIVPLL_DIV5_CK			34
#define FM_UNIVPLL_DIV6_CK			35
#define FM_UNIVPLL_DIV7_CK			36
#define FM_CSI0A_CDPHY_DELAYCAL_CK		37
#define FM_CSI0B_CDPHY_DELAYCAL_CK		38
#define FM_CSI1A_DPHY_DELAYCAL_CK		39
#define FM_CSI1B_DPHY_DELAYCAL_CK		40
#define FM_CSI2A_DPHY_DELAYCAL_CK		41
#define FM_CSI2B_DPHY_DELAYCAL_CK		42
#define FM_CSI3A_DPHY_DELAYCAL_CK		43
#define FM_CSI3B_DPHY_DELAYCAL_CK		44
#define FM_DSI0_LNTC_DSICLK			49
#define FM_DSI0_MPPLL_TST_CK			50
#define FM_MMPLL_D4_CK				51
#define FM_MAINPLL_CK				52
#define FM_MDPLL1_FS26M_GUIDE			53
#define FM_MMPLL_D5_CK				54
#define FM_MMPLL_CK				55
#define FM_MMPLL_D3_CK				56
#define FM_MPLL_CK				57
#define FM_MSDCPLL_CK				58
#define FM_IMGPLL_CK				59
#define FM_EMIPLL_CK				60
#define FM_UFSPLL_CK				61
#define FM_ULPOSC2_MON_V_VCORE_CK		62
#define FM_ULPOSC_MON_VCROE_CK			63
#define FM_UNIVPLL_CK				64
#define FM_UNIVPLL_DIV2_CK			65
#define FM_UNIVPLL_192M_CK			66
#define FM_U_CLK2FREQ				67
#define FM_WBG_DIG_BPLL_CK			68
#define FM_WBG_DIG_WPLL_CK960			69
#define FM_466M_FMEM_INFRASYS			70
#define FM_MCUSYS_ARM_OUT_ALL			71
#define FM_APPLLGP_MON_FM_CK_2			72
#define FM_MMPLL_D6_CK				73
#define FM_MMPLL_D7_CK				74
#define FM_MMPLL_D9_CK				75
#define FM_MAINPLL_DIV3_CK			76
#define FM_MSDC11_IN_CK				77
#define FM_MSDC01_IN_CK				78
#define FM_F32K_VCORE_CK			79
#define FM_MAINPLL_DIV4_CK			80
#define FM_MAINPLL_DIV5_CK			81
#define FM_MAINPLL_DIV6_CK			82
#define FM_MAINPLL_DIV7_CK			83
#define FM_UNIVPLL_DIV3_CK_2			84
#define FM_APLL2_CKDIV_CK			85
#define FM_APLL1_CKDIV_CK			86
#define FM_ADSPPLL_CKDIV_CK			87
#define FM_UFSPLL_CKDIV_CK			88
#define FM_MPLL_CKDIV_CK			89
#define FM_MMPLL_CKDIV_CK			90
#define FM_MAINPLL_CKDIV_CK			91
#define FM_IMGPLL_CKDIV_CK			92
#define FM_EMIPLL_CKDIV_CK			93
#define FM_MSDCPLL_CKDIV_CK			94
#define FM_ABIST_NUM				95
/* VLPCK Part */
#define FM_SCP_VLP_CK				1
#define FM_PWRAP_ULPOSC_CK			2
#define FM_F26M_APXGPT_VLP_CK			3
#define FM_DXCC_VLP_CK				4
#define FM_SPMI_P_CK				5
#define FM_SPMI_M_CK				6
#define FM_DVFSRC_CK				7
#define FM_PWM_VLP_CK				8
#define FM_AXI_VLP_CK				9
#define FM_DBGAO_26M_VLP_CK			10
#define FM_SYSTIMER_26M_VLP_CK			11
#define FM_SSPM_VLP_CK				12
#define FM_SSPM_F26M_CK				13
#define FM_SRCK_CK				14
#define FM_SCP_SPI_CK				15
#define FM_SCP_IIC_CK				16
#define FM_PSVLP_CK				17
#define FM_MD_BUCK_26M_CK			18
#define FM_SSPM_ULPOSC_CK			19
#define FM_CLKRTC				21
#define FM_OSC_2				22
#define FM_OSC_CK				23
#define FM_OSC_CKDIV_CK				26
#define FM_OSC_CKDIV_2				27
#define FM_VLPCK_NUM				28

enum fm_sys_id {
	FM_TOPCKGEN = 0,
	FM_APMIXED = 1,
	FM_VLP_CKSYS = 2,
	FM_MFGPLL = 3,
	FM_MFGSCPLL = 4,
	FM_CCIPLL = 5,
	FM_ARMPLL_LL = 6,
	FM_ARMPLL_BL = 7,
	FM_PTPPLL = 8,
	FM_SYS_NUM = 9,
};

#endif /* _CLK_MT6886_FMETER_H */