// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2022 MediaTek Inc. */ /dts-v1/; #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include / { model = "MT6985"; compatible = "mediatek,MT6985"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; i2c7 = &i2c7; i2c8 = &i2c8; i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; i2c12 = &i2c12; i2c13 = &i2c13; scp_i2c1 = &scp_i2c1; y2r0 = &disp_y2r0; y2r1 = &disp1_y2r0; y2r4 = &ovl_y2r0; y2r5 = &ovl_y2r1; y2r6 = &ovl1_y2r0; y2r7 = &ovl1_y2r1; ovl3 = &disp_ovl0_2l; ovl4 = &disp_ovl1_2l; ovl5 = &disp_ovl2_2l; ovl6 = &disp_ovl3_2l; ovl11 = &disp1_ovl0_2l; ovl12 = &disp1_ovl1_2l; ovl13 = &disp1_ovl2_2l; ovl14 = &disp1_ovl3_2l; rsz0 = &disp_rsz0; rsz2 = &disp1_rsz0; rsz4 = &disp_rsz1; rsz5 = &disp1_rsz1; // mrsz0 = &disp_mdp_rsz0; // mrsz1 = &disp1_mdp_rsz0; mdp-rsz0 = &mdp_rsz6; mdp-rsz1 = &mdp_rsz7; wdma0 = &disp_wdma1; wdma1 = &disp1_wdma1; wdma10 = &disp_wdma0; wdma11 = &disp_wdma2; wdma12 = &disp1_wdma0; wdma13 = &disp1_wdma2; wdma6 = &disp_ufbc_wdma0; wdma7 = &disp_ufbc_wdma1; wdma8 = &disp1_ufbc_wdma0; wdma9 = &disp1_ufbc_wdma1; mdp_rdma0 = &disp_mdp_rdma0; mdp_rdma1 = &disp1_mdp_rdma0; postmask0 = &disp_postmask0; postmask1 = &disp1_postmask0; chist0 = &disp_chist0; chist1 = &disp_chist1; chist2 = &disp1_chist0; chist3 = &disp1_chist1; tdshp0 = &disp_tdshp0_0; tdshp1 = &disp_tdshp0_1; tdshp2 = &disp_tdshp1_0; tdshp3 = &disp_tdshp1_1; color0 = &disp_color0; color1 = &disp_color1; ccorr0 = &disp_ccorr0_0; ccorr1 = &disp_ccorr0_1; ccorr2 = &disp_ccorr1_0; ccorr3 = &disp_ccorr1_1; c3d0 = &disp_c3d0; c3d1 = &disp_c3d1; aal0 = &disp_aal0; aal1 = &disp_aal1; maal0 = &disp_mdp_aal0; maal1 = &disp_mdp_aal1; gamma0 = &disp_gamma0; gamma1 = &disp_gamma1; dither0 = &disp_dither0_0; dither1 = &disp_dither0_1; dither2 = &disp_dither1_0; dither3 = &disp_dither1_1; spr0 = &disp_spr0; spr1 = &disp1_spr0; postalign0 = &disp_postalign0; postalign1 = &disp1_postalign0; oddmr0 = &disp_oddmr0; oddmr1 = &disp1_oddmr0; dsc0 = &disp_dsc_wrap0; dsc1 = &disp1_dsc_wrap0; vdcm0 = &disp_vdcm0; vdcm1 = &disp1_vdcm0; merge0 = &disp_merge0; merge1 = &disp_merge1; merge2 = &disp1_merge0; merge3 = &disp1_merge1; dsi0 = &dsi0; dsi1 = &dsi1; mutex0 = &disp_mutex0; mml-wrot0 = &mml_wrot0; mml-wrot1 = &mml_wrot1; mml-wrot2 = &mml_wrot2; mml-wrot3 = &mml_wrot3; mtksmmu0 = &disp_iommu; mtksmmu1 = &mdp_iommu; mtksmmu2 = &apu_iommu0; mtksmmu3 = &apu_iommu1; inlinerotate0 = &inlinerot0; inlinerotate1 = &inlinerot1; dli-async12 = &ovl_dli_async0; dli-async15 = &ovl1_dli_async0; dlo-async8 = &ovl_dlo_async0; dlo-async15 = &ovl1_dlo_async0; mmlsys-cfg = &mmlsys_config; mml-mutex = &mml_mutex0; }; cache-parity { compatible = "mediatek,mt6985-cache-parity"; ecc-irq-support = <1>; arm_complex_ecc_hwirq = <40 41>; arm_dsu_ecc_hwirq = <48>; interrupts = , /* Core 0 Fault IRQ */ , /* Core 1 Fault IRQ */ , /* Core 2 Fault IRQ */ , /* Core 3 Fault IRQ */ , /* Core 4 Fault IRQ */ , /* Core 5 Fault IRQ */ , /* Core 6 Fault IRQ */ , /* Core 7 Fault IRQ */ , /* Complex 0 Fault IRQ */ , /* Complex 1 Fault IRQ */ ; /* DSU Fault IRQ */ }; /* chosen */ chosen: chosen { mkp,policy=<0x0001fffb>; bootargs = "console=tty0 root=/dev/ram \ rcupdate.rcu_expedited=1 \ swiotlb=noforce disable_dma32=on \ 8250.nr_uarts=4 \ transparent_hugepage=never \ allow_mismatched_32bit_el0 cgroup.memory=nosocket,nokmem \ firmware_class.path=/vendor/firmware"; kaslr-seed = <0 0>; mkp_panic="on"; }; cpus { /*TODO: add cpus node here*/ #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0000>; performance-domains = <&performance 0>; enable-method = "psci"; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <307>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a55"; performance-domains = <&performance 0>; reg = <0x0100>; enable-method = "psci"; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <307>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a55"; performance-domains = <&performance 0>; reg = <0x0200>; enable-method = "psci"; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <307>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a55"; performance-domains = <&performance 0>; reg = <0x0300>; enable-method = "psci"; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <307>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a78"; performance-domains = <&performance 1>; reg = <0x0400>; enable-method = "psci"; cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <785>; }; cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a78"; performance-domains = <&performance 1>; reg = <0x0500>; enable-method = "psci"; cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <785>; }; cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a78"; performance-domains = <&performance 1>; reg = <0x0600>; enable-method = "psci"; cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <785>; }; cpu7: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a78"; performance-domains = <&performance 2>; reg = <0x0700>; enable-method = "psci"; cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff_b &system_mem &system_pll &system_bus &system_vcore &s2idle>; capacity-dmips-mhz = <1024>; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; doe_dvfs_cl0: doe { }; }; cluster1 { core0 { cpu = <&cpu4>; }; core1 { cpu = <&cpu5>; }; core2 { cpu = <&cpu6>; }; doe_dvfs_cl1: doe { }; }; cluster2 { core0 { cpu = <&cpu7>; }; doe_dvfs_cl2: doe { }; }; }; idle-states { entry-method = "arm,psci"; cpuoff_l: cpuoff_l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010000>; local-timer-stop; entry-latency-us = <126>; exit-latency-us = <251>; min-residency-us = <5700>; }; cpuoff_m: cpuoff_m { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010000>; local-timer-stop; entry-latency-us = <77>; exit-latency-us = <179>; min-residency-us = <6840>; }; cpuoff_b: cpuoff_b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010000>; local-timer-stop; entry-latency-us = <52>; exit-latency-us = <129>; min-residency-us = <2770>; }; clusteroff_l: clusteroff_l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; entry-latency-us = <143>; exit-latency-us = <420>; min-residency-us = <5700>; }; clusteroff_m: clusteroff_m { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; entry-latency-us = <82>; exit-latency-us = <253>; min-residency-us = <6840>; }; clusteroff_b: clusteroff_b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; entry-latency-us = <46>; exit-latency-us = <150>; min-residency-us = <3130>; }; mcusysoff_l: mcusysoff_l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x02010007>; local-timer-stop; entry-latency-us = <697>; exit-latency-us = <627>; min-residency-us = <5700>; }; mcusysoff_m: mcusysoff_m { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x02010007>; local-timer-stop; entry-latency-us = <563>; exit-latency-us = <486>; min-residency-us = <6840>; }; mcusysoff_b: mcusysoff_b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x02010007>; local-timer-stop; entry-latency-us = <524>; exit-latency-us = <337>; min-residency-us = <5170>; }; system_mem: system_mem { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0201000f>; local-timer-stop; entry-latency-us = <697>; exit-latency-us = <886>; min-residency-us = <6840>; }; system_pll: system_pll { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0201001f>; local-timer-stop; entry-latency-us = <697>; exit-latency-us = <936>; min-residency-us = <6840>; }; system_bus: system_bus { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0201007f>; local-timer-stop; entry-latency-us = <697>; exit-latency-us = <2686>; min-residency-us = <6840>; }; system_vcore: system_vcore { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x020100ff>; local-timer-stop; entry-latency-us = <940>; exit-latency-us = <3500>; min-residency-us = <35200>; }; s2idle: s2idle { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x020180ff>; local-timer-stop; entry-latency-us = <10000>; exit-latency-us = <10000>; min-residency-us = <4294967295>; }; }; }; /* ATF logger */ atf_logger: atf_logger { compatible = "mediatek,tfa_debug"; }; dramc: dramc@10230000 { compatible = "mediatek,mt6985-dramc", "mediatek,common-dramc"; reg = <0 0x10250000 0 0x2000>, /* DRAMC AO CHA */ <0 0x10260000 0 0x2000>, /* DRAMC AO CHB */ <0 0x10230000 0 0x2000>, /* DRAMC AO CHC */ <0 0x10240000 0 0x2000>, /* DRAMC AO CHD */ <0 0x10254000 0 0x1000>, /* DRAMC NAO CHA */ <0 0x10264000 0 0x1000>, /* DRAMC NAO CHB */ <0 0x10234000 0 0x1000>, /* DRAMC NAO CHC */ <0 0x10244000 0 0x1000>, /* DRAMC NAO CHD */ <0 0x10258000 0 0x2000>, /* DDRPHY AO CHA */ <0 0x10268000 0 0x2000>, /* DDRPHY AO CHB */ <0 0x10238000 0 0x2000>, /* DDRPHY AO CHC */ <0 0x10248000 0 0x2000>, /* DDRPHY AO CHD */ <0 0x10256000 0 0x2000>, /* DDRPHY NAO CHA */ <0 0x10266000 0 0x2000>, /* DDRPHY NAO CHB */ <0 0x10236000 0 0x2000>, /* DDRPHY NAO CHC */ <0 0x10246000 0 0x2000>, /* DDRPHY NAO CHD */ <0 0x10006000 0 0x1000>; /* SLEEP BASE */ mr4_version = <0>; mr4_rg = <0x0090 0x0000ffff 0>; fmeter_version = <2>; crystal_freq = <26>; pll_id = <0x0CB4 0x00000100 8>; shu_lv = <0x0CB4 0x00030000 16>; shu_of = <0x700>; sdmpcw = <0x0908 0x0007FFF8 3>, <0x0928 0x0007FFF8 3>; prediv = <0x090c 0x0000fffc 14>, <0x092c 0x0000fffc 14>; posdiv = <0x090c 0x00003800 11>, <0x092c 0x00003800 11>; ckdiv4 = <0x13ec 0x00000004 2>, <0x13ec 0x00000004 2>; pll_md = <0x0944 0x00000100 8>, <0x0944 0x00000100 8>; cldiv2 = <0x0f34 0x00000002 1>, <0x0f34 0x00000002 1>; fbksel = <0x0910 0x00000020 5>, <0x0910 0x00000020 5>; dqsopen = <0x0D94 0x02000000 25>, <0x0D94 0x02000000 25>; dqopen = <0x0D94 0x0001fffe 21>, <0x0D94 0x0001fffe 21>; ckdiv4_ca = <0x136c 0x00000004 2>, <0x136c 0x00000004 2>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; lastbus: lastbus { compatible = "mediatek,lastbus"; enabled = <1>; sw_version = <1>; timeout_ms = <200>; timeout_type = <0>; monitors { monitor1 { monitor_name = "debug_ctrl_ao_INFRA_AO"; base = <0x10023000>; num_ports = <39>; bus_freq_mhz = <78>; }; monitor2 { monitor_name = "debug_ctrl_ao_INFRA_AO1"; base = <0x1002b000>; num_ports = <60>; idle_masks = <0x1c 0x800000>; bus_freq_mhz = <78>; }; monitor3 { monitor_name = "debug_ctrl_ao_NEMI_AO"; base = <0x10042000>; num_ports = <20>; idle_masks = <0xc 0xffff8000>, <0x10 0x3fff>; bus_freq_mhz = <625>; }; monitor4 { monitor_name = "debug_ctrl_ao_SEMI_AO"; base = <0x10028000>; num_ports = <20>; idle_masks = <0xc 0xffff8000>, <0x10 0x3fff>; bus_freq_mhz = <625>; }; monitor5 { monitor_name = "debug_ctrl_ao_PERI_PAR_AO"; base = <0x11037000>; num_ports = <22>; bus_freq_mhz = <78>; }; monitor6 { monitor_name = "debug_ctrl_ao_VLP_AO"; base = <0x1c01d000>; num_ports = <14>; bus_freq_mhz = <156>; }; monitor7 { monitor_name = "debug_ctrl_ao_MM_AO"; base = <0x1e825000>; num_ports = <25>; bus_freq_mhz = <688>; }; }; }; memory { device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; firmware: firmware { scmi: scmi { compatible = "arm,scmi"; mboxes = <&tinysys_mbox 0>, <&tinysys_mbox 1>; shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>; mbox-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; scmi_tinysys: protocol@80 { reg = <0x80>; scmi-qos = <1>; scmi_dispplatdbg = <2>; scmi-met = <3>; scmi-apmcupm = <4>; scmi-mminfra = <5>; scmi-gpupm = <6>; scmi-plt = <7>; scmi_smi = <8>; scmi-cm = <9>; scmi-slbc = <10>; scmi_ssc = <11>; }; }; }; reserved-memory { /*TODO: add reserved memory node here*/ #address-cells = <2>; #size-cells = <2>; ranges; ssmr_cma_mem: ssmr-reserved-cma_memory { compatible = "shared-dma-pool"; reusable; size = <0 0x10000000>; alignment = <0 0x1000000>; }; ssheap_cma_mem: ssheap-reserved-cma_memory { compatible = "shared-dma-pool"; reusable; size = <0 0x10000000>; alignment = <0 0x200000>; }; mkp_mem: mkp-kernel-code-protection-memory { compatible = "mkp-kernel-protection"; size = <0 0x10000>; alloc-ranges = <0 0x40000000 0 0x10000>; }; dpmaif_resv_cache_mem: ccci_dpmaif_cache-memory { compatible = "mediatek,dpmaif-resv-cache-mem"; size = <0 0x00210000>; /* 2162688 Bytes for 2rxq */ alignment = <0 0x1000>; alloc-ranges = <0 0x40000000 0 0xF0000000>; }; dpmaif_resv_nocache_mem: ccci_dpmaif_nocache-memory { compatible = "mediatek,dpmaif-resv-nocache-mem"; no-map; size = <0 0x0050000>; /* 327680 Bytes */ alignment = <0 0x1000>; alloc-ranges = <0 0x40000000 0 0xF0000000>; }; }; memory_ssmr_features: memory-ssmr-features { compatible = "mediatek,memory-ssmr-features"; svp-region-based-size = <0 0x6000000>; svp-page-based-size = <0 0x38000000>; tui-size = <0 0x4000000>; wfd-region-based-size = <0 0x4000000>; wfd-page-based-size = <0 0x4000000>; prot-region-based-size = <0 0x8000000>; prot-page-based-size = <0 0>; sapu-data-shm-size = <0 0x1000000>; }; ssmr { compatible = "mediatek,trusted_mem"; memory-region = <&ssmr_cma_mem>; }; ssheap { compatible = "mediatek,trusted_mem_ssheap"; memory-region = <&ssheap_cma_mem>; }; drm_wv: drm_wv { compatible = "mediatek,drm_wv"; status = "okay"; }; mtee_svp: mtee_svp { compatible = "medaitek,svp"; }; aod_scp: aod_scp { compatible = "medaitek,aod_scp"; dsi0 = <&dsi0 0x1000>; dsc0 = <&disp_dsc_wrap0 0x1000>; mipitx0 = <&mipi_tx_config0 0x1000>; }; qos:qos@11bb00 { compatible = "mediatek,mt6893-qos"; reg = <0 0x0011bb00 0 0x100>, <0 0x0011b9C0 0 0x140>; reg-names = "sram", "share_sram"; mediatek,enable = <1>; }; cm_mgr: cm-mgr@c100000 { compatible = "mediatek,mt6985-cm_mgr"; reg = <0 0xc100000 0 0x9000>; reg-names = "cm_mgr_base"; interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "cm-perf-bw"; required-opps = <&dvfsrc_freq_opp0>, <&dvfsrc_freq_opp1>, <&dvfsrc_freq_opp2>, <&dvfsrc_freq_opp3>, <&dvfsrc_freq_opp4>, <&dvfsrc_freq_opp5>, <&dvfsrc_freq_opp7>, <&dvfsrc_freq_opp8>; cm-mgr,cp-down = <100 100 100 100 100 100 100>; cm-mgr,cp-up = <100 100 100 100 100 100 100>; cm-mgr,dt-down = <0 0 0 0 0 0 0>; cm-mgr,dt-up = <0 0 0 0 0 0 0>; cm-mgr,vp-down = <100 100 100 100 100 100 100>; cm-mgr,vp-up = <100 100 100 100 100 100 100>; use-cpu-to-dram-map = "enable"; cm-mgr-cpu-opp-to-dram = <1 1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8>; use-bcpu-weight = "enable"; cpu-power-bcpu-weight-max = <100>; cpu-power-bcpu-weight-min = <100>; cpu-power-bbcpu-weight-max = <100>; cpu-power-bbcpu-weight-min = <100>; use-cpu-to-dram-map-new = "enable"; }; fpsgo: fpsgo { compatible = "mediatek,fpsgo"; interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "fpsgo-perf-bw"; required-opps = <&dvfsrc_freq_opp1>; cpu_limit = <2>; gcc_enable = <1>; fbt_cpu_mask = <255 128 15 127 240 112>; sbe_resceue_enable = <1>; }; mcupm: mcupm@0c070000 { compatible = "mediatek,mcupm"; reg = <0 0x0c070000 0 0x50000>, <0 0x0c0bfb00 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>, <0 0x0c0bfba0 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>, <0 0x0c0bfc40 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>, <0 0x0c0bfce0 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>, <0 0x0c0bfd80 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>, <0 0x0c0bfe20 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>, <0 0x0c0bfec0 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>, <0 0x0c0bff60 0 0xa0>, <0 0x0c072004 0 0x4>, <0 0x0c072018 0 0x4>, <0 0x0c072000 0 0x4>, <0 0x0c072010 0 0x4>; reg-names = "mcupm_base", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_send", "mbox0_recv", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_send", "mbox1_recv", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_send", "mbox2_recv", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_send", "mbox3_recv", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_send", "mbox4_recv", "mbox5_base", "mbox5_set", "mbox5_clr", "mbox5_send", "mbox5_recv", "mbox6_base", "mbox6_set", "mbox6_clr", "mbox6_send", "mbox6_recv", "mbox7_base", "mbox7_set", "mbox7_clr", "mbox7_send", "mbox7_recv"; interrupts = , , , , , , , ; interrupt-names = "mbox0", "mbox1", "mbox2", "mbox3", "mbox4", "mbox5", "mbox6", "mbox7"; }; cpuqos_v3: cpuqos-v3@113400 { compatible = "mediatek,cpuqos-v3"; reg = <0 0x00113400 0 0x400>; enable = <1>; }; sspm: sspm@1c340000 { compatible = "mediatek,sspm"; reg = <0 0x1c300000 0 0x30000>, <0 0x1c340000 0 0x10000>, <0 0x1c380000 0 0x80>; reg-names = "sspm_base", "cfgreg", "mbox_share"; interrupts = ; interrupt-names = "ipc"; sspm_res_ram_start = <0x0>; sspm_res_ram_size = <0x110000>; /* 1M + 64K */ }; teeperf { compatible = "mediatek,teeperf"; cpu-type = <1>; /* 1: CPU_V9_TYPE, 2: CPU_V8_TYPE */ cpu-map = <1>; /* 1: CPU_4_3_1_MAP, 2: CPU_6_2_MAP */ }; /* Trustonic Mobicore SW IRQ number 144 = 32 + 112 */ mobicore: mobicore { compatible = "trustonic,mobicore"; interrupts = ; }; /* Microtrust SW IRQ number 114(146 - 32) ~ 115(147 - 32) */ utos: utos { compatible = "microtrust,utos"; interrupts = ; }; utos_tester { compatible = "microtrust,tester-v1"; }; ssram1@1c350000 { compatible = "mmio-sram_1"; reg = <0x0 0x1c350000 0x0 0x80>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x1c350000 0x80>; scmi_tx_shmem: tiny_mbox@0 { compatible = "arm,scmi-shmem"; reg = <0x0 0x80>; }; }; ssram2@1c360000 { compatible = "mmio-sram_2"; reg = <0x0 0x1c360000 0x0 0x80>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x1c360000 0x80>; scmi_rx_shmem: tiny_mbox@1 { compatible = "arm,scmi-shmem"; reg = <0x0 0x80>; }; }; tinysys_mbox: tinysys_mbox@1c351000 { compatible = "mediatek,tinysys_mbox"; reg = <0 0x1c351000 0 0x1000>, <0 0x1c361000 0 0x1000>; /* for profiling */ shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>; interrupts = , ; #mbox-cells = <1>; }; gic: interrupt-controller { compatible = "arm,gic-v3"; #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; #redistributor-regions = <1>; interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x0c400000 0 0x40000>, // distributor <0 0x0c440000 0 0x200000>; // redistributor interrupts = ; ppi-partitions { ppi_cluster0: interrupt-partition-0 { affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; }; ppi_cluster1: interrupt-partition-1 { affinity = <&cpu4 &cpu5 &cpu6>; }; ppi_cluster2: interrupt-partition-2 { affinity = <&cpu7>; }; }; }; bus_parity { compatible = "mediatek,bus-parity"; reg = <0 0x0c000900 0 0x20>, /* MST_EMI0_CH0 */ <0 0x0c000920 0 0x20>, /* MST_EMI0_CH1 */ <0 0x0c000940 0 0x20>, /* MST_EMI1_CH0 */ <0 0x0c000960 0 0x20>, /* MST_EMI1_CH1 */ <0 0x0c000980 0 0x20>, /* MST_INFRA */ <0 0x0c0009a0 0 0x30>, /* SLV_L3GIC */ <0 0x10270600 0 0x20>, /* MCU2EMI_M0 */ <0 0x10270620 0 0x20>, /* MCU2EMI_M1 */ <0 0x1030e600 0 0x20>, /* MCU2SUBEMI_M0 */ <0 0x1030e620 0 0x20>, /* MCU2SUBEMI_M1 */ <0 0x100017a8 0 0x14>, /* MCU2IFR_REG */ <0 0x100017bc 0 0x8>, /* INF_L3C2MCU */ <0 0x0c0009dc 0 0x4>; /* BUS_PARITY_FAIL */ interrupts = , /* MCU */ ; /* Infra */ interrupt-names = "mcu-bus-parity", "infra-bus-parity"; mcu-names = "MST_EMI0_CH0", "MST_EMI0_CH1", "MST_EMI1_CH0", "MST_EMI1_CH1", "MST_INFRA", "SLV_L3GIC"; infra-names = "MCU2EMI_M0", "MCU2EMI_M1", "MCU2SUBEMI_M0", "MCU2SUBEMI_M1", "MCU2IFR", "INF_L3C2MCU"; /* 0:master, 1:slave, 2:emi */ mcu-types = <0 0 0 0 0 1>; infra-types = <2 2 2 2 1 0>; /* offset of MST_XXX_LOG_RD0/SLV_XXX_LOG_WD0 for mcu bpm */ mcu-rd0wd0-offset = <0x0c 0x0c 0x0c 0x0c 0x0c 0x24>; /* shift of parity fail bit in BUS_PARITY_FAIL for mcu bpm */ mcu-fail-bit-shift = <0 1 2 3 4 5>; mcu-data-len = <4 4 4 4 4 2>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , , , ; clock-frequency = <13000000>; }; hwrng: hwrng { compatible = "arm,sec-rng"; methods = "smc"; method-fid = /bits/ 16 <0x26a>; quality = /bits/ 16 <900>; }; clk_ao: clk_ao { compatible = "simple-bus"; }; clkitg: clkitg { compatible = "simple-bus"; }; disable_unused: disable_unused { compatible = "simple-bus"; }; clkchk { compatible = "mediatek,mt6985-clkchk"; interrupts = ; interrupt-names = "hwv_irq"; }; pdchk { compatible = "mediatek,mt6985-pdchk"; interrupts = ; interrupt-names = "hwv_irq"; }; clocks { clk_null: clk_null { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; clk32k: clk32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; clk26m: clk26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clk13m: clk13m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <13000000>; }; ulposc: ulposc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <520000000>; }; clk10m: clk10m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <10000000>; }; clk104m: clk104m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <104000000>; }; }; pmu-a715 { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = ; }; pmu-x3 { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = ; }; pmu-a510 { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = ; }; dsu-pmu-0 { compatible = "arm,dsu-pmu"; interrupts = ; cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; cpuhvfs: cpuhvfs@114400 { compatible = "mediatek,cpufreq-hybrid"; reg = <0 0x00114400 0 0xc00>, <0 0x0011bc00 0 0x1400>, <0 0x00118000 0 0x800>, <0 0x00114f40 0 0xc0>; reg-names = "USRAM", "CSRAM", "ESRAM"; cslog-range = <0x03d0>, <0x0fa0>; tbl-off = <4>, <76>, <148>, <220>; /* pll mcucfg */ mcucfg-ver = <0>; apmixedsys = <&cpu_pll>; clk-div-base = <&cpu_mcucfg>; pll-con = <0x40c>, <0x80c>, <0xc0c>, <0x00c>; clk-div = <0x10c>, <0x118>, <0x124>, <0x100>; /* regulator */ proc1-supply = <&mt6373_vbuck9>; //L proc2-supply = <&mt6319_7_vbuck1>; //M proc3-supply = <&mt6319_6_vbuck1>; //B proc4-supply = <&mt6373_vbuck9>; //DSU /* leakage info */ nvmem-cells = <&lkginfo>; nvmem-cell-names = "lkginfo"; }; hwv: syscon@10320000 { compatible = "mediatek,mt6985-hwv", "syscon"; reg = <0 0x10320000 0 0x2000>; }; topckgen_clk: syscon@10000000 { compatible = "mediatek,mt6985-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; infracfg_ao_clk: syscon@10001000 { compatible = "mediatek,mt6985-infracfg_ao", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; }; apmixedsys_clk: syscon@1000c000 { compatible = "mediatek,mt6985-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; ifr_bus: syscon@1002c000 { compatible = "mediatek,mt6985-ifr_bus", "syscon"; reg = <0 0x1002c000 0 0x1000>; }; ifr_mem_bus: syscon@10270000 { compatible = "mediatek,mt6985-ifr_mem_bus", "syscon"; reg = <0 0x10270000 0 0x1000>; }; semi_bus: syscon@1030e000 { compatible = "mediatek,mt6985-semi_bus", "syscon"; reg = <0 0x1030e000 0 0x1000>; }; ssr_top_clk: syscon@10400000 { compatible = "mediatek,mt6985-ssr_top", "syscon"; reg = <0 0x10400000 0 0x1000>; #clock-cells = <1>; }; pericfg_ao_clk: syscon@11036000 { compatible = "mediatek,mt6985-pericfg_ao", "syscon"; reg = <0 0x11036000 0 0x1000>; #clock-cells = <1>; }; afe_clk: syscon@11050000 { compatible = "mediatek,mt6985-audiosys", "syscon"; reg = <0 0x11050000 0 0x1000>; #clock-cells = <1>; }; imp_iic_wrap_c_clk: syscon@11281000 { compatible = "mediatek,mt6985-imp_iic_wrap_c", "syscon"; reg = <0 0x11281000 0 0x1000>; #clock-cells = <1>; }; ufscfg_ao_clk: syscon@112b8000 { compatible = "mediatek,mt6985-ufscfg_ao", "syscon", "simple-mfd"; reg = <0 0x112b8000 0 0x1000>; #clock-cells = <1>; ufscfgao_rst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < /* ufs unipro reset */ 0x48 8 0x4c 8 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: unipro */ /* ufs mphy reset */ 0x48 9 0x4c 9 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: mphy */ >; }; }; ufscfg_pdn_clk: syscon@112bb000 { compatible = "mediatek,mt6985-ufscfg_pdn", "syscon", "simple-mfd"; reg = <0 0x112bb000 0 0x1000>; #clock-cells = <1>; ufscfgpdn_rst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < /* ufs crypto/ufshci reset */ /* 0: ufs-crypto */ 0x48 0 0x4c 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: ufshci */ 0x48 1 0x4c 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) >; }; }; pextpcfg_ao_clk: syscon@112e0000 { compatible = "mediatek,mt6985-pextpcfg_ao", "syscon"; reg = <0 0x112e0000 0 0x1000>; #clock-cells = <1>; }; imp_iic_wrap_s_clk: syscon@11d07000 { compatible = "mediatek,mt6985-imp_iic_wrap_s", "syscon"; reg = <0 0x11d07000 0 0x1000>; #clock-cells = <1>; }; imp_iic_wrap_n_clk: syscon@11f06000 { compatible = "mediatek,mt6985-imp_iic_wrap_n", "syscon"; reg = <0 0x11f06000 0 0x1000>; #clock-cells = <1>; }; gpusys: power-controller@13f91000 { compatible = "mediatek,mt6985-gpusys", "syscon"; reg = <0 0x13f91000 0 0x1000>; #power-domain-cells = <1>; clocks = <&topckgen_clk CLK_TOP_MFG_REF_SEL>, <&topckgen_clk CLK_TOP_MFGSC_REF_SEL>; clock-names = "mfg_ref", "mfgsc_ref"; ifr_bus = <&ifr_bus>; ufscfg_ao_bus = <&ufscfg_ao_clk>; gpu_eb_rpc = <&gpusys>; img_sub0_bus = <&img_sub0_bus>; img_sub1_bus = <&img_sub1_bus>; cam_sub0_bus = <&cam_sub0_bus>; cam_sub2_bus = <&cam_sub2_bus>; cam_sub1_bus = <&cam_sub1_bus>; vlpcfg = <&vlpcfg_bus>; }; mfgpll_pll_ctrl_clk: syscon@13fa0000 { compatible = "mediatek,mt6985-mfgpll_pll_ctrl", "syscon"; reg = <0 0x13fa0000 0 0x0C00>; #clock-cells = <1>; }; mfgscpll_pll_ctrl_clk: syscon@13fa0c00 { compatible = "mediatek,mt6985-mfgscpll_pll_ctrl", "syscon"; reg = <0 0x13fa0c00 0 0x1000>; #clock-cells = <1>; }; dispsys_config_clk: syscon@14000000 { compatible = "mediatek,mt6985-mmsys0", "syscon"; reg = <0 0x14000000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; dispsys1_config_clk: syscon@14200000 { compatible = "mediatek,mt6985-mmsys1", "syscon"; reg = <0 0x14200000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; ovlsys_config_clk: syscon@14400000 { compatible = "mediatek,mt6985-ovlsys_config", "syscon"; reg = <0 0x14400000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; ovlsys1_config_clk: syscon@14600000 { compatible = "mediatek,mt6985-ovlsys1_config", "syscon"; reg = <0 0x14600000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; imgsys_main_clk: syscon@15000000 { compatible = "mediatek,mt6985-imgsys_main", "syscon"; reg = <0 0x15000000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; img_sub0_bus: syscon@15002000 { compatible = "mediatek,mt6985-img_sub0_bus", "syscon"; reg = <0 0x15002000 0 0x1000>; }; img_sub1_bus: syscon@15003000 { compatible = "mediatek,mt6985-img_sub1_bus", "syscon"; reg = <0 0x15003000 0 0x1000>; }; dip_top_dip1_clk: syscon@15110000 { compatible = "mediatek,mt6985-dip_top_dip1", "syscon"; reg = <0 0x15110000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; dip_nr1_dip1_clk: syscon@15130000 { compatible = "mediatek,mt6985-dip_nr1_dip1", "syscon"; reg = <0 0x15130000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; dip_nr2_dip1_clk: syscon@15170000 { compatible = "mediatek,mt6985-dip_nr2_dip1", "syscon"; reg = <0 0x15170000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; wpe1_dip1_clk: syscon@15220000 { compatible = "mediatek,mt6985-wpe1_dip1", "syscon"; reg = <0 0x15220000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; wpe2_dip1_clk: syscon@15520000 { compatible = "mediatek,mt6985-wpe2_dip1", "syscon"; reg = <0 0x15520000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; wpe3_dip1_clk: syscon@15620000 { compatible = "mediatek,mt6985-wpe3_dip1", "syscon"; reg = <0 0x15620000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; traw_dip1_clk: syscon@15710000 { compatible = "mediatek,mt6985-traw_dip1", "syscon"; reg = <0 0x15710000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; vdec_soc_gcon_base_clk: syscon@1600f000 { compatible = "mediatek,mt6985-vdecsys_soc", "syscon"; reg = <0 0x1600f000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; vdec_gcon_base_clk: syscon@1602f000 { compatible = "mediatek,mt6985-vdecsys", "syscon"; reg = <0 0x1602f000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; venc_gcon_clk: syscon@17000000 { compatible = "mediatek,mt6985-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; }; venc_gcon_core1_clk: syscon@17800000 { compatible = "mediatek,mt6985-vencsys_c1", "syscon"; reg = <0 0x17800000 0 0x1000>; #clock-cells = <1>; }; venc_gcon_core2_clk: syscon@17c00000 { compatible = "mediatek,mt6985-vencsys_c2", "syscon"; reg = <0 0x17c00000 0 0x1000>; #clock-cells = <1>; }; cam_sub0_bus: syscon@1a005000 { compatible = "mediatek,mt6985-cam_sub0_bus", "syscon"; reg = <0 0x1a005000 0 0x1000>; }; cam_sub2_bus: syscon@1a006000 { compatible = "mediatek,mt6985-cam_sub2_bus", "syscon"; reg = <0 0x1a006000 0 0x1000>; }; cam_sub1_bus: syscon@1a007000 { compatible = "mediatek,mt6985-cam_sub1_bus", "syscon"; reg = <0 0x1a007000 0 0x1000>; }; touch: touch { compatible = "mediatek,touch"; }; scpsys: power-controller@1c001000 { compatible = "mediatek,mt6985-scpsys", "syscon"; reg = <0 0x1c001000 0 0x1000>; #power-domain-cells = <1>; clocks = <&topckgen_clk CLK_TOP_ADSP_SEL>, <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>, <&topckgen_clk CLK_TOP_AUDIO_LOCAL_BUS_SEL>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CCUSYS_SEL>, <&topckgen_clk CLK_TOP_CCU_AHB_SEL>, <&topckgen_clk CLK_TOP_DISP0_SEL>, <&topckgen_clk CLK_TOP_DISP1_SEL>, <&topckgen_clk CLK_TOP_MDP0_SEL>, <&topckgen_clk CLK_TOP_MDP1_SEL>, <&topckgen_clk CLK_TOP_OVL0_SEL>, <&topckgen_clk CLK_TOP_OVL1_SEL>, <&topckgen_clk CLK_TOP_MMINFRA_SEL>, <&topckgen_clk CLK_TOP_MMUP_SEL>, <&topckgen_clk CLK_TOP_IMG1_SEL>, <&topckgen_clk CLK_TOP_VDEC_SEL>, <&topckgen_clk CLK_TOP_VENC_SEL>, <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CCUSYS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2SYS_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM2_GALS_CON_0>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&mdpsys_config_clk CLK_MDP_SMI0>, <&mdpsys1_config_clk CLK_MDP1_SMI0>, <&imgsys_main_clk CLK_IMG_LARB9>, <&imgsys_main_clk CLK_IMG_SMI_ADL_LARB0>, <&vdec_soc_gcon_base_clk CLK_VDE1_LARB1_CKEN>, <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>, <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBA_CON_0>, <&camsys_rawa_clk CLK_CAM_RA_LARBX>, <&camsys_yuva_clk CLK_CAM_YA_LARBX>, <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBB_CON_0>, <&camsys_rawb_clk CLK_CAM_RB_LARBX>, <&camsys_yuvb_clk CLK_CAM_YB_LARBX>, <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBC_CON_0>, <&camsys_rawc_clk CLK_CAM_RC_LARBX>, <&camsys_yuvc_clk CLK_CAM_YC_LARBX>, <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&imgsys_main_clk CLK_IMG_DIP0>, <&imgsys_main_clk CLK_IMG_WPE0>, <&imgsys_main_clk CLK_IMG_WPE1>, <&imgsys_main_clk CLK_IMG_WPE2>, <&imgsys_main_clk CLK_IMG_TRAW0>, <&imgsys_main_clk CLK_IMG_IPE>, <&pextpcfg_ao_clk CLK_PEXT_MAC0_26M>, <&pextpcfg_ao_clk CLK_PEXT_MAC1_26M>, <&pericfg_ao_clk CLK_PERAO_AUDIO_SLV>; clock-names = "adsp", "audio", "aud_bus", "cam", "ccu", "ccu_ahb", "disp", "disp1", "mdp", "mdp1", "ovl", "ovl1", "mm_infra", "mmup", "isp", "vde", "ven", "cam-0", "cam-1", "cam-2", "cam-3", "cam-4", "cam-5", "cam_lp-0", "cam_lp-1", "cam_lp-2", "cam_lp-3", "mm_infra_lp-0", "disp-0", "disp1-0", "ovl-0", "ovl1-0", "mdp-0", "mdp1-0", "isp_lp-0", "isp_lp-1", "vde0-0", "vde1-0", "cam_suba-0", "cam_suba-1", "cam_suba-2", "cam_subb-0", "cam_subb-1", "cam_subb-2", "cam_subc-0", "cam_subc-1", "cam_subc-2", "cam_mraw-0", "cam_mraw-1", "dip1_lp-0", "dip1_lp-1", "dip1_lp-2", "dip1_lp-3", "dip1_lp-4", "dip1_lp-5", "pextp0-0", "pextp1-0", "audio-0"; ifr_bus = <&ifr_bus>; ifr_mem_bus = <&ifr_mem_bus>; ufscfg_ao_bus = <&ufscfg_ao_clk>; gpu_eb_rpc = <&gpusys>; img_sub0_bus = <&img_sub0_bus>; img_sub1_bus = <&img_sub1_bus>; cam_sub0_bus = <&cam_sub0_bus>; cam_sub2_bus = <&cam_sub2_bus>; cam_sub1_bus = <&cam_sub1_bus>; vlpcfg = <&vlpcfg_bus>; semi_bus = <&semi_bus>; hw-voter-regmap = <&hwv>; }; watchdog: watchdog@1C007000 { compatible = "mediatek,mt6985-wdt", "mediatek,mt6589-wdt", "syscon", "simple-mfd"; reg = <0 0x1c007000 0 0x100>; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x24>; mask = <0xf>; mode-charger = ; mode-recovery = ; mode-bootloader = ; mode-dm-verity-dev-corrupt = ; mode-kpoc = ; mode-ddr-reserve = ; mode-meta = ; mode-rpmbpk = ; }; }; vlpcfg_bus: syscon@1c00c000 { compatible = "mediatek,mt6985-vlpcfg_bus", "syscon"; reg = <0 0x1c00c000 0 0x1000>; }; masp: masp@1c009000 { compatible = "mediatek,masp"; reg = <0 0x1c009000 0 0x1000>; interrupts = ; /* GIC_IRQ ID(sej_axgpt_irq) - 32 = 359 - 32 = 327 */ }; security_ao@1c00b000 { compatible = "mediatek,security_ao"; reg = <0 0x1c00b000 0 0x1000>; }; systimer: systimer@1C011000 { compatible = "mediatek,mt6985-timer", "mediatek,mt6765-timer"; reg = <0 0x1c011000 0 0x1000>; interrupts = ; clocks = <&clk13m>; }; vlp_cksys_clk: syscon@1c013000 { compatible = "mediatek,mt6985-vlp_cksys", "syscon"; reg = <0 0x1c013000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; scp_clk: syscon@1c721000 { compatible = "mediatek,mt6985-scp", "syscon"; reg = <0 0x1c721000 0 0x1000>; #clock-cells = <1>; }; scp_iic_clk: syscon@1c7b8000 { compatible = "mediatek,mt6985-scp_iic", "syscon"; reg = <0 0x1c7b8000 0 0x1000>; #clock-cells = <1>; }; camsys_main_clk: syscon@1a000000 { compatible = "mediatek,mt6985-camsys_main", "syscon"; reg = <0 0x1a000000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; camsys_rawa_clk: syscon@1a04f000 { compatible = "mediatek,mt6985-camsys_rawa", "syscon"; reg = <0 0x1a04f000 0 0x1000>; #clock-cells = <1>; }; camsys_yuva_clk: syscon@1a06f000 { compatible = "mediatek,mt6985-camsys_yuva", "syscon"; reg = <0 0x1a06f000 0 0x1000>; #clock-cells = <1>; }; camsys_rawb_clk: syscon@1a08f000 { compatible = "mediatek,mt6985-camsys_rawb", "syscon"; reg = <0 0x1a08f000 0 0x1000>; #clock-cells = <1>; }; camsys_yuvb_clk: syscon@1a0af000 { compatible = "mediatek,mt6985-camsys_yuvb", "syscon"; reg = <0 0x1a0af000 0 0x1000>; #clock-cells = <1>; }; camsys_rawc_clk: syscon@1a0cf000 { compatible = "mediatek,mt6985-camsys_rawc", "syscon"; reg = <0 0x1a0cf000 0 0x1000>; #clock-cells = <1>; }; camsys_yuvc_clk: syscon@1a0ef000 { compatible = "mediatek,mt6985-camsys_yuvc", "syscon"; reg = <0 0x1a0ef000 0 0x1000>; #clock-cells = <1>; }; camsys_mraw_clk: syscon@1a170000 { compatible = "mediatek,mt6985-camsys_mraw", "syscon"; reg = <0 0x1a170000 0 0x1000>; #clock-cells = <1>; }; pda: pda@1a180000 { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek,camera-pda"; reg = <0 0x1a180000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; interrupts = ; clocks = <&camsys_mraw_clk CLK_CAM_MR_PDA0>, <&camsys_mraw_clk CLK_CAM_MR_PDA1>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>; clock-names = "camsys_mraw_pda0", "camsys_mraw_pda1", "mraw_larbx", "cam_main_cam2mm0_gals_cg_con", "cam_main_cam2mm1_gals_cg_con", "cam_main_cam_cg_con"; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; mediatek,pda2 = <&pda2>; mediatek,larbs = <&smi_larb25>; iommus = <&disp_iommu M4U_PORT_L25_PDAI_A_0>, <&disp_iommu M4U_PORT_L25_PDAI_A_1>, <&disp_iommu M4U_PORT_L25_PDAI_A_2>, <&disp_iommu M4U_PORT_L25_PDAI_A_3>, <&disp_iommu M4U_PORT_L25_PDAI_A_4>, <&disp_iommu M4U_PORT_L25_PDAO_A_0>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_3) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAI_A_4) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_PDAO_A_0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_0) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_2) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_3) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_PDAI_B_4) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_PDAO_B_0) &mmqos SLAVE_COMMON(1)>; interconnect-names = "l25_pdai_a0", "l25_pdai_a1", "l25_pdai_a2", "l25_pdai_a3", "l25_pdai_a4", "l25_pdao_a", "l26_pdai_b0", "l26_pdai_b1", "l26_pdai_b2", "l26_pdai_b3", "l26_pdai_b4", "l26_pdao_b"; }; pda2: pda2@1a181000 { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek,camera-pda2"; reg = <0 0x1a181000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; interrupts = ; clocks = <&camsys_mraw_clk CLK_CAM_MR_PDA0>, <&camsys_mraw_clk CLK_CAM_MR_PDA1>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>; clock-names = "camsys_mraw_pda0", "camsys_mraw_pda1", "mraw_larbx", "cam_main_cam2mm0_gals_cg_con", "cam_main_cam2mm1_gals_cg_con", "cam_main_cam_cg_con"; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; mediatek,larbs = <&smi_larb26>; iommus = <&mdp_iommu M4U_PORT_L26_PDAI_B_0>, <&mdp_iommu M4U_PORT_L26_PDAI_B_1>, <&mdp_iommu M4U_PORT_L26_PDAI_B_2>, <&mdp_iommu M4U_PORT_L26_PDAI_B_3>, <&mdp_iommu M4U_PORT_L26_PDAI_B_4>, <&mdp_iommu M4U_PORT_L26_PDAO_B_0>; }; camera-fsync-ccu { compatible = "mediatek,camera-fsync-ccu"; mediatek,ccu-rproc = <&ccu_rproc>; }; camera-camsys-ccu { compatible = "mediatek,camera-camsys-ccu"; mediatek,ccu-rproc = <&ccu_rproc>; }; ccu_rproc: ccu_rproc@1b080000 { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek,ccu_rproc"; reg = <0 0x1b080000 0 0x9000>; interrupts = ; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>, <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; mediatek,larbs = <&smi_larb19>; clocks = <&topckgen_clk CLK_TOP_CCUSYS>, <&topckgen_clk CLK_TOP_CCU_AHB>, <&ccu_main_clk CLK_CCU_LARB19>, <&ccu_main_clk CLK_CCU_AHB>, <&ccu_main_clk CLK_CCUSYS_CCU0>, <&camsys_main_clk CLK_CAM_MAIN_CCUSYS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2SYS_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>; clock-names = "CLK_TOP_CCUSYS_SEL", "CLK_TOP_CCU_AHB_SEL", "CLK_CCU_LARB", "CLK_CCU_AHB", "CLK_CCUSYS_CCU0", "CAM_CCUSYS", "CAM_CAM2SYS_GALS", "CAM_CAM2MM1_GALS", "CAM_CAM2MM0_GALS", "CAM_MRAW", "CAM_CG"; mediatek,ccu_rproc1 = <&ccu_rproc1>; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L19_CCUO>, <&disp_iommu M4U_PORT_L19_CCUI>; interconnects = <&mmqos SLAVE_LARB(39) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L19_CCUO) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L19_CCUI) &mmqos SLAVE_COMMON(0)>; interconnect-names = "ccu_g", "ccu_o", "ccu_i"; secured = "yes"; ccu_version = <72>; ccu_sramSize = <0x00020000>; ccu_sramOffset = <0x00020000>; ccu_dramSize = <0x00100000>; ccu_dramAddr = <0x80000000>; ccu_emiRegion = <20>; }; vmmspm: vmmspm { compatible = "mediatek,vmm_spm_7s"; reg = <0 0x1c001000 0 0x1000>; // sys_spm reg-names = "SPM_BASE"; vmm-pmic-supply = <&mt6319_6_vbuck3>; }; camsys_power: camsys-power { compatible = "mediatek,vmm_notifier"; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clock-names = "cam_avs"; clocks = <&camsys_main_clk CLK_CAM_MAIN_AVS_CON_0>; pd-id = <0>; reg = <0 0x1A00D000 0 0x1000>; reg-names = "cam_reg"; }; imgsys_power: imgsys-power { compatible = "mediatek,vmm_notifier"; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; clock-names = "img_avs"; clocks = <&imgsys_main_clk CLK_IMG_AVS>; pd-id = <1>; reg = <0 0x15004000 0 0x1000>; reg-names = "img_reg"; }; camsys_vcore_power: camsys-vcore-power { compatible = "mediatek,vmm_notifier"; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_VCORE>; pd-id = <2>; }; imgsys_vcore_power: imgsys-vcore-power { compatible = "mediatek,vmm_notifier"; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_VCORE>; pd-id = <3>; }; vde0_power: vde0_power { compatible = "mediatek,vmm_notifier"; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE0>; pd-id = <4>; }; vde1_power: vde1_power { compatible = "mediatek,vmm_notifier"; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE1>; pd-id = <5>; }; ccu_rproc1: ccu_rproc1 { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek,ccu_rproc1"; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&disp_iommu M4U_PORT_L19_CCUO2>, <&disp_iommu M4U_PORT_L19_CCUI2>; }; ccu_main_clk: syscon@1b200000 { compatible = "mediatek,mt6985-ccu", "syscon"; reg = <0 0x1b200000 0 0x1000>; #clock-cells = <1>; }; dvs: dvs@1b210000 { compatible = "mediatek,dvs"; reg = <0 0x1b210000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; interrupts = ; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; mboxes = <&gce_m 21 1000 CMDQ_THR_PRIO_1>; mediatek,larb = <&smi_larb19>; iommus = <&mdp_iommu M4U_PORT_L19_DVS_RDMA>, <&mdp_iommu M4U_PORT_L19_DVS_WDMA>, <&mdp_iommu M4U_PORT_L19_DVP_RDMA>, <&mdp_iommu M4U_PORT_L19_DVP_WDMA>; dvs_done_async_shot = ; clocks = <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CCUSYS>, <&topckgen_clk CLK_TOP_CCU_AHB>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM2_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CCUSYS_CON_0>, <&ccu_main_clk CLK_CCU_LARB19>, <&ccu_main_clk CLK_CCU_AHB>, <&ccu_main_clk CLK_CCUSYS_CCU0>, <&ccu_main_clk CLK_CCUSYS_CCU1>, <&ccu_main_clk CLK_CCUSYS_DPE>; clock-names = "CLK_TOP_CAM_SEL", "CLK_TOP_CCUSYS_SEL", "CLK_TOP_CCU_AHB_SEL", "CAM_CG", "CAM_MRAW", "CAM_CAM2MM0_GALS", "CAM_CAM2MM1_GALS", "CAM_CAM2MM2_GALS", "CAM_CCUSYS", "CCU_LARB19", "CLK_CCU_AHB", "CLK_CCUSYS_CCU0", "CLK_CCUSYS_CCU1", "CLK_CCUSYS_DPE"; }; dvp: dvp@1b210800 { compatible = "mediatek,dvp"; reg = <0 0x1b210800 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; interrupts = ; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; mboxes = <&gce_m 21 1000 CMDQ_THR_PRIO_1>; mediatek,larb = <&smi_larb19>; iommus = <&mdp_iommu M4U_PORT_L19_DVS_RDMA>, <&mdp_iommu M4U_PORT_L19_DVS_WDMA>, <&mdp_iommu M4U_PORT_L19_DVP_RDMA>, <&mdp_iommu M4U_PORT_L19_DVP_WDMA>; dvp_done_async_shot = ; clocks = <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CCUSYS>, <&topckgen_clk CLK_TOP_CCU_AHB>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM0_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM1_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM2MM2_GALS_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CCUSYS_CON_0>, <&ccu_main_clk CLK_CCU_LARB19>, <&ccu_main_clk CLK_CCU_AHB>, <&ccu_main_clk CLK_CCUSYS_CCU0>, <&ccu_main_clk CLK_CCUSYS_CCU1>, <&ccu_main_clk CLK_CCUSYS_DPE>; clock-names = "CLK_TOP_CAM_SEL", "CLK_TOP_CCUSYS_SEL", "CLK_TOP_CCU_AHB_SEL", "CAM_CG", "CAM_MRAW", "CAM_CAM2MM0_GALS", "CAM_CAM2MM1_GALS", "CAM_CAM2MM2_GALS", "CAM_CCUSYS", "CCU_LARB19", "CLK_CCU_AHB", "CLK_CCUSYS_CCU0", "CLK_CCUSYS_CCU1", "CLK_CCUSYS_DPE"; }; mminfra_config_clk: syscon@1e800000 { compatible = "mediatek,mt6985-mminfra_config", "syscon"; reg = <0 0x1e800000 0 0x1000>; hw-voter-regmap = <&hwv>; #clock-cells = <1>; }; mdpsys_config_clk: syscon@1f000000 { compatible = "mediatek,mt6985-mdpsys", "syscon"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; }; mdpsys1_config_clk: syscon@1f800000 { compatible = "mediatek,mt6985-mdpsys1", "syscon"; reg = <0 0x1f800000 0 0x1000>; #clock-cells = <1>; }; ccipll_pll_ctrl_clk: syscon@c030000 { compatible = "mediatek,mt6985-ccipll_pll_ctrl", "syscon"; reg = <0 0xc030000 0 0x0400>; #clock-cells = <1>; }; armpll_ll_pll_ctrl_clk: syscon@c030400 { compatible = "mediatek,mt6985-armpll_ll_pll_ctrl", "syscon"; reg = <0 0xc030400 0 0x0400>; #clock-cells = <1>; }; armpll_bl_pll_ctrl_clk: syscon@c030800 { compatible = "mediatek,mt6985-armpll_bl_pll_ctrl", "syscon"; reg = <0 0xc030800 0 0x0400>; #clock-cells = <1>; }; armpll_b_pll_ctrl_clk: syscon@c030c00 { compatible = "mediatek,mt6985-armpll_b_pll_ctrl", "syscon"; reg = <0 0xc030c00 0 0x1000>; #clock-cells = <1>; }; ptppll_pll_ctrl_clk: syscon@c034000 { compatible = "mediatek,mt6985-ptppll_pll_ctrl", "syscon"; reg = <0 0xc034000 0 0x1000>; #clock-cells = <1>; }; efuse: efuse@11e80000 { compatible = "mediatek,devinfo"; efuse_segment: segment@78 { reg = <0x78 0x4>; }; u2_phy_data: u2-phy-data { reg = <0x1cc 0x4>; }; lvts_e_data1: data1 { reg = <0x2d4 0x74>; }; lvts_e_data2: data2 { reg = <0x350 0x18>; }; cpu_version: cpu_data { reg = <0x234 0x4>; }; csi_efuse0: csi_data0 { reg = <0x1d4 0x4>; }; csi_efuse1: csi_data1 { reg = <0x1d8 0x4>; }; csi_efuse2: csi_data2 { reg = <0x1dc 0x4>; }; csi_efuse3: csi_data3 { reg = <0x140 0x4>; }; csi_efuse4: csi_data4 { reg = <0x144 0x4>; }; csi_efuse5: csi_data5 { reg = <0x148 0x4>; }; lkginfo: lkg { reg = <0x218 0x18>; }; }; tboard_thermistor1: thermal-ntc1@1c805554 { compatible = "mediatek,mt6685-tia-ntc"; #thermal-sensor-cells = <0>; reg = <0 0x1c805554 0 0x4>; /* TIA DATA T0 */ temperature-lookup-table = <(-40000) 4397119>, <(-39000) 4092874>, <(-38000) 3811717>, <(-37000) 3551749>, <(-36000) 3311236>, <(-35000) 3088599>, <(-34000) 2882396>, <(-33000) 2691310>, <(-32000) 2514137>, <(-31000) 2349778>, <(-30000) 2197225>, <(-29000) 2055558>, <(-28000) 1923932>, <(-27000) 1801573>, <(-26000) 1687773>, <(-25000) 1581881>, <(-24000) 1483100>, <(-23000) 1391113>, <(-22000) 1305413>, <(-21000) 1225531>, <(-20000) 1151037>, <(-19000) 1081535>, <(-18000) 1016661>, <(-17000) 956080>, <(-16000) 899481>, <(-15000) 846579>, <(-14000) 797111>, <(-13000) 750834>, <(-12000) 707524>, <(-11000) 666972>, <(-10000) 628988>, <(-9000) 593342>, <(-8000) 559931>, <(-7000) 528602>, <(-6000) 499212>, <(-5000) 471632>, <(-4000) 445772>, <(-3000) 421480>, <(-2000) 398652>, <(-1000) 377193>, <0 357012>, <1000 338006>, <2000 320122>, <3000 303287>, <4000 287434>, <5000 272500>, <6000 258426>, <7000 245160>, <8000 232649>, <9000 220847>, <10000 209710>, <11000 199196>, <12000 189268>, <13000 179890>, <14000 171027>, <15000 162651>, <16000 154726>, <17000 147232>, <18000 140142>, <19000 133432>, <20000 127080>, <21000 121066>, <22000 115368>, <23000 109970>, <24000 104852>, <25000 100000>, <26000 95398>, <27000 91032>, <28000 86889>, <29000 82956>, <30000 79222>, <31000 75675>, <32000 72306>, <33000 69104>, <34000 66061>, <35000 63167>, <36000 60415>, <37000 57797>, <38000 55306>, <39000 52934>, <40000 50677>, <41000 48528>, <42000 46482>, <43000 44533>, <44000 42675>, <45000 40904>, <46000 39213>, <47000 37601>, <48000 36063>, <49000 34595>, <50000 33195>, <51000 31859>, <52000 30584>, <53000 29366>, <54000 28203>, <55000 27091>, <56000 26028>, <57000 25013>, <58000 24042>, <59000 23113>, <60000 22224>, <61000 21374>, <62000 20560>, <63000 19782>, <64000 19036>, <65000 18322>, <66000 17640>, <67000 16986>, <68000 16360>, <69000 15759>, <70000 15184>, <71000 14631>, <72000 14100>, <73000 13591>, <74000 13103>, <75000 12635>, <76000 12187>, <77000 11756>, <78000 11343>, <79000 10946>, <80000 10565>, <81000 10199>, <82000 9847>, <83000 9509>, <84000 9184>, <85000 8872>, <86000 8572>, <87000 8283>, <88000 8005>, <89000 7738>, <90000 7481>, <91000 7234>, <92000 6997>, <93000 6769>, <94000 6548>, <95000 6337>, <96000 6132>, <97000 5934>, <98000 5744>, <99000 5561>, <100000 5384>, <101000 5214>, <102000 5051>, <103000 4893>, <104000 4741>, <105000 4594>, <106000 4453>, <107000 4316>, <108000 4184>, <109000 4057>, <110000 3934>, <111000 3816>, <112000 3701>, <113000 3591>, <114000 3484>, <115000 3380>, <116000 3281>, <117000 3185>, <118000 3093>, <119000 3003>, <120000 2916>, <121000 2832>, <122000 2751>, <123000 2672>, <124000 2596>, <125000 2522>; }; tboard_thermistor2: thermal-ntc2@1c805558 { compatible = "mediatek,mt6685-tia-ntc"; #thermal-sensor-cells = <0>; reg = <0 0x1c805558 0 0x4>; /* TIA DATA T1 */ temperature-lookup-table = <(-40000) 4397119>, <(-39000) 4092874>, <(-38000) 3811717>, <(-37000) 3551749>, <(-36000) 3311236>, <(-35000) 3088599>, <(-34000) 2882396>, <(-33000) 2691310>, <(-32000) 2514137>, <(-31000) 2349778>, <(-30000) 2197225>, <(-29000) 2055558>, <(-28000) 1923932>, <(-27000) 1801573>, <(-26000) 1687773>, <(-25000) 1581881>, <(-24000) 1483100>, <(-23000) 1391113>, <(-22000) 1305413>, <(-21000) 1225531>, <(-20000) 1151037>, <(-19000) 1081535>, <(-18000) 1016661>, <(-17000) 956080>, <(-16000) 899481>, <(-15000) 846579>, <(-14000) 797111>, <(-13000) 750834>, <(-12000) 707524>, <(-11000) 666972>, <(-10000) 628988>, <(-9000) 593342>, <(-8000) 559931>, <(-7000) 528602>, <(-6000) 499212>, <(-5000) 471632>, <(-4000) 445772>, <(-3000) 421480>, <(-2000) 398652>, <(-1000) 377193>, <0 357012>, <1000 338006>, <2000 320122>, <3000 303287>, <4000 287434>, <5000 272500>, <6000 258426>, <7000 245160>, <8000 232649>, <9000 220847>, <10000 209710>, <11000 199196>, <12000 189268>, <13000 179890>, <14000 171027>, <15000 162651>, <16000 154726>, <17000 147232>, <18000 140142>, <19000 133432>, <20000 127080>, <21000 121066>, <22000 115368>, <23000 109970>, <24000 104852>, <25000 100000>, <26000 95398>, <27000 91032>, <28000 86889>, <29000 82956>, <30000 79222>, <31000 75675>, <32000 72306>, <33000 69104>, <34000 66061>, <35000 63167>, <36000 60415>, <37000 57797>, <38000 55306>, <39000 52934>, <40000 50677>, <41000 48528>, <42000 46482>, <43000 44533>, <44000 42675>, <45000 40904>, <46000 39213>, <47000 37601>, <48000 36063>, <49000 34595>, <50000 33195>, <51000 31859>, <52000 30584>, <53000 29366>, <54000 28203>, <55000 27091>, <56000 26028>, <57000 25013>, <58000 24042>, <59000 23113>, <60000 22224>, <61000 21374>, <62000 20560>, <63000 19782>, <64000 19036>, <65000 18322>, <66000 17640>, <67000 16986>, <68000 16360>, <69000 15759>, <70000 15184>, <71000 14631>, <72000 14100>, <73000 13591>, <74000 13103>, <75000 12635>, <76000 12187>, <77000 11756>, <78000 11343>, <79000 10946>, <80000 10565>, <81000 10199>, <82000 9847>, <83000 9509>, <84000 9184>, <85000 8872>, <86000 8572>, <87000 8283>, <88000 8005>, <89000 7738>, <90000 7481>, <91000 7234>, <92000 6997>, <93000 6769>, <94000 6548>, <95000 6337>, <96000 6132>, <97000 5934>, <98000 5744>, <99000 5561>, <100000 5384>, <101000 5214>, <102000 5051>, <103000 4893>, <104000 4741>, <105000 4594>, <106000 4453>, <107000 4316>, <108000 4184>, <109000 4057>, <110000 3934>, <111000 3816>, <112000 3701>, <113000 3591>, <114000 3484>, <115000 3380>, <116000 3281>, <117000 3185>, <118000 3093>, <119000 3003>, <120000 2916>, <121000 2832>, <122000 2751>, <123000 2672>, <124000 2596>, <125000 2522>; }; tboard_thermistor3: thermal-ntc3@1c80555c { compatible = "mediatek,mt6685-tia-ntc"; #thermal-sensor-cells = <0>; reg = <0 0x1c80555c 0 0x4>; /* TIA DATA T2 */ temperature-lookup-table = <(-40000) 4397119>, <(-39000) 4092874>, <(-38000) 3811717>, <(-37000) 3551749>, <(-36000) 3311236>, <(-35000) 3088599>, <(-34000) 2882396>, <(-33000) 2691310>, <(-32000) 2514137>, <(-31000) 2349778>, <(-30000) 2197225>, <(-29000) 2055558>, <(-28000) 1923932>, <(-27000) 1801573>, <(-26000) 1687773>, <(-25000) 1581881>, <(-24000) 1483100>, <(-23000) 1391113>, <(-22000) 1305413>, <(-21000) 1225531>, <(-20000) 1151037>, <(-19000) 1081535>, <(-18000) 1016661>, <(-17000) 956080>, <(-16000) 899481>, <(-15000) 846579>, <(-14000) 797111>, <(-13000) 750834>, <(-12000) 707524>, <(-11000) 666972>, <(-10000) 628988>, <(-9000) 593342>, <(-8000) 559931>, <(-7000) 528602>, <(-6000) 499212>, <(-5000) 471632>, <(-4000) 445772>, <(-3000) 421480>, <(-2000) 398652>, <(-1000) 377193>, <0 357012>, <1000 338006>, <2000 320122>, <3000 303287>, <4000 287434>, <5000 272500>, <6000 258426>, <7000 245160>, <8000 232649>, <9000 220847>, <10000 209710>, <11000 199196>, <12000 189268>, <13000 179890>, <14000 171027>, <15000 162651>, <16000 154726>, <17000 147232>, <18000 140142>, <19000 133432>, <20000 127080>, <21000 121066>, <22000 115368>, <23000 109970>, <24000 104852>, <25000 100000>, <26000 95398>, <27000 91032>, <28000 86889>, <29000 82956>, <30000 79222>, <31000 75675>, <32000 72306>, <33000 69104>, <34000 66061>, <35000 63167>, <36000 60415>, <37000 57797>, <38000 55306>, <39000 52934>, <40000 50677>, <41000 48528>, <42000 46482>, <43000 44533>, <44000 42675>, <45000 40904>, <46000 39213>, <47000 37601>, <48000 36063>, <49000 34595>, <50000 33195>, <51000 31859>, <52000 30584>, <53000 29366>, <54000 28203>, <55000 27091>, <56000 26028>, <57000 25013>, <58000 24042>, <59000 23113>, <60000 22224>, <61000 21374>, <62000 20560>, <63000 19782>, <64000 19036>, <65000 18322>, <66000 17640>, <67000 16986>, <68000 16360>, <69000 15759>, <70000 15184>, <71000 14631>, <72000 14100>, <73000 13591>, <74000 13103>, <75000 12635>, <76000 12187>, <77000 11756>, <78000 11343>, <79000 10946>, <80000 10565>, <81000 10199>, <82000 9847>, <83000 9509>, <84000 9184>, <85000 8872>, <86000 8572>, <87000 8283>, <88000 8005>, <89000 7738>, <90000 7481>, <91000 7234>, <92000 6997>, <93000 6769>, <94000 6548>, <95000 6337>, <96000 6132>, <97000 5934>, <98000 5744>, <99000 5561>, <100000 5384>, <101000 5214>, <102000 5051>, <103000 4893>, <104000 4741>, <105000 4594>, <106000 4453>, <107000 4316>, <108000 4184>, <109000 4057>, <110000 3934>, <111000 3816>, <112000 3701>, <113000 3591>, <114000 3484>, <115000 3380>, <116000 3281>, <117000 3185>, <118000 3093>, <119000 3003>, <120000 2916>, <121000 2832>, <122000 2751>, <123000 2672>, <124000 2596>, <125000 2522>; }; tboard_thermistor4: thermal-ntc4 { compatible = "generic-adc-thermal"; #thermal-sensor-cells = <0>; io-channels = <&pmic_adc (ADC_PURES_OPEN_MASK | AUXADC_VIN2)>; io-channel-names = "sensor-channel"; temperature-lookup-table = <(-40000) 1760>, <(-39000) 1757>, <(-38000) 1754>, <(-37000) 1751>, <(-36000) 1747>, <(-35000) 1744>, <(-34000) 1740>, <(-33000) 1736>, <(-32000) 1731>, <(-31000) 1727>, <(-30000) 1722>, <(-29000) 1716>, <(-28000) 1711>, <(-27000) 1705>, <(-26000) 1699>, <(-25000) 1693>, <(-24000) 1686>, <(-23000) 1679>, <(-22000) 1672>, <(-21000) 1664>, <(-20000) 1656>, <(-19000) 1648>, <(-18000) 1639>, <(-17000) 1630>, <(-16000) 1620>, <(-15000) 1610>, <(-14000) 1599>, <(-13000) 1588>, <(-12000) 1577>, <(-11000) 1565>, <(-10000) 1553>, <(-9000) 1540>, <(-8000) 1527>, <(-7000) 1514>, <(-6000) 1500>, <(-5000) 1485>, <(-4000) 1470>, <(-3000) 1455>, <(-2000) 1439>, <(-1000) 1423>, <0 1406>, <1000 1389>, <2000 1372>, <3000 1354>, <4000 1335>, <5000 1317>, <6000 1298>, <7000 1279>, <8000 1259>, <9000 1239>, <10000 1219>, <11000 1198>, <12000 1178>, <13000 1157>, <14000 1136>, <15000 1115>, <16000 1093>, <17000 1072>, <18000 1050>, <19000 1029>, <20000 1007>, <21000 986>, <22000 964>, <23000 943>, <24000 921>, <25000 900>, <26000 879>, <27000 858>, <28000 837>, <29000 816>, <30000 796>, <31000 775>, <32000 755>, <33000 736>, <34000 716>, <35000 697>, <36000 678>, <37000 659>, <38000 641>, <39000 623>, <40000 605>, <41000 588>, <42000 571>, <43000 555>, <44000 538>, <45000 523>, <46000 507>, <47000 492>, <48000 477>, <49000 463>, <50000 449>, <51000 435>, <52000 422>, <53000 409>, <54000 396>, <55000 384>, <56000 372>, <57000 360>, <58000 349>, <59000 338>, <60000 327>, <61000 317>, <62000 307>, <63000 297>, <64000 288>, <65000 279>, <66000 270>, <67000 261>, <68000 253>, <69000 245>, <70000 237>, <71000 230>, <72000 222>, <73000 215>, <74000 209>, <75000 202>, <76000 196>, <77000 189>, <78000 183>, <79000 178>, <80000 172>, <81000 167>, <82000 161>, <83000 156>, <84000 151>, <85000 147>, <86000 142>, <87000 138>, <88000 133>, <89000 129>, <90000 125>, <91000 121>, <92000 118>, <93000 114>, <94000 111>, <95000 107>, <96000 104>, <97000 101>, <98000 98>, <99000 95>, <100000 92>, <101000 89>, <102000 87>, <103000 84>, <104000 81>, <105000 79>, <106000 77>, <107000 74>, <108000 72>, <109000 70>, <110000 68>, <111000 66>, <112000 64>, <113000 62>, <114000 61>, <115000 59>, <116000 57>, <117000 56>, <118000 54>, <119000 52>, <120000 51>, <121000 50>, <122000 48>, <123000 47>, <124000 46>, <125000 44>; }; tboard_thermistor5: thermal-ntc5 { compatible = "generic-adc-thermal"; #thermal-sensor-cells = <0>; io-channels = <&pmic_adc (ADC_PURES_OPEN_MASK | AUXADC_VIN3)>; io-channel-names = "sensor-channel"; temperature-lookup-table = <(-40000) 1760>, <(-39000) 1757>, <(-38000) 1754>, <(-37000) 1751>, <(-36000) 1747>, <(-35000) 1744>, <(-34000) 1740>, <(-33000) 1736>, <(-32000) 1731>, <(-31000) 1727>, <(-30000) 1722>, <(-29000) 1716>, <(-28000) 1711>, <(-27000) 1705>, <(-26000) 1699>, <(-25000) 1693>, <(-24000) 1686>, <(-23000) 1679>, <(-22000) 1672>, <(-21000) 1664>, <(-20000) 1656>, <(-19000) 1648>, <(-18000) 1639>, <(-17000) 1630>, <(-16000) 1620>, <(-15000) 1610>, <(-14000) 1599>, <(-13000) 1588>, <(-12000) 1577>, <(-11000) 1565>, <(-10000) 1553>, <(-9000) 1540>, <(-8000) 1527>, <(-7000) 1514>, <(-6000) 1500>, <(-5000) 1485>, <(-4000) 1470>, <(-3000) 1455>, <(-2000) 1439>, <(-1000) 1423>, <0 1406>, <1000 1389>, <2000 1372>, <3000 1354>, <4000 1335>, <5000 1317>, <6000 1298>, <7000 1279>, <8000 1259>, <9000 1239>, <10000 1219>, <11000 1198>, <12000 1178>, <13000 1157>, <14000 1136>, <15000 1115>, <16000 1093>, <17000 1072>, <18000 1050>, <19000 1029>, <20000 1007>, <21000 986>, <22000 964>, <23000 943>, <24000 921>, <25000 900>, <26000 879>, <27000 858>, <28000 837>, <29000 816>, <30000 796>, <31000 775>, <32000 755>, <33000 736>, <34000 716>, <35000 697>, <36000 678>, <37000 659>, <38000 641>, <39000 623>, <40000 605>, <41000 588>, <42000 571>, <43000 555>, <44000 538>, <45000 523>, <46000 507>, <47000 492>, <48000 477>, <49000 463>, <50000 449>, <51000 435>, <52000 422>, <53000 409>, <54000 396>, <55000 384>, <56000 372>, <57000 360>, <58000 349>, <59000 338>, <60000 327>, <61000 317>, <62000 307>, <63000 297>, <64000 288>, <65000 279>, <66000 270>, <67000 261>, <68000 253>, <69000 245>, <70000 237>, <71000 230>, <72000 222>, <73000 215>, <74000 209>, <75000 202>, <76000 196>, <77000 189>, <78000 183>, <79000 178>, <80000 172>, <81000 167>, <82000 161>, <83000 156>, <84000 151>, <85000 147>, <86000 142>, <87000 138>, <88000 133>, <89000 129>, <90000 125>, <91000 121>, <92000 118>, <93000 114>, <94000 111>, <95000 107>, <96000 104>, <97000 101>, <98000 98>, <99000 95>, <100000 92>, <101000 89>, <102000 87>, <103000 84>, <104000 81>, <105000 79>, <106000 77>, <107000 74>, <108000 72>, <109000 70>, <110000 68>, <111000 66>, <112000 64>, <113000 62>, <114000 61>, <115000 59>, <116000 57>, <117000 56>, <118000 54>, <119000 52>, <120000 51>, <121000 50>, <122000 48>, <123000 47>, <124000 46>, <125000 44>; }; tsx_thermistor: thermal-ntc6@1c80554c { compatible = "mediatek,mt6685-tia-ntc"; #thermal-sensor-cells = <0>; reg = <0 0x1c80554c 0 0x4>; /* TIA DATA TSX */ temperature-lookup-table = <(-40000) 5319893>, <(-39000) 4921450>, <(-38000) 4555864>, <(-37000) 4220193>, <(-36000) 3911778>, <(-35000) 3628214>, <(-34000) 3367324>, <(-33000) 3127136>, <(-32000) 2905864>, <(-31000) 2701885>, <(-30000) 2513730>, <(-29000) 2340060>, <(-28000) 2179662>, <(-27000) 2031430>, <(-26000) 1894358>, <(-25000) 1767530>, <(-24000) 1650110>, <(-23000) 1541338>, <(-22000) 1440519>, <(-21000) 1347016>, <(-20000) 1260250>, <(-19000) 1179692>, <(-18000) 1104854>, <(-17000) 1035294>, <(-16000) 970604>, <(-15000) 910412>, <(-14000) 854374>, <(-13000) 802177>, <(-12000) 753533>, <(-11000) 708176>, <(-10000) 665864>, <(-9000) 626371>, <(-8000) 589493>, <(-7000) 555039>, <(-6000) 522835>, <(-5000) 492719>, <(-4000) 464542>, <(-3000) 438167>, <(-2000) 413469>, <(-1000) 390328>, <0 368639>, <1000 348299>, <2000 329218>, <3000 311309>, <4000 294493>, <5000 278697>, <6000 263852>, <7000 249896>, <8000 236769>, <9000 224418>, <10000 212791>, <11000 201843>, <12000 191528>, <13000 181808>, <14000 172643>, <15000 163999>, <16000 155844>, <17000 148146>, <18000 140877>, <19000 134011>, <20000 127523>, <21000 121390>, <22000 115591>, <23000 110105>, <24000 104914>, <25000 100000>, <26000 95347>, <27000 90939>, <28000 86762>, <29000 82803>, <30000 79049>, <31000 75488>, <32000 72109>, <33000 68902>, <34000 65857>, <35000 62965>, <36000 60218>, <37000 57607>, <38000 55125>, <39000 52765>, <40000 50520>, <41000 48384>, <42000 46351>, <43000 44415>, <44000 42572>, <45000 40816>, <46000 39143>, <47000 37548>, <48000 36028>, <49000 34578>, <50000 33195>, <51000 31875>, <52000 30615>, <53000 29412>, <54000 28264>, <55000 27167>, <56000 26119>, <57000 25117>, <58000 24159>, <59000 23243>, <60000 22368>, <61000 21530>, <62000 20728>, <63000 19961>, <64000 19226>, <65000 18523>, <66000 17849>, <67000 17203>, <68000 16584>, <69000 15991>, <70000 15423>, <71000 14878>, <72000 14355>, <73000 13853>, <74000 13372>, <75000 12910>, <76000 12466>, <77000 12040>, <78000 11631>, <79000 11238>, <80000 10861>, <81000 10498>, <82000 10149>, <83000 9814>, <84000 9491>, <85000 9181>, <86000 8883>, <87000 8596>, <88000 8319>, <89000 8053>, <90000 7797>, <91000 7551>, <92000 7313>, <93000 7084>, <94000 6864>, <95000 6651>, <96000 6446>, <97000 6249>, <98000 6059>, <99000 5875>, <100000 5698>, <101000 5527>, <102000 5362>, <103000 5203>, <104000 5050>, <105000 4901>, <106000 4758>, <107000 4620>, <108000 4486>, <109000 4357>, <110000 4233>, <111000 4112>, <112000 3996>, <113000 3883>, <114000 3774>, <115000 3669>, <116000 3567>, <117000 3469>, <118000 3374>, <119000 3281>, <120000 3192>, <121000 3106>, <122000 3022>, <123000 2941>, <124000 2863>, <125000 2787>; }; md_cooler: md-cooler { compatible = "mediatek,mt6298-md-cooler"; pa1: pa1 { mutt_pa1: mutt-pa1 { #cooling-cells = <2>; }; tx_pwr_pa1: tx-pwr-pa1 { #cooling-cells = <2>; }; }; pa2: pa2 { mutt_pa2: mutt-pa2 { #cooling-cells = <2>; }; tx_pwr_pa2: tx-pwr-pa2 { #cooling-cells = <2>; }; scg_off_pa2: scg-off-pa2 { #cooling-cells = <2>; }; }; }; wifi_cooler: wifi-cooler { compatible = "mediatek,wifi-level-cooler"; #cooling-cells = <2>; }; charger_cooler: charger-cooler { compatible = "mediatek,mt6375-charger-cooler"; #cooling-cells = <2>; }; backlight_cooler: backlight-cooler { compatible = "mediatek,backlight-cooler"; backlight-names = "lcd-backlight"; #cooling-cells = <2>; }; therm_intf: therm-intf@114000 { compatible = "mediatek,therm_intf"; reg = <0 0x00114000 0 0x400>, <0 0x190e1000 0 0x1000>; reg-names = "therm_sram", "apu_mbox"; }; thermal_zones: thermal-zones { soc_max { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 0>; trips { soc_max_crit: so-max-crit { temperature = <119000>; hysteresis = <2000>; type = "critical"; }; }; }; cpu-medium1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 1>; }; cpu-medium2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 2>; }; cpu-medium3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 3>; }; cpu-medium4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 4>; }; cpu-little1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 5>; }; cpu-little2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 6>; }; cpu-little3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 7>; }; cpu-little4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 8>; }; cpu-little5 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 9>; }; cpu-little6 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 10>; }; cpu-little7 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 11>; }; cpu-little8 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 12>; }; cpu-medium5 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 13>; }; cpu-medium6 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 14>; }; cpu-big1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 15>; }; cpu-big2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 16>; }; apu-a-1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 17>; }; apu-a-2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 18>; }; apu-a-3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 19>; }; apu-a-4{ polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 20>; }; apu-b-1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 21>; }; soc1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 22>; }; soc2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 23>; }; soc3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 24>; }; soc4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 25>; }; soc5 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 26>; }; soc6 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 27>; }; soc7 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 28>; }; soc8 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 29>; }; md1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 30>; }; md2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 31>; }; md3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 32>; }; md4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 33>; }; gpu1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 34>; }; gpu2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 36>; }; gpu3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 38>; }; gpu4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 39>; }; gpu5 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&lvts 40>; }; ap_ntc: ap_ntc { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tboard_thermistor1>; }; ltepa_ntc: ltepa_ntc { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tboard_thermistor2>; }; nrpa_ntc: nrpa_ntc { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tboard_thermistor3>; }; quiet_ntc: quiet_ntc { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tboard_thermistor4>; }; wifi_ntc: wifi-ntc { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tboard_thermistor5>; }; tsx_ntc: tsx-ntc { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tsx_thermistor>; }; vtskin-max { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&vtskin 0>; }; vtskin1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&vtskin 1>; }; vtskin2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&vtskin 2>; }; vtskin3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&vtskin 3>; }; vtskin4 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&vtskin 4>; }; vtskin5 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&vtskin 5>; }; vtskin6 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&vtskin 6>; }; wifi-adie-0 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&wifi 0>; }; wifi-ddie-0 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&wifi 1>; }; wifi-ddie-1 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&wifi 2>; }; wifi-ddie-2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&wifi 3>; }; wifi-ddie-3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&wifi 4>; }; pmic6363-vio18 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6363_temp 0>; }; pmic6363-vs1-vs3 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6363_temp 1>; }; pmic6363-bk3-bk7 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6363_temp 2>; }; pmic6363-vs2 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6363_temp 3>; }; pmic6373-bk0 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6373_temp 0>; }; pmic6373-ldo { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6373_temp 1>; }; pmic6373-bk3-bk7 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6373_temp 2>; }; pmic6373-bk4-bk8 { polling-delay = <0>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&mt6373_temp 3>; }; }; mt6363_temp: mt6363-temp { compatible = "mediatek,mt6363-pmic-temp"; io-channels = <&pmic_adc AUXADC_CHIP_TEMP>, <&pmic_adc AUXADC_VCORE_TEMP>, <&pmic_adc AUXADC_VPROC_TEMP>, <&pmic_adc AUXADC_VGPU_TEMP>; io-channel-names = "pmic6363_ts1", "pmic6363_ts2", "pmic6363_ts3", "pmic6363_ts4"; #thermal-sensor-cells = <1>; nvmem-cells = <&mt6363_thermal_efuse>; nvmem-cell-names = "mt6363_e_data"; }; mt6373_temp: mt6373-temp { compatible = "mediatek,mt6373-pmic-temp"; io-channels = <&mt6373_adc AUXADC_CHIP_TEMP>, <&mt6373_adc AUXADC_VCORE_TEMP>, <&mt6373_adc AUXADC_VPROC_TEMP>, <&mt6373_adc AUXADC_VGPU_TEMP>; io-channel-names = "pmic6373_ts1", "pmic6373_ts2", "pmic6373_ts3", "pmic6373_ts4"; #thermal-sensor-cells = <1>; nvmem-cells = <&mt6373_thermal_efuse>; nvmem-cell-names = "mt6373_e_data"; }; odm: odm { compatible = "simple-bus"; /* reserved for overlay by odm */ }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges; drm:drm@1000d000 { compatible = "mediatek,dbgtop-drm"; reg = <0 0x1000d000 0 0x1000>; rgu_timeout = <0xea60>; // for ddr-reserved mode ver = <2>; }; lkg: lkg@114400 { compatible = "mediatek,mtk-lkg"; reg = <0 0x00114400 0 0xc00>; }; performance: performance-controller@11bc00 { compatible = "mediatek,cpufreq-hw"; reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>, <0 0x0011be50 0 0x120>; reg-names = "performance-domain0", "performance-domain1", "performance-domain2"; #performance-domain-cells = <1>; }; eas_info: eas_info { compatible = "mediatek,eas-info"; csram-base = <0x0011bc00>; /* L, M, B, CCI */ offs-thermal-limit = <0x1208 0x120c 0x1210 0x1214>; offs-cap = <0xfa0>; }; cpu_mcucfg: mcusys_ao_cfg@c530000 { reg = <0 0x0c000000 0 0x10000>; /* 64KB */ }; dfd_mcu: dfd-mcu { compatible = "mediatek,dfd_mcu"; enabled = <1>; hw-version = <35>; sw-version = <1>; dfd-timeout = <0x2710>; buf-addr-align = <0x400000>; buf-addr-max = <0xffffffff>; buf-length = <0x280000>; nr-max-core = <8>; nr-big-core = <4>; nr-rs-entry-little = <8>; nr-rs-entry-big = <16>; nr-header-row = <4>; chip-id-offset = <0x38>; check-pattern-offset = <0x20>; dfd-disable-efuse = <25 12>; /* dfd-disable-efuse = <(-1) (-1)>; */ dfd_cache: dfd-cache { enabled = <1>; /* dfd-timeout = <0x1d4c0>; */ /* 60 sec */ dfd-timeout = <0x6000>; /* 12.3 sec */ /* buf-length = <0x2000000>; */ buf-length = <0x280000>; tap-en = <0x200000>; }; }; dfd_soc: dfd-soc { compatible = "mediatek,dfd_soc"; enabled = <1>; dfd-timeout = <0x1000>; buf-length = <0x200000>; buf-addr-align = <0x400000>; buf-addr-max = <0xffffffff>; }; cpu_pll: mcusys_pll1u_top@1000c000 { reg = <0 0x0c030000 0 0x1000>; /* 4KB */ }; apdma: dma-controller@11301000 { compatible = "mediatek,mt6985-uart-dma"; reg = <0 0x11301000 0 0x80>, <0 0x11301080 0 0x80>, <0 0x11301100 0 0x80>, <0 0x11301180 0 0x80>, <0 0x11301200 0 0x80>, <0 0x11301280 0 0x80>, <0 0x11301300 0 0x80>, <0 0x11301380 0 0x80>; interrupts = , , , , , , , ; clocks = <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "apdma"; dma-requests = <8>; support-hub = <0xC0>; /*bit 0~7 to ch 0~7*/ peri-regs = <0x11036300 0x1 0x1>; /*peri: */ peri-axi-dbg = <0x11036150>; #dma-cells = <1>; }; uart0: serial@11001000 { compatible = "mediatek,mt6577-uart"; reg = <0 0x11001000 0 0x1000>; interrupts = ; clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>; clock-names = "baud", "bus"; dmas = <&apdma 0 &apdma 1>; dma-names = "tx", "rx"; uart_line = <0>; }; uart1: serial@11002000 { compatible = "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = ; clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART1>; clock-names = "baud", "bus"; dmas = <&apdma 2 &apdma 3>; dma-names = "tx", "rx"; uart_line = <1>; }; uart2: serial@11003000 { compatible = "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x1000>; interrupts = ; clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART2>; clock-names = "baud", "bus"; dmas = <&apdma 4 &apdma 5>; dma-names = "tx", "rx"; uart_line = <2>; }; uart3: serial@11004000 { compatible = "mediatek,mt6985-uart"; reg = <0 0x11004000 0 0x1000>; interrupts = ; clocks = <&clk104m>, <&pericfg_ao_clk CLK_PERAO_UART3>; clock-names = "baud", "bus"; dmas = <&apdma 6 &apdma 7>; dma-names = "tx", "rx"; peri-clock-con = <0x11036020 0xF00 0x800>; /*UART ClOCK SEL*/ peri-wakeup = <0x11036050 0x3 0x3 0x1>; /*reg* mask* val* toggal*/ peri-wakeup-sta = <0x11036054>; peri-reset = <0x11036000>; peri-reset-set = <0x11036004 0x80000 0x80000>; /*reg* mask* val*/ peri-reset-clr = <0x11036008 0x80000 0x80000>; /*reg* mask* val*/ uart_line = <3>; hub-baud = <12000000>; }; mtk_leds: mtk_leds { backlight { label = "lcd-backlight"; max-brightness = <2047>; min-brightness = <4>; max-hw-brightness = <2047>; }; }; mtk_leds1: mtk_leds1 { backlight { label = "lcd-backlight1"; max-brightness = <2047>; min-brightness = <4>; max-hw-brightness = <2047>; }; }; topckgen@10000000 { compatible = "mediatek,topckgen"; reg = <0 0x10000000 0 0x1000>; }; infracfg_ao@10001000 { compatible = "mediatek,infracfg_ao"; reg = <0 0x10001000 0 0x1000>; }; scp_infra: scp_infra@10001000 { compatible = "mediatek,scpinfra"; reg = <0 0x10001000 0 0x1000>, /* infracfg_ao */ <0 0x10006000 0 0x1000>, /* spm */ <0 0x10000000 0 0x1000>; /* topckgen */ #clock-cells = <1>; }; gpio: gpio@10005000 { compatible = "mediatek,gpio"; reg = <0 0x10005000 0 0x1000>; }; pio: pinctrl { compatible = "mediatek,mt6985-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x11b20000 0 0x1000>, <0 0x11c00000 0 0x1000>, <0 0x11d30000 0 0x1000>, <0 0x11d40000 0 0x1000>, <0 0x11d50000 0 0x1000>, <0 0x11d80000 0 0x1000>, <0 0x11d90000 0 0x1000>, <0 0x11f10000 0 0x1000>, <0 0x11f20000 0 0x1000>, <0 0x11f30000 0 0x1000>, <0 0x11f40000 0 0x1000>; reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_bl", "iocfg_bm", "iocfg_br", "iocfg_brr", "iocfg_lb", "iocfg_tr", "iocfg_tm", "iocfg_tl", "iocfg_lt"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 242>; interrupt-controller; #interrupt-cells = <2>; mediatek,eint = <&eint>; }; mtkfb: mtkfb { compatible = "mediatek,mtkfb"; }; apmixed@1000c000 { compatible = "mediatek,apmixed"; reg = <0 0x1000c000 0 0xe00>; }; fhctl: fhctl@1000ce00 { compatible = "mediatek,mt6985-fhctl"; reg = <0 0x1000ce00 0 0x200>, //AP FHCTL base <0 0x1000c000 0 0xe00>, //APMIX base <0 0x13fa0100 0 0x030>, //GPU0 EN <0 0x13fa0000 0 0x100>, //GPU APMIX <0 0x13fa0d00 0 0x030>, <0 0x13fa0c00 0 0x100>, <0 0x0c030100 0 0x030>,//mcupm EN <0 0x0c030000 0 0x100>,//mcupm APMIX <0 0x0c030500 0 0x030>, <0 0x0c030400 0 0x100>, <0 0x0c030900 0 0x030>, <0 0x0c030800 0 0x100>, <0 0x0c030d00 0 0x030>, <0 0x0c030c00 0 0x100>, <0 0x0c034100 0 0x030>, <0 0x0c034000 0 0x100>; map0 { domain = "top"; method = "fhctl-ap"; mainpll2 { fh-id = <0>; pll-id = ; }; mmpll2 { fh-id = <1>; pll-id = ; }; mpll { fh-id = <4>; pll-id = ; }; mmpll { fh-id = <5>; pll-id = ; }; mainpll { fh-id = <6>; pll-id = ; }; msdcpll { fh-id = <7>; pll-id = ; }; adsppll { fh-id = <8>; pll-id = ; }; imgpll { fh-id = <9>; pll-id = ; }; tvdpll { fh-id = <10>; pll-id = ; }; }; map6 { domain = "gpu0"; method = "fhctl-gpueb"; mfg_ao_mfgpll { fh-id = <0>; pll-id = ; }; }; map9 { domain = "gpu3"; method = "fhctl-gpueb"; mfgsc_ao_mfgscpll { fh-id = <0>; pll-id = ; }; }; map10 { domain = "mcu0"; method = "fhctl-mcupm"; buspll { fh-id = <0>; pll-id = <999>; perms = <0x18>; }; }; map11 { domain = "mcu1"; method = "fhctl-mcupm"; cpu0pll { fh-id = <0>; pll-id = <999>; perms = <0x1C>; }; }; map12 { domain = "mcu2"; method = "fhctl-mcupm"; cpu1pll { fh-id = <0>; pll-id = <999>; perms = <0x1C>; }; }; map13 { domain = "mcu3"; method = "fhctl-mcupm"; cpu2pll { fh-id = <0>; pll-id = <999>; perms = <0x1C>; }; }; map14 { domain = "mcu4"; method = "fhctl-mcupm"; ptppll { fh-id = <0>; pll-id = <999>; perms = <0x1C>; }; }; }; pmsr_apb@1000f000 { compatible = "mediatek,pmsr_apb"; reg = <0 0x1000f000 0 0x800>; }; topmisc@10011000 { compatible = "mediatek,topmisc"; reg = <0 0x10011000 0 0x1000>; }; mbist_ao@10013000 { compatible = "mediatek,mbist_ao"; reg = <0 0x10013000 0 0x1000>; }; topckgen_ao@1001b000 { compatible = "mediatek,topckgen_ao"; reg = <0 0x1001b000 0 0x1000>; }; devapc_ao_mm@1001c000 { compatible = "mediatek,devapc_ao_mm"; reg = <0 0x1001c000 0 0x1000>; }; devapc_ao_infra_peri@10022000 { compatible = "mediatek,devapc_ao_infra_peri"; reg = <0 0x10022000 0 0x1000>; }; devapc_ao_infra_peri@10023000 { compatible = "mediatek,devapc_ao_infra_peri"; reg = <0 0x10023000 0 0x1000>; }; bcrm_infra_ao1_apb@1002a000 { compatible = "mediatek,bcrm_infra_ao1_apb"; reg = <0 0x1002a000 0 0x1000>; }; debug_ctrl_infra_ao1_apb@1002b000 { compatible = "mediatek,debug_ctrl_infra_ao1_apb"; reg = <0 0x1002b000 0 0x1000>; }; sys_cirq@10204000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10204000 0 0x1000>; interrupts = ; }; nth_emi_mbist_pdn_apb@10205000 { compatible = "mediatek,nth_emi_mbist_pdn_apb"; reg = <0 0x10205000 0 0x1000>; }; devapc@10207000 { compatible = "mediatek,mt6985-devapc"; reg = <0 0x10207000 0 0x1000>, /* infra pd */ <0 0x10274000 0 0x1000>, /* infra1 pd */ <0 0x11020000 0 0x1000>, /* peri pd */ <0 0x1c01c000 0 0x1000>, /* vlp pd */ <0 0x1e019000 0 0x1000>, /* adsp pd */ <0 0x1e826000 0 0x1000>, /* mminfra pd */ <0 0x1eca4000 0 0x1000>, /* mmup pd */ <0 0x13fa2000 0 0x1000>, /* gpu pd */ <0 0x10030000 0 0x1000>, /* infra ao */ <0 0x1103c000 0 0x1000>, /* peri ao */ <0 0x1c018000 0 0x1000>, /* vlp ao */ <0 0x1e01c000 0 0x1000>, /* adsp ao */ <0 0x1e820000 0 0x1000>, /* mminfra ao */ <0 0x1eca0000 0 0x1000>, /* mmup ao */ <0 0x13fa1000 0 0x1000>, /* gpu ao */ <0 0x1020e000 0 0x1000>, /* infracfg */ <0 0x10033000 0 0x1000>, /* swp */ <0 0x0010c000 0 0x1000>; /* sramrom */ interrupts = , /* infra irq */ , /* peri irq */ , /* vlp irq */ , /* adsp irq */ , /* mminfra irq */ , /* mmup irq */ ; /* gpu irq */ }; bus_dbg@10208000 { compatible = "mediatek,bus_dbg"; reg = <0 0x10208000 0 0x1000>; }; dpmaif:dpmaif@10014000 { compatible = "mediatek,dpmaif"; reg = <0 0x10014000 0 0x1000>, /*AO_UL*/ <0 0x1022d000 0 0x1000>, /*PD_UL*/ <0 0x1022c000 0 0x1000>, /*PD_MD_MISC*/ <0 0x1022e000 0 0x1000>; /*SRAM*/ /* rxq0 irq: 179 307 339 */ interrupts = , ; /* new rxq1 irq: 724 852 884 */ mediatek,dpmaif-ver = <3>; mediatek,dpmaif-cap = <0x00000004>; mediatek,plat-info = <6985>; clocks = <&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>, <&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>, <&infracfg_ao_clk CLK_IFRAO_RG_MMW_DPMAIF26M_CK>; clock-names = "infra-dpmaif-clk", "infra-dpmaif-blk-clk", "infra-dpmaif-rg-mmw-clk"; interconnects = <&dvfsrc MT6873_MASTER_NETSYS &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "icc-mdspd-bw"; required-opps = <&dvfsrc_freq_opp0>, <&dvfsrc_freq_opp1>; net-spd-ver = <8>; hw-reset-ver = <1>; dpmaif-infracfg = <&infracfg_ao_clk>; }; ccifdriver:ccifdriver@10209000 { compatible = "mediatek,ccci_ccif"; reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/ <0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/ mediatek,sram-size = <512>; /* ccif hw reset version */ mediatek,ccif-hw-reset-ver = <1>; /* ccif hw reset bit */ mediatek,ccif-hw-reset-bit = <18>; /* no need control ccif0 clk when ccif_clk_free_run = 1 */ mediatek,ccif-clk-free-run = <1>; /* DTS/GIC_ID: CCIF0 289/321; CCIF0 290/322 */ interrupts = , ; }; mddriver:mddriver { compatible = "mediatek,mddriver"; /* bit0~3: CLDMA|CCIF|DPMAIF */ mediatek,mdhif-type = <6>; mediatek,ap-plat-info = <6985>; mediatek,md-generation = <6298>; mediatek,md-sub-version = <1>; /* 0x44: epon offset; */ /* 0x06: once a value[1] exist, means in l2sram */ /* value[1] not exist means in mddbgsys. the value(6) has no meaningful */ mediatek,offset-epon-md1 = <0x44 0x06>; mediatek,cldma-capability = <10>; /* bit0:srcclkena|bit1:srclken_o1_on|bit2:revert_sequencer */ mediatek,power-flow-config = <0x4>; /* srclken_o1 set value |= 1<<14 */ mediatek,srclken-o1 = <0>; reg = <0 0x0d124000 0 0x2000>; /* l2sram base address */ /* DTS/GIC_ID: MDWDT 304/336; CCIF0 289/321; CCIF0 290/322 */ interrupts = , , ; power-domains = <&scpsys MT6985_POWER_DOMAIN_MD>; ccci-infracfg = <&infracfg_ao_clk>; ccci-topckgen = <&topckgen_clk>; /* ccci-spmsleep = <&sleep>; */ }; md_auxadc:md-auxadc { compatible = "mediatek,md_auxadc"; /* io-channels = <&auxadc 2>; */ io-channel-names = "md-channel", "md-battery"; }; ccci_scp:ccci-scp { compatible = "mediatek,ccci_md_scp"; reg = <0 0x1023c000 0 0x1000>, /* AP_CCIF2_BASE */ <0 0x1023d000 0 0x1000>; /* MD_CCIF2_BASE */ /* no need control ccif2 clk when scp-clk-free-run = 1 */ mediatek,scp-clk-free-run = <1>; }; gpio_usage_mapping:gpio { compatible = "mediatek,gpio_usage_mapping"; }; md1_sim1_hot_plug_eint:MD1-SIM1-HOT-PLUG-EINT { }; md1_sim2_hot_plug_eint:MD1-SIM2-HOT-PLUG-EINT { }; mrdump_ext_rst:mrdump_ext_rst { compatible = "mediatek, mrdump_ext_rst-eint"; mode = "IRQ"; status = "okay"; }; subpmic_pmu_eint:subpmic_pmu_eint { }; dsi_te:dsi-te { compatible = "mediatek, dsi_te-eint"; status = "disabled"; }; dsi1_te: dsi1-te { compatible = "mediatek, dsi1_te-eint"; status = "disabled"; }; ap-ccif0@10209000 { compatible = "mediatek,ap_ccif0"; reg = <0 0x10209000 0 0x1000>; }; md-ccif0@1020a000 { compatible = "mediatek,md_ccif0"; reg = <0 0x1020a000 0 0x1000>; }; ap-ccif1@1020b000 { compatible = "mediatek,ap_ccif1"; reg = <0 0x1020b000 0 0x1000>; }; md-ccif1@1020c000 { compatible = "mediatek,md_ccif1"; reg = <0 0x1020c000 0 0x1000>; }; infra_mbist@1020d000 { compatible = "mediatek,infra_mbist"; reg = <0 0x1020d000 0 0x1000>; }; infracfg@1020e000 { compatible = "mediatek,infracfg"; reg = <0 0x1020e000 0 0x1000>; }; trng@1020f000 { compatible = "mediatek,trng"; reg = <0 0x1020f000 0 0x1000>; }; dxcc_sec@10210000 { compatible = "mediatek,dxcc_sec"; reg = <0 0x10210000 0 0x1000>; }; md2md_md1_ccif0@10211000 { compatible = "mediatek,md2md_md1_ccif0"; reg = <0 0x10211000 0 0x1000>; }; cq_dma@10212000 { compatible = "mediatek,cq_dma"; reg = <0 0x10212000 0 0x1000>; interrupts = ; }; md2md_md2_ccif0@10213000 { compatible = "mediatek,md2md_md2_ccif0"; reg = <0 0x10213000 0 0x1000>; }; sramrom@10214000 { compatible = "mediatek,sramrom"; reg = <0 0x10214000 0 0x1000>; }; infra_bcrm@10215000 { compatible = "mediatek,infra_bcrm"; reg = <0 0x10215000 0 0x1000>; }; sub_infra_bcrm@10216000 { compatible = "mediatek,sub_infra_bcrm"; reg = <0 0x10216000 0 0x1000>; }; dbg_tracker2@10218000 { compatible = "mediatek,dbg_tracker2"; reg = <0 0x10218000 0 0x1000>; }; emicen: emicen@10219000 { compatible = "mediatek,mt6877-emicen", "mediatek,common-emicen"; reg = <0 0x10219000 0 0x1000>, <0 0x1021d000 0 0x1000>; mediatek,emi-reg = <&emichn>; a2d_hash = <0xb>; a2d_disph = <0xe>; }; emichn: emichn@10235000 { compatible = "mediatek,mt6877-emichn", "mediatek,common-emichn"; reg = <0 0x10235000 0 0x1000>, <0 0x10245000 0 0x1000>, <0 0x10255000 0 0x1000>, <0 0x10265000 0 0x1000>; }; emi-fake-eng@1026c000 { compatible = "mediatek,emi-fake-engine"; reg = <0 0x1026c000 0 0x1000>, <0 0x1026d000 0 0x1000>, <0 0x10310000 0 0x1000>, <0 0x10311000 0 0x1000>; }; emiisu { compatible = "mediatek,mt6983-emiisu", "mediatek,common-emiisu"; ctrl_intf = <1>; }; infra_device_mpu@1021a000 { compatible = "mediatek,infra_device_mpu"; reg = <0 0x1021a000 0 0x1000>; }; infra_device_mpu@1021b000 { compatible = "mediatek,infra_device_mpu"; reg = <0 0x1021b000 0 0x1000>; }; infracfg_mem@1021c000 { compatible = "mediatek,infracfg_mem"; reg = <0 0x1021c000 0 0x1000>; }; infra_device_mpu@1021d000 { compatible = "mediatek,infra_device_mpu"; reg = <0 0x1021d000 0 0x1000>; }; infra_device_mpu@1021e000 { compatible = "mediatek,infra_device_mpu"; reg = <0 0x1021e000 0 0x1000>; }; apcldmain@1021f000 { compatible = "mediatek,apcldmain"; reg = <0 0x1021f000 0 0x1000>; }; apcldmaout@1021b400 { compatible = "mediatek,apcldmaout"; reg = <0 0x1021b400 0 0x400>; }; apcldmamisc@1021b800 { compatible = "mediatek,apcldmamisc"; reg = <0 0x1021b800 0 0x400>; }; apcldmamisc@1021bc00 { compatible = "mediatek,apcldmamisc"; reg = <0 0x1021bc00 0 0x400>; }; mdcldmain@1021c000 { compatible = "mediatek,mdcldmain"; reg = <0 0x1021c000 0 0x400>; }; mdcldmaout@1021c400 { compatible = "mediatek,mdcldmaout"; reg = <0 0x1021c400 0 0x400>; }; mdcldmamisc@1021c800 { compatible = "mediatek,mdcldmamisc"; reg = <0 0x1021c800 0 0x400>; }; mdcldmamisc@1021cc00 { compatible = "mediatek,mdcldmamisc"; reg = <0 0x1021cc00 0 0x400>; }; infra_md@1021d000 { compatible = "mediatek,infra_md"; reg = <0 0x1021d000 0 0x1000>; }; bpi_bsi_slv0@1021e000 { compatible = "mediatek,bpi_bsi_slv0"; reg = <0 0x1021e000 0 0x1000>; }; bpi_bsi_slv1@1021f000 { compatible = "mediatek,bpi_bsi_slv1"; reg = <0 0x1021f000 0 0x1000>; }; bpi_bsi_slv2@10225000 { compatible = "mediatek,bpi_bsi_slv2"; reg = <0 0x10225000 0 0x1000>; }; apdma@10220000 { compatible = "mediatek,apdma"; reg = <0 0x10220000 0 0x4000>; }; infra_device_mpu@10225000 { compatible = "mediatek,infra_device_mpu"; reg = <0 0x10225000 0 0x1000>; }; emimpu: emimpu@10226000 { compatible = "mediatek,mt6983-emimpu"; reg = <0 0x10226000 0 0x1000>, <0 0x10225000 0 0x1000>; mediatek,emi-reg = <&emicen>; mediatek,miukp-reg = <&miukp>; mediatek,miumpu-reg = <&miumpu>; interrupts = ; sr_cnt = <63>; aid_cnt = <256>; aid_num_per_set = <32>; dump = <0x1f0 0x1f8 0x1fc>; clear = <0x1f0 0x80000000 1>, <0x160 0xffffffff 16>, <0x200 0x00000003 16>; clear_hp = <0x1fc 0x40000000 1>; clear_md = <0x1fc 0x80000000 1>; }; infra_dpmaif@1022c000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022c000 0 0x1000>; }; infra_dpmaif@1022d000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022d000 0 0x1000>; }; infra_dpmaif@1022e000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022e000 0 0x1000>; }; infra_dpmaif@1022f000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022f000 0 0x1000>; }; dramc_ch0_top0@10230000 { compatible = "mediatek,dramc_ch0_top0"; reg = <0 0x10230000 0 0x2000>; }; dramc_ch0_top1@10232000 { compatible = "mediatek,dramc_ch0_top1"; reg = <0 0x10232000 0 0x2000>; }; dramc_ch0_top2@10234000 { compatible = "mediatek,dramc_ch0_top2"; reg = <0 0x10234000 0 0x1000>; }; dramc_ch0_top3@10235000 { compatible = "mediatek,dramc_ch0_top3"; reg = <0 0x10235000 0 0x1000>; }; dramc_ch0_top4@10236000 { compatible = "mediatek,dramc_ch0_top4"; reg = <0 0x10236000 0 0x2000>; }; dramc_ch0_top5@10238000 { compatible = "mediatek,dramc_ch0_top5"; reg = <0 0x10238000 0 0x2000>; }; dramc_ch0_top6@1023a000 { compatible = "mediatek,dramc_ch0_top6"; reg = <0 0x1023a000 0 0x2000>; }; ap-ccif2@1023c000 { compatible = "mediatek,ap_ccif2"; reg = <0 0x1023c000 0 0x1000>; }; md-ccif2@1023d000 { compatible = "mediatek,md_ccif2"; reg = <0 0x1023d000 0 0x1000>; }; ap_ccif3@1023e000 { compatible = "mediatek,ap_ccif3"; reg = <0 0x1023e000 0 0x1000>; }; md_ccif3@1023f000 { compatible = "mediatek,md_ccif3"; reg = <0 0x1023f000 0 0x1000>; }; dramc_ch1_top0@10240000 { compatible = "mediatek,dramc_ch1_top0"; reg = <0 0x10240000 0 0x2000>; }; dramc_ch1_top1@10242000 { compatible = "mediatek,dramc_ch1_top1"; reg = <0 0x10242000 0 0x2000>; }; dramc_ch1_top2@10244000 { compatible = "mediatek,dramc_ch1_top2"; reg = <0 0x10244000 0 0x1000>; }; dramc_ch1_top3@10245000 { compatible = "mediatek,dramc_ch1_top3"; reg = <0 0x10245000 0 0x1000>; }; dramc_ch1_top4@10246000 { compatible = "mediatek,dramc_ch1_top4"; reg = <0 0x10246000 0 0x2000>; }; dramc_ch1_top5@10248000 { compatible = "mediatek,dramc_ch1_top5"; reg = <0 0x10248000 0 0x2000>; }; dramc_ch1_top6@1024a000 { compatible = "mediatek,dramc_ch1_top6"; reg = <0 0x1024a000 0 0x2000>; }; ap_ccif4@1024c000 { compatible = "mediatek,ap_ccif4"; reg = <0 0x1024c000 0 0x1000>; }; md-ccif4@1024d000 { compatible = "mediatek,md_ccif4"; reg = <0 0x1024d000 0 0x1000>; }; ipi_apb@1024e000 { compatible = "mediatek,ipi_apb"; reg = <0 0x1024e000 0 0x2000>; }; dramc_ch2_top0@10250000 { compatible = "mediatek,dramc_ch2_top0"; reg = <0 0x10250000 0 0x2000>; }; dramc_ch2_top1@10252000 { compatible = "mediatek,dramc_ch2_top1"; reg = <0 0x10252000 0 0x2000>; }; dramc_ch2_top2@10254000 { compatible = "mediatek,dramc_ch2_top2"; reg = <0 0x10254000 0 0x1000>; }; dramc_ch2_top3@10255000 { compatible = "mediatek,dramc_ch2_top3"; reg = <0 0x10255000 0 0x1000>; }; dramc_ch2_top4@10256000 { compatible = "mediatek,dramc_ch2_top4"; reg = <0 0x10256000 0 0x2000>; }; dramc_ch2_top5@10258000 { compatible = "mediatek,dramc_ch2_top5"; reg = <0 0x10258000 0 0x2000>; }; dramc_ch2_top6@1025a000 { compatible = "mediatek,dramc_ch2_top6"; reg = <0 0x1025a000 0 0x2000>; }; ap_ccif5@1025c000 { compatible = "mediatek,ap_ccif5"; reg = <0 0x1025c000 0 0x1000>; }; md-ccif5@1025d000 { compatible = "mediatek,md_ccif5"; reg = <0 0x1025d000 0 0x1000>; }; mm_vpu_m0_sub_common@1025e000 { compatible = "mediatek,mm_vpu_m0_sub_common"; reg = <0 0x1025e000 0 0x1000>; }; mm_vpu_m1_sub_common@1025f000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1025f000 0 0x1000>; }; dramc_ch3_top0@10260000 { compatible = "mediatek,dramc_ch3_top0"; reg = <0 0x10260000 0 0x2000>; }; dramc_ch3_top1@10262000 { compatible = "mediatek,dramc_ch3_top1"; reg = <0 0x10262000 0 0x2000>; }; dramc_ch3_top2@10264000 { compatible = "mediatek,dramc_ch3_top2"; reg = <0 0x10264000 0 0x1000>; }; dramc_ch3_top3@10265000 { compatible = "mediatek,dramc_ch3_top3"; reg = <0 0x10265000 0 0x1000>; }; dramc_ch3_top4@10266000 { compatible = "mediatek,dramc_ch3_top4"; reg = <0 0x10266000 0 0x2000>; }; dramc_ch3_top5@10268000 { compatible = "mediatek,dramc_ch3_top5"; reg = <0 0x10268000 0 0x2000>; }; dramc_ch3_top6@1026a000 { compatible = "mediatek,dramc_ch3_top6"; reg = <0 0x1026a000 0 0x2000>; }; infracfg_ao_mem@10270000 { compatible = "mediatek,infracfg_ao_mem"; reg = <0 0x10270000 0 0x1000>; }; ssc_sub_infra_apb0@10309000 { compatible = "mediatek,ssc_sub_infra_apb0"; reg = <0 0x10309000 0 0x1000>; }; ssc_sub_infra_apb1@1030a000 { compatible = "mediatek,ssc_sub_infra_apb1"; reg = <0 0x1030a000 0 0x1000>; }; ssc_sub_infra_apb2@1030b000 { compatible = "mediatek,ssc_sub_infra_apb2"; reg = <0 0x1030b000 0 0x1000>; }; ssc_infra_apb2@1030c000 { compatible = "mediatek,ssc_infra_apb2"; reg = <0 0x1030c000 0 0x1000>; }; sys_cirq@10312000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10312000 0 0x1000>; }; sys_cirq@10313000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10313000 0 0x1000>; }; sys_cirq@10314000 { compatible = "mediatek,sys_cirq"; reg = <0 0x10314000 0 0x1000>; }; lvts: lvts@10315000 { compatible = "mediatek,mt6985-lvts"; #thermal-sensor-cells = <1>; reg = <0 0x10315000 0 0x1000>, <0 0x10316000 0 0x1000>, <0 0x13ff0000 0 0x1000>; interrupts = , , ; nvmem-cells = <&lvts_e_data1 &lvts_e_data2>; nvmem-cell-names = "e_data1","e_data2"; }; vtskin: vtskin { compatible = "mediatek,mt6985-virtual-tskin"; #thermal-sensor-cells = <1>; }; ptp_therm_ctrl_apb@10315000 { compatible = "mediatek,ptp_therm_ctrl_apb"; reg = <0 0x10315000 0 0x1000>; }; ptp_therm_ctrl2_apb@10316000 { compatible = "mediatek,ptp_therm_ctrl2_apb"; reg = <0 0x10316000 0 0x1000>; }; hwccf_apb@10320000 { compatible = "mediatek,hwccf_apb"; reg = <0 0x10320000 0 0x2000>; }; rsi_slb0_apb@10324000 { compatible = "mediatek,rsi_slb0_apb"; reg = <0 0x10324000 0 0x1000>; }; rsi_slb1_apb@10325000 { compatible = "mediatek,rsi_slb1_apb"; reg = <0 0x10325000 0 0x1000>; }; emi_m4_m_apb@10328000 { compatible = "mediatek,emi_m4_m_apb"; reg = <0 0x10328000 0 0x1000>; }; emi_m6_m_apb@10329000 { compatible = "mediatek,emi_m6_m_apb"; reg = <0 0x10329000 0 0x1000>; }; emi_m7_m_apb@1032a000 { compatible = "mediatek,emi_m7_m_apb"; reg = <0 0x1032a000 0 0x1000>; }; infra_bus_hre_apb@1032c000 { compatible = "mediatek,infra_bus_hre_apb"; reg = <0 0x1032c000 0 0x1000>; }; nemi_rsi_apb@10340000 { compatible = "mediatek,nemi_rsi_apb"; reg = <0 0x10340000 0 0x1000>; }; semi_rsi_apb@10341000 { compatible = "mediatek,semi_rsi_apb"; reg = <0 0x10341000 0 0x1000>; }; emislb: emislb@10342000 { compatible = "mediatek,common-emislb"; reg = <0 0x10342000 0 0x1000>, <0 0x10343000 0 0x1000>; interrupts = ; dump = <0xd14 0xd18 0xd1c 0xd20 0xd24>; clear = <0x680 0x80000000 1>; mpu_base_clear = <1>; }; nemi_hre_emi_apb@10344000 { compatible = "mediatek,nemi_hre_emi_apb"; reg = <0 0x10344000 0 0x1000>; }; semi_hre_emi_apb@10345000 { compatible = "mediatek,semi_hre_emi_apb"; reg = <0 0x10345000 0 0x1000>; }; nemi_hre_emi_mpu_apb@10346000 { compatible = "mediatek,nemi_hre_emi_mpu_apb"; reg = <0 0x10346000 0 0x1000>; }; semi_hre_emi_mpu_apb@10347000 { compatible = "mediatek,semi_hre_emi_mpu_apb"; reg = <0 0x10347000 0 0x1000>; }; nemi_hre_emi_slb_apb@10348000 { compatible = "mediatek,nemi_hre_emi_slb_apb"; reg = <0 0x10348000 0 0x1000>; }; semi_hre_emi_slb_apb@10349000 { compatible = "mediatek,semi_hre_emi_slb_apb"; reg = <0 0x10349000 0 0x1000>; }; nemi_hre_smpu_apb@1034a000 { compatible = "mediatek,nemi_hre_smpu_apb"; reg = <0 0x1034a000 0 0x1000>; }; semi_hre_smpu_apb@1034b000 { compatible = "mediatek,semi_hre_smpu_apb"; reg = <0 0x1034b000 0 0x1000>; }; nemi_smpu0@10350000 { compatible = "mediatek,nemi_smpu0"; reg = <0 0x10350000 0 0x1000>; }; nemi_smpu1@10351000 { compatible = "mediatek,nemi_smpu1"; reg = <0 0x10351000 0 0x1000>; }; miukp: miukp@10351000 { compatible = "mediatek,common-miukp"; reg = <0 0x10351000 0 0x1000>, <0 0x10355000 0 0x1000>; dump = <0xc00 0xc04 0xc10 0xc14>; clear = <0x410 0x1 1>, <0x410 0x0 1>; vio-info = <0x1 0xf 0x3 0xf>; }; miumpu: miumpu@10351000 { compatible = "mediatek,common-miumpu"; reg = <0 0x10351000 0 0x1000>, <0 0x10355000 0 0x1000>; dump = <0xe00 0xe08 0xe0c 0xe10 0xe14 0xe18 0xe1c 0xe20 0xe28 0xe80 0xe88 0xe8c 0xe90 0xe94 0xe98 0xe9c 0xea0 0xea8>; clear = <0xe00 0x1 1>, <0xe00 0x0 1>, <0xe80 0x1 1>, <0xe80 0x0 1>; vio-info = <0x0 0x2 0x9 0x2>; bypass = <0xe1c 0xe9c 0xe28 0xea8>; bypass-axi = <0x6 0xff80 0x4000 0x7 0xff01 0x4001>; }; nemi_smpu2@10352000 { compatible = "mediatek,nemi_smpu2"; reg = <0 0x10352000 0 0x1000>; }; semi_smpu0@10354000 { compatible = "mediatek,semi_smpu0"; reg = <0 0x10354000 0 0x1000>; }; semi_smpu1@10355000 { compatible = "mediatek,semi_smpu1"; reg = <0 0x10355000 0 0x1000>; }; semi_smpu2@10356000 { compatible = "mediatek,semi_smpu2"; reg = <0 0x10356000 0 0x1000>; }; pwrap_partition_0@10400000 { compatible = "mediatek,pwrap_partition_0"; reg = <0 0x10400000 0 0x100000>; }; pwrap_partition_1@10400000 { compatible = "mediatek,pwrap_partition_1"; reg = <0 0x10400000 0 0x1000>; }; pwrap_partition_2@10401000 { compatible = "mediatek,pwrap_partition_2"; reg = <0 0x10401000 0 0x1000>; }; pwrap_partition_3@10402000 { compatible = "mediatek,pwrap_partition_3"; reg = <0 0x10402000 0 0x1000>; }; pwrap_partition_4@10403000 { compatible = "mediatek,pwrap_partition_4"; reg = <0 0x10403000 0 0x1000>; }; pwrap_partition_5@10404000 { compatible = "mediatek,pwrap_partition_5"; reg = <0 0x10404000 0 0x1000>; }; pwrap_partition_6@10405000 { compatible = "mediatek,pwrap_partition_6"; reg = <0 0x10405000 0 0x1000>; }; pwrap_partition_7@10406000 { compatible = "mediatek,pwrap_partition_7"; reg = <0 0x10406000 0 0x1000>; }; pwrap_partition_8@10480000 { compatible = "mediatek,pwrap_partition_8"; reg = <0 0x10480000 0 0x10000>; }; pwrap_partition_9@10490000 { compatible = "mediatek,pwrap_partition_9"; reg = <0 0x10490000 0 0x10000>; }; pwrap_partition_10@104a0000 { compatible = "mediatek,pwrap_partition_10"; reg = <0 0x104a0000 0 0x20000>; }; pwrap_partition_11@104c0000 { compatible = "mediatek,pwrap_partition_11"; reg = <0 0x104c0000 0 0x40000>; }; dramc_md32_s0_apb@10900000 { compatible = "mediatek,dramc_md32_s0_apb"; reg = <0 0x10900000 0 0x40000>; }; dramc_md32_s0_apb@10940000 { compatible = "mediatek,dramc_md32_s0_apb"; reg = <0 0x10940000 0 0xc0000>; }; dramc_md32_s1_apb@10a00000 { compatible = "mediatek,dramc_md32_s1_apb"; reg = <0 0x10a00000 0 0x40000>; }; dramc_md32_s1_apb@10a40000 { compatible = "mediatek,dramc_md32_s1_apb"; reg = <0 0x10a40000 0 0xc0000>; }; dramc_md32_s2_apb@10b00000 { compatible = "mediatek,dramc_md32_s2_apb"; reg = <0 0x10b00000 0 0x40000>; }; dramc_md32_s2_apb@10b40000 { compatible = "mediatek,dramc_md32_s2_apb"; reg = <0 0x10b40000 0 0xc0000>; }; dramc_md32_s3_apb@10c00000 { compatible = "mediatek,dramc_md32_s3_apb"; reg = <0 0x10c00000 0 0x40000>; }; dramc_md32_s3_apb@10c40000 { compatible = "mediatek,dramc_md32_s3_apb"; reg = <0 0x10c40000 0 0xc0000>; }; gic500@0c000000 { compatible = "mediatek,gic500"; reg = <0 0x0c000000 0 0x400000>; }; gic_cpu@0c400000 { compatible = "mediatek,gic_cpu"; reg = <0 0x0c400000 0 0x40000>; }; dfd@0c600000 { compatible = "mediatek,dfd"; reg = <0 0x0c600000 0 0x100000>; }; dbg_cti@0d020000 { compatible = "mediatek,dbg_cti"; reg = <0 0x0d020000 0 0x10000>; }; dbg_etr@0d030000 { compatible = "mediatek,dbg_etr"; reg = <0 0x0d030000 0 0x1000>; }; bus_tracer@d040000 { compatible = "mediatek,bus_tracer-v1"; reg = <0 0x0d040000 0 0x1000>, /* dem base */ <0 0x0d01a000 0 0x1000>, /* dbgao base */ <0 0x0d041000 0 0x3000>, /* funnel/rep/etr base */ <0 0x0d044000 0 0x1000>, /* bus tracer etf base */ <0 0x0d040800 0 0x100>, /* ap bus tracer base */ <0 0x0d040900 0 0x100>; /* infra bus tracer base */ mediatek,err-flag = <0xffff00c3>; /* * index 0 for ap bus tracer * index 1 for infra bus tracer */ mediatek,num-tracer = <2>; mediatek,enabled-tracer = <0 1>; mediatek,at-id = <0x10 0x30>; /* filters: disabled by default */ /* * mediatek,watchpoint-filter = <0x0 0x10010000 0xfffff000>; * mediatek,bypass-filter = <0x14000000 0xffff0000>; * mediatek,id-filter = <0x10 0x40>; * mediatek,rw-filter = <0x0 0x1>; */ }; dbg_dem@0d0a0000 { compatible = "mediatek,dbg_dem"; reg = <0 0x0d0a0000 0 0x10000>; interrupts = ; }; dbg_mdsys1@0d100000 { compatible = "mediatek,dbg_mdsys1"; reg = <0 0x0d100000 0 0x100000>; }; pwm@11008000 { compatible = "mediatek,pwm"; reg = <0 0x11008000 0 0x1000>; interrupts = ; clocks = <&pericfg_ao_clk CLK_PERAO_PWM_FB1>, <&pericfg_ao_clk CLK_PERAO_PWM_FB2>, <&pericfg_ao_clk CLK_PERAO_PWM_FB3>, <&pericfg_ao_clk CLK_PERAO_PWM_FB4>, <&pericfg_ao_clk CLK_PERAO_PWM_H>, <&pericfg_ao_clk CLK_PERAO_PWM_B>; clock-names = "PWM1-main", "PWM2-main", "PWM3-main", "PWM4-main", "PWM-HCLK-main", "PWM-main"; /* 1. pwm periclk control reg offset */ mediatek,pwm-topclk-ctl-reg = <0x20>; /* 2. pwm bclk sw ctrl offset */ mediatek,pwm-bclk-sw-ctrl-offset = <12>; /* 3. pwm_x bclk sw ctrl offset */ mediatek,pwm1-bclk-sw-ctrl-offset = <20>; mediatek,pwm2-bclk-sw-ctrl-offset = <18>; mediatek,pwm3-bclk-sw-ctrl-offset = <16>; mediatek,pwm4-bclk-sw-ctrl-offset = <14>; /* 4. pwm version */ mediatek,pwm-version = <0x2>; pwmsrcclk = <&pericfg_ao_clk>; }; irtx_pwm:irtx-pwm { compatible = "mediatek,irtx-pwm"; pwm-ch = <3>; pwm-data-invert = <0>; pwm-supply = "mt6373_vio28"; }; peri_imp_iic_wrap@11b70000 { compatible = "mediatek,peri_imp_iic_wrap"; reg = <0 0x11b70000 0 0x10000>; }; peri_efusec@11c10000 { compatible = "mediatek,peri_efusec"; reg = <0 0x11c10000 0 0x10000>; }; peri_io_cfg_rm@11c20000 { compatible = "mediatek,peri_io_cfg_rm"; reg = <0 0x11c20000 0 0x10000>; }; peri_io_rb@11c30000 { compatible = "mediatek,peri_io_rb"; reg = <0 0x11c30000 0 0x10000>; }; peri_io_cfg_rt@11c50000 { compatible = "mediatek,peri_io_cfg_rt"; reg = <0 0x11c50000 0 0x10000>; }; peri_msdc1_pad_macro@11c70000 { compatible = "mediatek,peri_msdc1_pad_macro"; reg = <0 0x11c70000 0 0x10000>; }; peri_csi_top_ao@11c80000 { compatible = "mediatek,peri_csi_top_ao"; reg = <0 0x11c80000 0 0x10000>; }; peri_csi_top_ao@11c90000 { compatible = "mediatek,peri_csi_top_ao"; reg = <0 0x11c90000 0 0x10000>; }; peri_imp_iic_wrap@11cb0000 { compatible = "mediatek,peri_imp_iic_wrap"; reg = <0 0x11cb0000 0 0x10000>; }; eint: apirq@11ce0000 { compatible = "mediatek,mt6983-eint"; reg = <0 0x11ce0000 0 0x1000>, <0 0x11de0000 0 0x1000>, <0 0x11fe0000 0 0x1000>, <0 0x1c01e000 0 0x1000>; reg-name = "eint-e", "eint-s", "eint-n", "eint-c"; interrupts = ; mediatek,instance-num = <4>; mediatek,total-pin-number = <254>; mediatek,pins = <0 2 0 0>,<1 2 1 0>,<2 2 2 0>,<3 2 3 0>, <4 2 4 1>,<5 2 5 1>,<6 2 6 1>,<7 2 7 1>, <8 2 8 1>,<9 2 9 1>,<10 2 10 1>,<11 2 11 1>, <12 1 70 0>,<13 1 71 0>,<14 1 72 0>,<15 1 73 0>, <16 1 4 0>,<17 1 5 0>,<18 1 6 0>,<19 1 7 0>, <20 2 12 1>,<21 2 13 1>,<22 2 14 1>,<23 2 15 1>, <24 2 16 1>,<25 2 17 1>,<26 2 18 1>,<27 2 19 1>, <28 2 20 1>,<29 2 21 1>,<30 1 8 1>,<31 1 9 1>, <32 1 10 1>,<33 1 11 1>,<34 2 22 1>,<35 2 23 1>, <36 2 24 1>,<37 2 25 1>,<55 2 41 0>,<56 2 42 0>, <57 2 28 0>,<58 2 29 0>,<59 2 30 0>,<60 2 31 0>, <61 2 32 0>,<62 2 33 0>,<63 2 34 0>,<64 2 35 0>, <65 2 36 0>,<66 2 37 0>,<67 2 38 0>,<68 2 39 0>, <69 2 40 0>,<72 2 26 0>,<73 2 27 0>,<74 1 12 0>, <75 1 13 0>,<76 1 14 0>,<77 1 15 0>,<78 2 43 0>, <79 2 44 0>,<80 2 45 0>,<81 2 46 0>,<82 2 47 0>, <83 2 48 0>,<84 2 49 0>,<85 2 50 0>,<86 2 51 0>, <87 2 52 0>,<88 2 53 0>,<103 1 16 0>,<104 1 17 0>, <105 1 18 0>,<106 1 19 0>,<107 1 20 0>,<108 1 21 0>, <109 1 22 0>,<110 1 23 0>,<111 1 24 0>,<112 1 25 0>, <113 1 26 0>,<116 1 27 0>,<117 1 28 0>,<120 1 29 0>, <121 1 30 0>,<122 1 31 0>,<123 1 32 0>,<124 1 33 0>, <133 1 34 0>,<134 1 35 0>,<135 1 36 0>,<136 1 37 0>, <137 1 38 0>,<138 1 39 0>,<139 1 40 0>,<140 1 41 0>, <141 1 42 0>,<142 1 43 0>,<143 1 44 0>,<144 1 45 0>, <145 1 46 0>,<146 1 47 0>,<147 1 48 0>,<148 1 49 0>, <149 1 50 0>,<150 1 51 0>,<151 1 52 0>,<152 1 53 0>, <153 1 54 0>,<154 1 55 0>,<155 1 56 0>,<156 1 57 0>, <157 1 58 0>,<158 1 59 0>,<159 1 60 0>,<160 1 61 0>, <161 1 62 0>,<162 1 63 0>,<163 1 64 0>,<164 2 54 0>, <165 2 55 0>,<166 2 56 0>,<167 2 57 0>,<168 2 58 0>, <169 2 59 0>,<170 2 60 0>,<171 2 61 0>,<172 1 65 0>, <177 1 66 0>,<178 1 67 0>,<179 1 68 0>,<180 1 69 0>, <187 1 0 1>,<188 1 1 1>,<189 1 2 1>,<190 1 3 1>, <191 1 74 0>,<192 1 75 0>,<193 1 76 0>,<194 1 77 0>, <195 1 78 0>,<196 1 79 0>,<197 1 80 0>,<198 1 81 0>, <199 1 82 0>,<200 1 83 0>,<201 1 84 0>,<208 1 85 0>, <209 1 86 0>,<210 1 87 0>,<221 0 0 0>,<222 0 1 0>, <223 0 2 0>,<224 0 3 0>,<225 0 4 0>,<226 2 62 0>, <227 2 63 0>,<228 0 5 0>,<229 0 6 0>,<230 2 64 0>, <231 2 65 0>,<232 2 66 0>,<233 2 67 0>,<234 2 68 0>, <235 0 7 0>,<236 0 8 0>,<237 0 9 0>,<238 0 10 0>, <239 2 69 0>,<240 2 70 0>,<241 2 71 0>,<242 3 0 0>, <243 3 1 0>,<244 3 2 0>,<245 3 3 0>,<246 3 4 0>, <247 3 5 0>,<248 3 6 0>,<249 3 7 0>,<250 3 8 0>, <251 3 12 0>,<252 3 13 0>,<253 3 16 0>; }; peri_imp_iic_wrap@11d00000 { compatible = "mediatek,peri_imp_iic_wrap"; reg = <0 0x11d00000 0 0x10000>; }; peri_io_cfg_bm@11d10000 { compatible = "mediatek,peri_io_cfg_bm"; reg = <0 0x11d10000 0 0x10000>; }; peri_imp_iic_wrap@11d20000 { compatible = "mediatek,peri_imp_iic_wrap"; reg = <0 0x11d20000 0 0x10000>; }; peri_io_bl@11d30000 { compatible = "mediatek,peri_io_bl"; reg = <0 0x11d30000 0 0x10000>; }; peri_io_br@11d40000 { compatible = "mediatek,peri_io_br"; reg = <0 0x11d40000 0 0x10000>; }; peri_imp_iic_wrap@11e00000 { compatible = "mediatek,peri_imp_iic_wrap"; reg = <0 0x11e00000 0 0x10000>; }; peri_io_cfg_lt@11e10000 { compatible = "mediatek,peri_io_cfg_lt"; reg = <0 0x11e10000 0 0x10000>; }; peri_io_cfg_lm@11e20000 { compatible = "mediatek,peri_io_cfg_lm"; reg = <0 0x11e20000 0 0x10000>; }; peri_usbsif_top@11e30000 { compatible = "mediatek,peri_usbsif_top"; reg = <0 0x11e30000 0 0x10000>; }; peri_usbsif_top@11e40000 { compatible = "mediatek,peri_usbsif_top"; reg = <0 0x11e40000 0 0x10000>; }; peri_mipi_tx_cfg@11e50000 { compatible = "mediatek,peri_mipi_tx_cfg"; reg = <0 0x11e50000 0 0x10000>; }; peri_mipi_tx_cfg@11e60000 { compatible = "mediatek,peri_mipi_tx_cfg"; reg = <0 0x11e60000 0 0x10000>; }; peri_io_cfg_lb@11e70000 { compatible = "mediatek,peri_io_cfg_lb"; reg = <0 0x11e70000 0 0x10000>; }; peri_pextp_phy_top@11e90000 { compatible = "mediatek,peri_pextp_phy_top"; reg = <0 0x11e90000 0 0x10000>; }; peri_xtp_ckm_top@11ea0000 { compatible = "mediatek,peri_xtp_ckm_top"; reg = <0 0x11ea0000 0 0x10000>; }; peri_io_cfg_rt@11eb0000 { compatible = "mediatek,peri_io_cfg_rt"; reg = <0 0x11eb0000 0 0x10000>; }; peri_imp_iic_wrap@11f00000 { compatible = "mediatek,peri_imp_iic_wrap"; reg = <0 0x11f00000 0 0x10000>; }; peri_efusec@11f10000 { compatible = "mediatek,peri_efusec"; reg = <0 0x11f10000 0 0x10000>; }; peri_io_cfg_tr@11f20000 { compatible = "mediatek,peri_io_cfg_tr"; reg = <0 0x11f20000 0 0x10000>; }; peri_io_cfg_tm@11f30000 { compatible = "mediatek,peri_io_cfg_tm"; reg = <0 0x11f30000 0 0x10000>; }; peri_io_cfg_tl@11f40000 { compatible = "mediatek,peri_io_cfg_tl"; reg = <0 0x11f40000 0 0x10000>; }; peri_msdc0_pad_macro@11f50000 { compatible = "mediatek,peri_msdc0_pad_macro"; reg = <0 0x11f50000 0 0x10000>; }; peri_ufs_glb_dig@11fa0000 { compatible = "mediatek,peri_ufs_glb_dig"; reg = <0 0x11fa0000 0 0x10000>; }; peri_ufs_glb_ana@11fa1000 { compatible = "mediatek,peri_ufs_glb_ana"; reg = <0 0x11fa1000 0 0x1000>; }; peri_ufs_glb_mib@11fa2000 { compatible = "mediatek,peri_ufs_glb_mib"; reg = <0 0x11fa2000 0 0x1000>; }; peri_ufs_glb_pll@11fa3000 { compatible = "mediatek,peri_ufs_glb_pll"; reg = <0 0x11fa3000 0 0x1000>; }; peri_ufs_glb_cdr@11fa4000 { compatible = "mediatek,peri_ufs_glb_cdr"; reg = <0 0x11fa4000 0 0x1000>; }; peri_ufs_ln_dig_tx@11fa8000 { compatible = "mediatek,peri_ufs_ln_dig_tx"; reg = <0 0x11fa8000 0 0x1000>; }; peri_ufs_ln_ana_tx@11fa9000 { compatible = "mediatek,peri_ufs_ln_ana_tx"; reg = <0 0x11fa9000 0 0x1000>; }; peri_ufs_ln_dig_rx@11faa000 { compatible = "mediatek,peri_ufs_ln_dig_rx"; reg = <0 0x11faa000 0 0x1000>; }; peri_ufs_ln_ana_rx@11fab000 { compatible = "mediatek,peri_ufs_ln_ana_rx"; reg = <0 0x11fab000 0 0x1000>; }; dcm: dcm@1002c000 { compatible = "mediatek,mt6985-dcm"; reg = <0 0x1002c000 0 0x1000>, <0 0x10324000 0 0x1000>, <0 0x10330000 0 0x1000>, <0 0x11035000 0 0x1000>, <0 0x112ba000 0 0x1000>, <0 0x112e2000 0 0x1000>, <0 0x1c017000 0 0x1000>, <0 0xc000000 0 0x10000>, <0 0xc040000 0 0x10000>, <0 0xc18c000 0 0x10000>, <0 0xc1ac000 0 0x10000>; reg-names = "ifrbus_ao", "ifrrsi", "ifriommu", "peri_ao_bcrm", "ufs0_ao_bcrm", "pcie0_ao_bcrm", "vlp_ao_bcrm", "mcusys_par_wrap", "mcusys_cpc", "mcusys_par_wrap_complex0", "mcusys_par_wrap_complex1"; }; spi0: spi0@11010000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <0>; reg = <0 0x11010000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI0_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi1: spi1@11011000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <0>; reg = <0 0x11011000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI1_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi2: spi2@11012000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <0>; reg = <0 0x11012000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI2_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi3: spi3@11013000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <0>; reg = <0 0x11013000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI3_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi4: spi4@11014000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <0>; reg = <0 0x11014000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI4_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi5: spi5@11015000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <0>; reg = <0 0x11015000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI5_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi6: spi6@11016000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <1>; reg = <0 0x11016000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI6_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi7: spi7@11017000 { compatible = "mediatek,mt6985-spi"; mediatek,pad-select = <1>; reg = <0 0x11017000 0 0x100>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>, <&topckgen_clk CLK_TOP_SPI_SEL>, <&pericfg_ao_clk CLK_PERAO_SPI7_B>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; goodix_fp: fingerprint { compatible = "mediatek,goodix-fp"; }; apu_top_3: apu_top_3 { compatible = "mt6985,apu_top_3"; reg = <0 0x1c000000 0 0x1000>, // sys_vlp <0 0x1c001000 0 0x1000>, // sys_spm <0 0x19020000 0 0x1000>, // apu_rcx <0 0x190e0000 0 0x4000>, // apu_vcore <0 0x190e1000 0 0x2000>, // apu_md32_mbox <0 0x190f0000 0 0x1000>, // apu_rpc <0 0x190f1000 0 0x1000>, // apu_pcu <0 0x190f2000 0 0x1000>, // apu_ao_ctl <0 0x190f3000 0 0x3000>, // apu_pll <0 0x190f3000 0 0x3000>, // apu_acc <0 0x190f6000 0 0x4000>, // apu_are <0 0x19100000 0 0x40000>, // apu_acx0 <0 0x19140000 0 0x1000>, // apu_acx0_rpc_lite <0 0x19200000 0 0x40000>, // apu_acx1 <0 0x19240000 0 0x1000>, // apu_acx1_rpc_lite <0 0x19300000 0 0x40000>, // apu_ncx <0 0x19340000 0 0x1000>; // apu_ncx_rpc_lite reg-names = "sys_vlp", "sys_spm", "apu_rcx", "apu_vcore", "apu_md32_mbox", "apu_rpc", "apu_pcu", "apu_ao_ctl", "apu_pll", "apu_acc", "apu_are", "apu_acx0", "apu_acx0_rpc_lite", "apu_acx1", "apu_acx1_rpc_lite", "apu_ncx", "apu_ncx_rpc_lite"; }; apusys_rv: apusys-rv@190e1000 { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek,mt6985-apusys_rv"; status = "okay"; reg = <0 0x190e1000 0 0x1000>, <0 0x19001000 0 0x1000>, <0 0x19002000 0 0x10>, <0 0x1903c000 0 0x8000>, <0 0x19050000 0 0x10000>, <0 0x190f2000 0 0x1000>, <0 0x1d000000 0 0x20000>, <0 0x0d298000 0 0x10000>; reg-names = "apu_mbox", "md32_sysctrl", "apu_wdt", "apu_sctrl_reviser", "md32_cache_dump", "apu_ao_ctl", "md32_tcm", "md32_debug_apb"; mediatek,apusys_power = <&apu_top_3>; apu-iommu0 = <&apu_iommu0>; apu-iommu1 = <&apu_iommu1>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; iommus = <&apu_iommu0 M4U_PORT_L40_APU_CODE>; interrupts = , , ; interrupt-names = "apu_wdt", "mbox0_irq", "mbox1_irq"; up-code-buf-sz = <0x100000>; up-coredump-buf-sz = <0x180000>; regdump-buf-sz = <0x10000>; mdla-coredump-buf-sz = <0x0>; mvpu-coredump-buf-sz = <0x0>; mvpu-sec-coredump-buf-sz = <0x0>; apu-ctrl { compatible = "mediatek,apu-ctrl-rpmsg"; mtk,rpmsg-name = "apu-ctrl-rpmsg"; }; apu-top-rpmsg { compatible = "mediatek,aputop-rpmsg"; mtk,rpmsg-name = "apu_top_3_rpmsg"; }; apu-mdw-rpmsg { compatible = "mediatek,apu-mdw-rpmsg"; mtk,rpmsg-name = "apu-mdw-rpmsg"; }; apu-reviser { compatible = "mediatek,apu-reviser-rpmsg"; mtk,rpmsg-name = "apu-reviser-rpmsg"; }; apu-edma { compatible = "mediatek,apu-edma-rpmsg"; mtk,rpmsg-name = "apu-edma-rpmsg"; }; apu-mnoc { compatible = "mediatek,apu-mnoc-rpmsg"; mtk,rpmsg-name = "apu-mnoc-rpmsg"; }; mdla-tx-rpmsg { compatible = "mediatek,mdla-tx-rpmsg"; mtk,rpmsg-name = "mdla-tx-rpmsg"; }; mdla-rx-rpmsg { compatible = "mediatek,mdla-rx-rpmsg"; mtk,rpmsg-name = "mdla-rx-rpmsg"; }; mvpu-tx-rpmsg { compatible = "mediatek,mvpu-tx-rpmsg"; mtk,rpmsg-name = "mvpu-tx-rpmsg"; }; mvpu-rx-rpmsg { compatible = "mediatek,mvpu-rx-rpmsg"; mtk,rpmsg-name = "mvpu-rx-rpmsg"; }; aps-tx-rpmsg { compatible = "mediatek,aps-tx-rpmsg"; mtk,rpmsg-name = "aps-tx-rpmsg"; }; aps-rx-rpmsg { compatible = "mediatek,aps-rx-rpmsg"; mtk,rpmsg-name = "aps-rx-rpmsg"; }; sapu-lock-rpmsg { compatible = "mediatek,apu-lock-rv-rpmsg"; mtk,rpmsg-name = "apu-lock-rv-rpmsg"; }; apu-scp-mdw-rpmsg { compatible = "mediatek,apu-scp-mdw-rpmsg"; mtk,rpmsg-name = "apu-scp-mdw-rpmsg"; }; apu-scp-np-recover-rpmsg { compatible = "mediatek,apu-scp-np-recover-rpmsg"; mtk,rpmsg-name = "apu-scp-np-recover-rpmsg"; }; }; apusys-hw-logger@19024000 { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek,apusys_hw_logger"; status = "okay"; reg = <0 0x19024000 0 0x1000>, <0 0x190e1000 0 0x1000>; reg-names = "apu_logtop", "apu_mbox"; interrupts = ; interrupt-names = "apu_logtop"; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; iommus = <&apu_iommu1 M4U_PORT_L40_APU_CODE>; aov-log-buf-sz = <0x100000>; }; mtk_apu_mem_code: mtk-apu-mem-code { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek, apu_mem_code"; status = "okay"; type = <1>; mask = /bits/ 64 <0x00000003ffffffff>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; iommus = <&apu_iommu0 M4U_PORT_L40_APU_CODE>; }; mtk_apu_mem_data: mtk-apu-mem-data { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek, apu_mem_data"; status = "okay"; type = <2>; mask = /bits/ 64 <0x00000003ffffffff>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&apu_iommu1 M4U_PORT_L40_APU_DATA>; }; apusys-reviser@1903c000 { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek, rv-reviser"; reg = <0 0x1903c000 0 0x1000>, /* apu_sctrl_reviser */ <0 0x02000000 0 0xc00000>, /* VLM */ <0 0x1d900000 0 0x600000>, /* TCM */ <0 0x19001000 0 0x1000>; /* apusys int */ //interrupts = ; default-dram = <0x0>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; boundary = <0x0>; iommus = <&apu_iommu0 M4U_PORT_L40_APU_CODE>; }; mdla { compatible = "mediatek, mdla-rv"; core-num = <4>; version = <0x69850305>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x0>; iommus = <&apu_iommu0 M4U_PORT_L40_APU_CODE>; }; mvpu { compatible = "mediatek, mt6985-mvpu"; core-num = <2>; version = <0x0>; mask = /bits/ 64 <0x00000003ffffffff>; iommus = <&apu_iommu0 M4U_PORT_L40_APU_CODE>; }; apusys-aov { compatible = "mediatek,apusys_aov"; }; i2c0: i2c@11f00000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11f00000 0 0x1000>, <0 0x11300200 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_n_clk CLK_IMPN_I2C0>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <78>; sda-gpio-id = <79>; }; i2c1: i2c@11d00000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11d00000 0 0x1000>, <0 0x11300280 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C1>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <173>; sda-gpio-id = <174>; }; i2c2: i2c@11d01000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11d01000 0 0x1000>, <0 0x11300300 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C2>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; ch-offset-i2c = <0x100>; ch-offset-scp = <0x200>; ch-offset-ch3 = <0x300>; scl-gpio-id = <185>; sda-gpio-id = <186>; }; i2c3: i2c@11d02000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11d02000 0 0x1000>, <0 0x11300480 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C3>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <175>; sda-gpio-id = <176>; }; i2c4: i2c@11d03000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11d03000 0 0x1000>, <0 0x11300500 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C4>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <183>; sda-gpio-id = <184>; }; i2c5: i2c@11280000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11280000 0 0x1000>, <0 0x11300680 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_c_clk CLK_IMPC_I2C5>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <82>; sda-gpio-id = <83>; }; i2c6: i2c@11f01000 { compatible = "mediatek,mt6983-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x11f01000 0 0x1000>, <0 0x11300700 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_n_clk CLK_IMPN_I2C6>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <80>; sda-gpio-id = <81>; }; i2c7: i2c@11d04000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11d04000 0 0x1000>, <0 0x11300780 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C7>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; ch-offset-i2c = <0x100>; ch-offset-scp = <0x200>; ch-offset-ch3 = <0x300>; scl-gpio-id = <181>; sda-gpio-id = <182>; }; i2c8: i2c@11d05000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11d05000 0 0x1000>, <0 0x11300900 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C8>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; ch-offset-i2c = <0x100>; ch-offset-scp = <0x200>; ch-offset-ch3 = <0x300>; scl-gpio-id = <179>; sda-gpio-id = <180>; }; i2c9: i2c@11d06000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11d06000 0 0x1000>, <0 0x11300a80 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C9>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <177>; sda-gpio-id = <178>; }; i2c10: i2c@11f02000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11f02000 0 0x1000>, <0 0x11300c00 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_n_clk CLK_IMPN_I2C10>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <72>; sda-gpio-id = <73>; }; i2c11: i2c@11f03000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11f03000 0 0x1000>, <0 0x11300c80 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_n_clk CLK_IMPN_I2C11>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <70>; sda-gpio-id = <71>; }; i2c12: i2c@11f04000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11f04000 0 0x1000>, <0 0x11300d00 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_n_clk CLK_IMPN_I2C12>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <135>; sda-gpio-id = <136>; }; i2c13: i2c@11f05000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x11f05000 0 0x1000>, <0 0x11300e80 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_n_clk CLK_IMPN_I2C13>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; scl-gpio-id = <137>; sda-gpio-id = <138>; }; scp_i2c1: i2c@1c7b1000 { compatible = "mediatek,mt6983-i2c"; reg = <0 0x1c7b1000 0 0x1000>, <0 0x1c753180 0 0x100>; interrupts = ; clocks = <&scp_iic_clk CLK_SCP_IIC_I2C1>, <&pericfg_ao_clk CLK_PERAO_DMA_B>; clock-names = "main", "dma"; clock-div = <1>; clk_src_in_hz = <130000000>; ch-offset-i2c = <0x200>; ch-offset-dma = <0x80>; scl-gpio-id = <49>; sda-gpio-id = <50>; }; dvfsrc: dvfsrc@1c00f000 { compatible = "mediatek,mt6985-dvfsrc"; reg = <0 0x1c00f000 0 0x1000>, <0 0x1c001000 0 0x1000>; reg-names = "dvfsrc", "spm"; #interconnect-cells = <1>; disable-wait-level; dvfsrc_vcore: dvfsrc-vcore { regulator-name = "dvfsrc-vcore"; regulator-min-microvolt = <575000>; regulator-max-microvolt = <825000>; regulator-always-on; }; dvfsrc_freq_opp8: opp8 { opp-peak-KBps = <0>; }; dvfsrc_freq_opp7: opp7 { opp-peak-KBps = <5120000>; }; dvfsrc_freq_opp6: opp6 { opp-peak-KBps = <10200000>; }; dvfsrc_freq_opp5: opp5 { opp-peak-KBps = <11900000>; }; dvfsrc_freq_opp4: opp4 { opp-peak-KBps = <13600000>; }; dvfsrc_freq_opp3: opp3 { opp-peak-KBps = <19800000>; }; dvfsrc_freq_opp2: opp2 { opp-peak-KBps = <26200000>; }; dvfsrc_freq_opp1: opp1 { opp-peak-KBps = <35200000>; }; dvfsrc_freq_opp0: opp0 { opp-peak-KBps = <40900000>; }; dvfsrc-helper { compatible = "mediatek,dvfsrc-helper"; vcore-supply = <&mt6363_vbuck6>; rc-vcore-supply = <&dvfsrc_vcore>; interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_HRT_DBGIF &dvfsrc MT6873_SLAVE_HRT_DDR_EMI>; interconnect-names = "icc-bw", "icc-perf-bw", "icc-hrt-bw"; required-opps = <&dvfsrc_freq_opp0>, <&dvfsrc_freq_opp1>, <&dvfsrc_freq_opp2>, <&dvfsrc_freq_opp3>, <&dvfsrc_freq_opp4>, <&dvfsrc_freq_opp5>, <&dvfsrc_freq_opp6>, <&dvfsrc_freq_opp7>; }; dvfsrc-met { rc-vcore-supply = <&dvfsrc_vcore>; interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_HRT_DBGIF &dvfsrc MT6873_SLAVE_HRT_DDR_EMI>; interconnect-names = "icc-bw", "icc-hrt-bw"; compatible = "mediatek,dvfsrc-met"; }; }; dfd@13600000 { compatible = "mediatek,dfd"; reg = <0 0x13600000 0 0x200000>; }; dfd@13800000 { compatible = "mediatek,dfd"; reg = <0 0x13800000 0 0x200000>; }; i2c@14220000 { compatible = "mediatek,i2c"; reg = <0 0x14220000 0 0x1000>; }; ovlsys_config@14400000 { compatible = "mediatek,ovlsys_config"; reg = <0 0x14400000 0 0x1000>; }; aov: aov@0 { compatible = "mediatek,aov"; status = "okay"; op_mode = <1>; }; hcp: hcp@0 { compatible = "mediatek,hcp7s"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L15_VIPI_D1>; }; imgsys_cmdq: imgsys_cmdq@0 { compatible = "mediatek,imgsys-cmdq-7s"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L15_VIPI_D1>; }; imgsys_fw: imgsys_fw@15000000 { compatible = "mediatek,imgsys-isp7s"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; reg = <0 0x15000000 0 0x4000>, /* 0 IMGSYS_TOP */ <0 0x15700000 0 0x10000>, /* 1 IMGSYS_TRAW */ <0 0x15040000 0 0x10000>, /* 2 IMGSYS_LTRAW */ <0 0x15100000 0 0x10000>, /* 3 IMGSYS_DIP */ <0 0x15150000 0 0x10000>, /* 4 IMGSYS_DIP_NR */ <0 0x15160000 0 0x10000>, /* 5 IMGSYS_DIP_NR2 */ <0 0x15210000 0 0x10000>, /* 6 IMGSYS_PQDIP_A */ <0 0x15510000 0 0x10000>, /* 7 IMGSYS_PQDIP_B */ <0 0x15200000 0 0x10000>, /* 8 IMGSYS_WPE_EIS */ <0 0x15500000 0 0x10000>, /* 9 IMGSYS_WPE_TNR */ <0 0x15600000 0 0x10000>, /* 10 IMGSYS_WPE_LITE */ <0 0x15220000 0 0x00100>, /* 11 IMGSYS_WPE1_DIP1 */ <0 0x15320000 0 0x10000>, /* 12 IMGSYS_ME */ <0 0x00000000 0 0x01500>, /* 13 IMGSYS_ADL_A */ <0 0x00000000 0 0x01500>, /* 14 IMGSYS_ADL_B */ <0 0x15520000 0 0x00100>, /* 15 IMGSYS_WPE2_DIP1 */ <0 0x15620000 0 0x00100>, /* 16 IMGSYS_WPE3_DIP1 */ <0 0x15110000 0 0x00100>, /* 17 IMGSYS_DIP_TOP */ <0 0x15130000 0 0x00100>, /* 18 IMGSYS_DIP_TOP_NR */ <0 0x15170000 0 0x00100>, /* 19 IMGSYS_DIP_TOP_NR2 */ <0 0x15710000 0 0x00100>, /* 20 IMGSYS_TRAW_DIP1 */ <0 0x15330000 0 0x10000>; /* 21 IMGSYS_ME_MMG */ power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; mediatek,hcp = <&hcp>; mediatek,larbs = <&smi_larb9>, <&smi_larb10>, <&smi_larb11>, <&smi_larb15>, <&smi_larb22>, <&smi_larb23>, <&smi_larb28>, <&smi_larb18>, <&smi_larb12>; mediatek,imgsys_cmdq = <&imgsys_cmdq>; iommus = <&disp_iommu M4U_PORT_L28_IMGI_T1_A>; mboxes = <&gce_m 0 3000 CMDQ_THR_PRIO_2>, <&gce_m 1 3000 CMDQ_THR_PRIO_2>, <&gce_m 2 3000 CMDQ_THR_PRIO_2>, <&gce_m 3 3000 CMDQ_THR_PRIO_2>, <&gce_m 4 3000 CMDQ_THR_PRIO_2>, <&gce_m 5 3000 CMDQ_THR_PRIO_2>, <&gce_m 16 3000 CMDQ_THR_PRIO_2>, <&gce_m 17 3000 CMDQ_THR_PRIO_2>, <&gce_m 18 3000 CMDQ_THR_PRIO_2>, <&gce_m 19 3000 CMDQ_THR_PRIO_1>, <&gce_m 22 3000 CMDQ_THR_PRIO_1>, <&gce_m 23 3000 CMDQ_THR_PRIO_1>, <&gce_m_sec 10 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>, <&gce_m_sec 12 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>; traw_cq_thread0_frame_done = /bits/ 16 ; traw_cq_thread1_frame_done = /bits/ 16 ; traw_cq_thread2_frame_done = /bits/ 16 ; traw_cq_thread3_frame_done = /bits/ 16 ; traw_cq_thread4_frame_done = /bits/ 16 ; traw_cq_thread5_frame_done = /bits/ 16 ; traw_cq_thread6_frame_done = /bits/ 16 ; traw_cq_thread7_frame_done = /bits/ 16 ; traw_cq_thread8_frame_done = /bits/ 16 ; traw_cq_thread9_frame_done = /bits/ 16 ; ltraw_cq_thread0_frame_done = /bits/ 16 ; ltraw_cq_thread1_frame_done = /bits/ 16 ; ltraw_cq_thread2_frame_done = /bits/ 16 ; ltraw_cq_thread3_frame_done = /bits/ 16 ; ltraw_cq_thread4_frame_done = /bits/ 16 ; ltraw_cq_thread5_frame_done = /bits/ 16 ; ltraw_cq_thread6_frame_done = /bits/ 16 ; ltraw_cq_thread7_frame_done = /bits/ 16 ; ltraw_cq_thread8_frame_done = /bits/ 16 ; ltraw_cq_thread9_frame_done = /bits/ 16 ; dip_cq_thread0_frame_done = /bits/ 16 ; dip_cq_thread1_frame_done = /bits/ 16 ; dip_cq_thread2_frame_done = /bits/ 16 ; dip_cq_thread3_frame_done = /bits/ 16 ; dip_cq_thread4_frame_done = /bits/ 16 ; dip_cq_thread5_frame_done = /bits/ 16 ; dip_cq_thread6_frame_done = /bits/ 16 ; dip_cq_thread7_frame_done = /bits/ 16 ; dip_cq_thread8_frame_done = /bits/ 16 ; dip_cq_thread9_frame_done = /bits/ 16 ; pqa_cq_thread0_frame_done = /bits/ 16 ; pqa_cq_thread1_frame_done = /bits/ 16 ; pqa_cq_thread2_frame_done = /bits/ 16 ; pqa_cq_thread3_frame_done = /bits/ 16 ; pqa_cq_thread4_frame_done = /bits/ 16 ; pqa_cq_thread5_frame_done = /bits/ 16 ; pqa_cq_thread6_frame_done = /bits/ 16 ; pqa_cq_thread7_frame_done = /bits/ 16 ; pqa_cq_thread8_frame_done = /bits/ 16 ; pqa_cq_thread9_frame_done = /bits/ 16 ; pqb_cq_thread0_frame_done = /bits/ 16 ; pqb_cq_thread1_frame_done = /bits/ 16 ; pqb_cq_thread2_frame_done = /bits/ 16 ; pqb_cq_thread3_frame_done = /bits/ 16 ; pqb_cq_thread4_frame_done = /bits/ 16 ; pqb_cq_thread5_frame_done = /bits/ 16 ; pqb_cq_thread6_frame_done = /bits/ 16 ; pqb_cq_thread7_frame_done = /bits/ 16 ; pqb_cq_thread8_frame_done = /bits/ 16 ; pqb_cq_thread9_frame_done = /bits/ 16 ; wpe_eis_cq_thread0_frame_done = /bits/ 16 ; wpe_eis_cq_thread1_frame_done = /bits/ 16 ; wpe_eis_cq_thread2_frame_done = /bits/ 16 ; wpe_eis_cq_thread3_frame_done = /bits/ 16 ; wpe_eis_cq_thread4_frame_done = /bits/ 16 ; wpe_eis_cq_thread5_frame_done = /bits/ 16 ; wpe_eis_cq_thread6_frame_done = /bits/ 16 ; wpe_eis_cq_thread7_frame_done = /bits/ 16 ; wpe_eis_cq_thread8_frame_done = /bits/ 16 ; wpe_eis_cq_thread9_frame_done = /bits/ 16 ; wpe_tnr_cq_thread0_frame_done = /bits/ 16 ; wpe_tnr_cq_thread1_frame_done = /bits/ 16 ; wpe_tnr_cq_thread2_frame_done = /bits/ 16 ; wpe_tnr_cq_thread3_frame_done = /bits/ 16 ; wpe_tnr_cq_thread4_frame_done = /bits/ 16 ; wpe_tnr_cq_thread5_frame_done = /bits/ 16 ; wpe_tnr_cq_thread6_frame_done = /bits/ 16 ; wpe_tnr_cq_thread7_frame_done = /bits/ 16 ; wpe_tnr_cq_thread8_frame_done = /bits/ 16 ; wpe_tnr_cq_thread9_frame_done = /bits/ 16 ; wpe_lite_cq_thread0_frame_done = /bits/ 16 ; wpe_lite_cq_thread1_frame_done = /bits/ 16 ; wpe_lite_cq_thread2_frame_done = /bits/ 16 ; wpe_lite_cq_thread3_frame_done = /bits/ 16 ; wpe_lite_cq_thread4_frame_done = /bits/ 16 ; wpe_lite_cq_thread5_frame_done = /bits/ 16 ; wpe_lite_cq_thread6_frame_done = /bits/ 16 ; wpe_lite_cq_thread7_frame_done = /bits/ 16 ; wpe_lite_cq_thread8_frame_done = /bits/ 16 ; wpe_lite_cq_thread9_frame_done = /bits/ 16 ; me_done = /bits/ 16 ; adl_tile_done = /bits/ 16 ; wpe_eis_sync_token = /bits/ 16 ; wpe_tnr_sync_token = /bits/ 16 ; wpe_lite_sync_token = /bits/ 16 ; traw_sync_token = /bits/ 16 ; ltraw_sync_token = /bits/ 16 ; dip_sync_token = /bits/ 16 ; pqdip_a_sync_token = /bits/ 16 ; pqdip_b_sync_token = /bits/ 16 ; me_sync_token = /bits/ 16 ; apu_sync_token = /bits/ 16 ; vss_traw_sync_token = /bits/ 16 ; vss_ltraw_sync_token = /bits/ 16 ; vss_dip_sync_token = /bits/ 16 ; sw_sync_token_pool_1 = /bits/ 16 ; sw_sync_token_pool_2 = /bits/ 16 ; sw_sync_token_pool_3 = /bits/ 16 ; sw_sync_token_pool_4 = /bits/ 16 ; sw_sync_token_pool_5 = /bits/ 16 ; sw_sync_token_pool_6 = /bits/ 16 ; sw_sync_token_pool_7 = /bits/ 16 ; sw_sync_token_pool_8 = /bits/ 16 ; sw_sync_token_pool_9 = /bits/ 16 ; sw_sync_token_pool_10 = /bits/ 16 ; sw_sync_token_pool_11 = /bits/ 16 ; sw_sync_token_pool_12 = /bits/ 16 ; sw_sync_token_pool_13 = /bits/ 16 ; sw_sync_token_pool_14 = /bits/ 16 ; sw_sync_token_pool_15 = /bits/ 16 ; sw_sync_token_pool_16 = /bits/ 16 ; sw_sync_token_pool_17 = /bits/ 16 ; sw_sync_token_pool_18 = /bits/ 16 ; sw_sync_token_pool_19 = /bits/ 16 ; sw_sync_token_pool_20 = /bits/ 16 ; sw_sync_token_pool_21 = /bits/ 16 ; sw_sync_token_pool_22 = /bits/ 16 ; sw_sync_token_pool_23 = /bits/ 16 ; sw_sync_token_pool_24 = /bits/ 16 ; sw_sync_token_pool_25 = /bits/ 16 ; sw_sync_token_pool_26 = /bits/ 16 ; sw_sync_token_pool_27 = /bits/ 16 ; sw_sync_token_pool_28 = /bits/ 16 ; sw_sync_token_pool_29 = /bits/ 16 ; sw_sync_token_pool_30 = /bits/ 16 ; sw_sync_token_pool_31 = /bits/ 16 ; sw_sync_token_pool_32 = /bits/ 16 ; sw_sync_token_pool_33 = /bits/ 16 ; sw_sync_token_pool_34 = /bits/ 16 ; sw_sync_token_pool_35 = /bits/ 16 ; sw_sync_token_pool_36 = /bits/ 16 ; sw_sync_token_pool_37 = /bits/ 16 ; sw_sync_token_pool_38 = /bits/ 16 ; sw_sync_token_pool_39 = /bits/ 16 ; sw_sync_token_pool_40 = /bits/ 16 ; sw_sync_token_pool_41 = /bits/ 16 ; sw_sync_token_pool_42 = /bits/ 16 ; sw_sync_token_pool_43 = /bits/ 16 ; sw_sync_token_pool_44 = /bits/ 16 ; sw_sync_token_pool_45 = /bits/ 16 ; sw_sync_token_pool_46 = /bits/ 16 ; sw_sync_token_pool_47 = /bits/ 16 ; sw_sync_token_pool_48 = /bits/ 16 ; sw_sync_token_pool_49 = /bits/ 16 ; sw_sync_token_pool_50 = /bits/ 16 ; sw_sync_token_pool_51 = /bits/ 16 ; sw_sync_token_pool_52 = /bits/ 16 ; sw_sync_token_pool_53 = /bits/ 16 ; sw_sync_token_pool_54 = /bits/ 16 ; sw_sync_token_pool_55 = /bits/ 16 ; sw_sync_token_pool_56 = /bits/ 16 ; sw_sync_token_pool_57 = /bits/ 16 ; sw_sync_token_pool_58 = /bits/ 16 ; sw_sync_token_pool_59 = /bits/ 16 ; sw_sync_token_pool_60 = /bits/ 16 ; sw_sync_token_pool_61 = /bits/ 16 ; sw_sync_token_pool_62 = /bits/ 16 ; sw_sync_token_pool_63 = /bits/ 16 ; sw_sync_token_pool_64 = /bits/ 16 ; sw_sync_token_pool_65 = /bits/ 16 ; sw_sync_token_pool_66 = /bits/ 16 ; sw_sync_token_pool_67 = /bits/ 16 ; sw_sync_token_pool_68 = /bits/ 16 ; sw_sync_token_pool_69 = /bits/ 16 ; sw_sync_token_pool_70 = /bits/ 16 ; sw_sync_token_pool_71 = /bits/ 16 ; sw_sync_token_pool_72 = /bits/ 16 ; sw_sync_token_pool_73 = /bits/ 16 ; sw_sync_token_pool_74 = /bits/ 16 ; sw_sync_token_pool_75 = /bits/ 16 ; sw_sync_token_pool_76 = /bits/ 16 ; sw_sync_token_pool_77 = /bits/ 16 ; sw_sync_token_pool_78 = /bits/ 16 ; sw_sync_token_pool_79 = /bits/ 16 ; sw_sync_token_pool_80 = /bits/ 16 ; sw_sync_token_pool_81 = /bits/ 16 ; sw_sync_token_pool_82 = /bits/ 16 ; sw_sync_token_pool_83 = /bits/ 16 ; sw_sync_token_pool_84 = /bits/ 16 ; sw_sync_token_pool_85 = /bits/ 16 ; sw_sync_token_pool_86 = /bits/ 16 ; sw_sync_token_pool_87 = /bits/ 16 ; sw_sync_token_pool_88 = /bits/ 16 ; sw_sync_token_pool_89 = /bits/ 16 ; sw_sync_token_pool_90 = /bits/ 16 ; sw_sync_token_pool_91 = /bits/ 16 ; sw_sync_token_pool_92 = /bits/ 16 ; sw_sync_token_pool_93 = /bits/ 16 ; sw_sync_token_pool_94 = /bits/ 16 ; sw_sync_token_pool_95 = /bits/ 16 ; sw_sync_token_pool_96 = /bits/ 16 ; sw_sync_token_pool_97 = /bits/ 16 ; sw_sync_token_pool_98 = /bits/ 16 ; sw_sync_token_pool_99 = /bits/ 16 ; sw_sync_token_pool_100 = /bits/ 16 ; sw_sync_token_pool_101 = /bits/ 16 ; sw_sync_token_pool_102 = /bits/ 16 ; sw_sync_token_pool_103 = /bits/ 16 ; sw_sync_token_pool_104 = /bits/ 16 ; sw_sync_token_pool_105 = /bits/ 16 ; sw_sync_token_pool_106 = /bits/ 16 ; sw_sync_token_pool_107 = /bits/ 16 ; sw_sync_token_pool_108 = /bits/ 16 ; sw_sync_token_pool_109 = /bits/ 16 ; sw_sync_token_pool_110 = /bits/ 16 ; sw_sync_token_pool_111 = /bits/ 16 ; sw_sync_token_pool_112 = /bits/ 16 ; sw_sync_token_pool_113 = /bits/ 16 ; sw_sync_token_pool_114 = /bits/ 16 ; sw_sync_token_pool_115 = /bits/ 16 ; sw_sync_token_pool_116 = /bits/ 16 ; sw_sync_token_pool_117 = /bits/ 16 ; sw_sync_token_pool_118 = /bits/ 16 ; sw_sync_token_pool_119 = /bits/ 16 ; sw_sync_token_pool_120 = /bits/ 16 ; sw_sync_token_pool_121 = /bits/ 16 ; sw_sync_token_pool_122 = /bits/ 16 ; sw_sync_token_pool_123 = /bits/ 16 ; sw_sync_token_pool_124 = /bits/ 16 ; sw_sync_token_pool_125 = /bits/ 16 ; sw_sync_token_pool_126 = /bits/ 16 ; sw_sync_token_pool_127 = /bits/ 16 ; sw_sync_token_pool_128 = /bits/ 16 ; sw_sync_token_pool_129 = /bits/ 16 ; sw_sync_token_pool_130 = /bits/ 16 ; sw_sync_token_pool_131 = /bits/ 16 ; sw_sync_token_pool_132 = /bits/ 16 ; sw_sync_token_pool_133 = /bits/ 16 ; sw_sync_token_pool_134 = /bits/ 16 ; sw_sync_token_pool_135 = /bits/ 16 ; sw_sync_token_pool_136 = /bits/ 16 ; sw_sync_token_pool_137 = /bits/ 16 ; sw_sync_token_pool_138 = /bits/ 16 ; sw_sync_token_pool_139 = /bits/ 16 ; sw_sync_token_pool_140 = /bits/ 16 ; sw_sync_token_pool_141 = /bits/ 16 ; sw_sync_token_pool_142 = /bits/ 16 ; sw_sync_token_pool_143 = /bits/ 16 ; sw_sync_token_pool_144 = /bits/ 16 ; sw_sync_token_pool_145 = /bits/ 16 ; sw_sync_token_pool_146 = /bits/ 16 ; sw_sync_token_pool_147 = /bits/ 16 ; sw_sync_token_pool_148 = /bits/ 16 ; sw_sync_token_pool_149 = /bits/ 16 ; sw_sync_token_pool_150 = /bits/ 16 ; sw_sync_token_pool_151 = /bits/ 16 ; sw_sync_token_pool_152 = /bits/ 16 ; sw_sync_token_pool_153 = /bits/ 16 ; sw_sync_token_pool_154 = /bits/ 16 ; sw_sync_token_pool_155 = /bits/ 16 ; sw_sync_token_pool_156 = /bits/ 16 ; sw_sync_token_pool_157 = /bits/ 16 ; sw_sync_token_pool_158 = /bits/ 16 ; sw_sync_token_pool_159 = /bits/ 16 ; sw_sync_token_pool_160 = /bits/ 16 ; sw_sync_token_pool_161 = /bits/ 16 ; sw_sync_token_pool_162 = /bits/ 16 ; sw_sync_token_pool_163 = /bits/ 16 ; sw_sync_token_pool_164 = /bits/ 16 ; sw_sync_token_pool_165 = /bits/ 16 ; sw_sync_token_pool_166 = /bits/ 16 ; sw_sync_token_pool_167 = /bits/ 16 ; sw_sync_token_pool_168 = /bits/ 16 ; sw_sync_token_pool_169 = /bits/ 16 ; sw_sync_token_pool_170 = /bits/ 16 ; sw_sync_token_pool_171 = /bits/ 16 ; sw_sync_token_pool_172 = /bits/ 16 ; sw_sync_token_pool_173 = /bits/ 16 ; sw_sync_token_pool_174 = /bits/ 16 ; sw_sync_token_pool_175 = /bits/ 16 ; sw_sync_token_pool_176 = /bits/ 16 ; sw_sync_token_pool_177 = /bits/ 16 ; sw_sync_token_pool_178 = /bits/ 16 ; sw_sync_token_pool_179 = /bits/ 16 ; sw_sync_token_pool_180 = /bits/ 16 ; sw_sync_token_pool_181 = /bits/ 16 ; sw_sync_token_pool_182 = /bits/ 16 ; sw_sync_token_pool_183 = /bits/ 16 ; sw_sync_token_pool_184 = /bits/ 16 ; sw_sync_token_pool_185 = /bits/ 16 ; sw_sync_token_pool_186 = /bits/ 16 ; sw_sync_token_pool_187 = /bits/ 16 ; sw_sync_token_pool_188 = /bits/ 16 ; sw_sync_token_pool_189 = /bits/ 16 ; sw_sync_token_pool_190 = /bits/ 16 ; sw_sync_token_pool_191 = /bits/ 16 ; sw_sync_token_pool_192 = /bits/ 16 ; sw_sync_token_pool_193 = /bits/ 16 ; sw_sync_token_pool_194 = /bits/ 16 ; sw_sync_token_pool_195 = /bits/ 16 ; sw_sync_token_pool_196 = /bits/ 16 ; sw_sync_token_pool_197 = /bits/ 16 ; sw_sync_token_pool_198 = /bits/ 16 ; sw_sync_token_pool_199 = /bits/ 16 ; sw_sync_token_pool_200 = /bits/ 16 ; sw_sync_token_pool_201 = /bits/ 16 ; sw_sync_token_pool_202 = /bits/ 16 ; sw_sync_token_pool_203 = /bits/ 16 ; sw_sync_token_pool_204 = /bits/ 16 ; sw_sync_token_pool_205 = /bits/ 16 ; sw_sync_token_pool_206 = /bits/ 16 ; sw_sync_token_pool_207 = /bits/ 16 ; sw_sync_token_pool_208 = /bits/ 16 ; sw_sync_token_pool_209 = /bits/ 16 ; sw_sync_token_pool_210 = /bits/ 16 ; sw_sync_token_pool_211 = /bits/ 16 ; sw_sync_token_pool_212 = /bits/ 16 ; sw_sync_token_pool_213 = /bits/ 16 ; sw_sync_token_pool_214 = /bits/ 16 ; sw_sync_token_pool_215 = /bits/ 16 ; sw_sync_token_pool_216 = /bits/ 16 ; sw_sync_token_pool_217 = /bits/ 16 ; sw_sync_token_pool_218 = /bits/ 16 ; sw_sync_token_pool_219 = /bits/ 16 ; sw_sync_token_pool_220 = /bits/ 16 ; sw_sync_token_pool_221 = /bits/ 16 ; sw_sync_token_pool_222 = /bits/ 16 ; sw_sync_token_pool_223 = /bits/ 16 ; sw_sync_token_pool_224 = /bits/ 16 ; sw_sync_token_pool_225 = /bits/ 16 ; sw_sync_token_pool_226 = /bits/ 16 ; sw_sync_token_pool_227 = /bits/ 16 ; sw_sync_token_pool_228 = /bits/ 16 ; sw_sync_token_pool_229 = /bits/ 16 ; sw_sync_token_pool_230 = /bits/ 16 ; sw_sync_token_pool_231 = /bits/ 16 ; sw_sync_token_pool_232 = /bits/ 16 ; sw_sync_token_pool_233 = /bits/ 16 ; sw_sync_token_pool_234 = /bits/ 16 ; sw_sync_token_pool_235 = /bits/ 16 ; sw_sync_token_pool_236 = /bits/ 16 ; sw_sync_token_pool_237 = /bits/ 16 ; sw_sync_token_pool_238 = /bits/ 16 ; sw_sync_token_pool_239 = /bits/ 16 ; sw_sync_token_pool_240 = /bits/ 16 ; sw_sync_token_pool_241 = /bits/ 16 ; sw_sync_token_pool_242 = /bits/ 16 ; sw_sync_token_pool_243 = /bits/ 16 ; sw_sync_token_pool_244 = /bits/ 16 ; sw_sync_token_pool_245 = /bits/ 16 ; sw_sync_token_pool_246 = /bits/ 16 ; sw_sync_token_pool_247 = /bits/ 16 ; sw_sync_token_pool_248 = /bits/ 16 ; sw_sync_token_pool_249 = /bits/ 16 ; sw_sync_token_pool_250 = /bits/ 16 ; sw_sync_token_tzmp_isp_wait = /bits/ 16 ; sw_sync_token_tzmp_isp_set = /bits/ 16 ; sw_sync_token_tzmp_adl_wait = /bits/ 16 ; sw_sync_token_tzmp_adl_set = /bits/ 16 ; #if 0 sw_sync_token_camsys_pool_1 = /bits/ 16 ; sw_sync_token_camsys_pool_2 = /bits/ 16 ; sw_sync_token_camsys_pool_3 = /bits/ 16 ; sw_sync_token_camsys_pool_4 = /bits/ 16 ; sw_sync_token_camsys_pool_5 = /bits/ 16 ; sw_sync_token_camsys_pool_6 = /bits/ 16 ; sw_sync_token_camsys_pool_7 = /bits/ 16 ; sw_sync_token_camsys_pool_8 = /bits/ 16 ; sw_sync_token_camsys_pool_9 = /bits/ 16 ; sw_sync_token_camsys_pool_10 = /bits/ 16 ; #endif clocks = <&imgsys_main_clk CLK_IMG_TRAW0>, <&imgsys_main_clk CLK_IMG_TRAW1>, <&imgsys_main_clk CLK_IMG_VCORE_GALS>, <&imgsys_main_clk CLK_IMG_DIP0>, <&imgsys_main_clk CLK_IMG_WPE0>, <&imgsys_main_clk CLK_IMG_WPE1>, <&imgsys_main_clk CLK_IMG_WPE2>, <&imgsys_main_clk CLK_IMG_ADL0>, <&imgsys_main_clk CLK_IMG_AVS>, <&imgsys_main_clk CLK_IMG_GALS>, <&dip_top_dip1_clk CLK_DIP_TOP_DIP1_DIP_TOP>, <&dip_nr1_dip1_clk CLK_DIP_NR1_DIP1_LARB>, <&dip_nr1_dip1_clk CLK_DIP_NR1_DIP1_DIP_NR1>, <&dip_nr2_dip1_clk CLK_DIP_NR2_DIP1_DIP_NR>, <&wpe1_dip1_clk CLK_WPE1_DIP1_WPE>, <&wpe2_dip1_clk CLK_WPE2_DIP1_WPE>, <&wpe3_dip1_clk CLK_WPE3_DIP1_WPE>, <&traw_dip1_clk CLK_TRAW_DIP1_TRAW>, <&imgsys_main_clk CLK_IMG_IPE>, <&imgsys_main_clk CLK_IMG_ME>, <&imgsys_main_clk CLK_IMG_MMG>, <&mmdvfs_clk CLK_MMDVFS_IMG>; clock-names = "IMGSYS_CG_IMG_TRAW0", "IMGSYS_CG_IMG_TRAW1", "IMGSYS_CG_IMG_VCORE_GALS", "IMGSYS_CG_IMG_DIP0", "IMGSYS_CG_IMG_WPE0", "IMGSYS_CG_IMG_WPE1", "IMGSYS_CG_IMG_WPE2", "IMGSYS_CG_IMG_ADL_TOP0", "IMGSYS_CG_IMG_AVS", "IMGSYS_CG_IMG_GALS", "DIP_TOP_DIP_TOP", "DIP_NR1_DIP1_LARB", "DIP_NR1_DIP_NR1", "DIP_NR2_DIP_NR", "WPE1_CG_DIP1_WPE", "WPE2_CG_DIP1_WPE", "WPE3_CG_DIP1_WPE", "TRAW_CG_DIP1_TRAW", "IMGSYS_CG_IMG_IPE", "ME_CG", "MMG_CG", "mmdvfs_clk"; operating-points-v2 = <&opp_table_img>; #if 0 dvfsrc-vmm-supply = <&vmm_proxy_label>; #endif mediatek,imgsys-qos-sc-motr = <2>; mediatek,imgsys-qos-sc-nums = <2>; mediatek,imgsys-qos-sc-id = <7 7>; interconnects = <&mmqos SLAVE_LARB(10) &mmqos SLAVE_COMMON(0)>, <&mmqos SLAVE_LARB(22) &mmqos SLAVE_COMMON(0)>, <&mmqos SLAVE_LARB(9) &mmqos SLAVE_COMMON(1)>, <&mmqos SLAVE_LARB(15) &mmqos SLAVE_COMMON(1)>; interconnect-names = "l10_common_r_0", "l22_common_w_0", "l9_common_r_1", "l15_common_w_1"; }; aie: aie@15310000 { compatible = "mediatek,aie-isp7s"; reg = <0 0x15310000 0 0x1000>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; mboxes = <&gce_m 20 0 CMDQ_THR_PRIO_1>, <&gce_m_sec 11 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>; mediatek,larb = <&smi_larb12>; mediatek,imgsys_fw = <&imgsys_fw>; mediatek,aov = <&aov>; fdvt_frame_done = ; sw_sync_token_tzmp_aie_wait = ; sw_sync_token_tzmp_aie_set = ; iommus = <&mdp_iommu M4U_PORT_L12_FDVT_RDA_0>, <&mdp_iommu M4U_PORT_L12_FDVT_WRA_0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; clocks = <&imgsys_main_clk CLK_IMG_VCORE_GALS>, <&imgsys_main_clk CLK_IMG_FDVT>, <&imgsys_main_clk CLK_IMG_LARB12>, <&imgsys_main_clk CLK_IMG_IPE>; clock-names = "VCORE_GALS", "IPE_FDVT", "IPE_SMI_LARB12", "IMG_IPE"; }; ipesys_me: ipesys_me@15320000 { compatible = "mediatek,ipesys-me-isp7s"; reg = <0 0x15320000 0 0x10000>; /* 9 IMGSYS_ME */ #if 0 mediatek,larb = <&smi_larb12>; iommus = <&mdp_iommu M4U_PORT_L12_IPE_ME_RDMA>, <&mdp_iommu M4U_PORT_L12_IPE_ME_WDMA>; clocks = <&imgsys_main_clk CLK_IMGSYS_MAIN_IPE>, <&ipesys_clk CLK_IPESYS_IPESYS_TOP>, <&ipesys_clk CLK_IPESYS_ME>, <&ipesys_clk CLK_IPESYS_SMI_LARB12>; clock-names = "ME_CG_IPE", "ME_CG_IPE_TOP", "ME_CG", "ME_CG_LARB12"; #endif }; jpgenc@17030000 { compatible = "mediatek,mtk-jpgenc"; reg = <0 0x17030000 0 0x10000>; interrupts = ; clocks = <&venc_gcon_clk CLK_VEN_CKE2_JPGENC>; clock-names = "jpgenc"; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN0>; mediatek,larb = <&smi_larb7>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L7_JPGENC_Y_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_C_RDMA>, <&disp_iommu M4U_PORT_L7_JPGENC_Q_TABLE>, <&disp_iommu M4U_PORT_L7_JPGENC_BSDMA>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_RDMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_TABLE) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA) &mmqos SLAVE_COMMON(0)>; interconnect-names = "path_jpegenc_y_rdma", "path_jpegenc_c_rmda", "path_jpegenc_q_table", "path_jpegenc_bsdma"; operating-points-v2 = <&opp_table_venc>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; }; jpgdec0@17040000 { compatible = "mediatek,jpgdec"; reg = <0 0x17040000 0 0x10000>, <0 0x17050000 0 0x10000>; interrupts = , ; mediatek,larbs = <&smi_larb7>; operating-points-v2 = <&opp_table_venc>; dvfsrc-vcore-supply = <&dvfsrc_vcore>; clocks = <&venc_gcon_clk CLK_VEN_CKE3_JPGDEC>, <&venc_gcon_clk CLK_VEN_CKE4_JPGDEC_C1>; clock-names = "MT_CG_VENC_JPGDEC", "MT_CG_VENC_JPGDEC_C1"; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; iommus = <&disp_iommu M4U_PORT_L7_JPGDEC_WDMA_0>, <&disp_iommu M4U_PORT_L7_JPGDEC_BSDMA_0>, <&disp_iommu M4U_PORT_L7_JPGDEC_WDMA_1>, <&disp_iommu M4U_PORT_L7_JPGDEC_BSDMA_1>, <&disp_iommu M4U_PORT_L7_JPGDEC_HUFF_OFFSET_1>, <&disp_iommu M4U_PORT_L7_JPGDEC_HUFF_OFFSET_0>; }; mbist@17060000 { compatible = "mediatek,mbist"; reg = <0 0x17060000 0 0x10000>; }; jpgenc@17830000 { compatible = "mediatek,mtk-jpgenc_c1"; reg = <0 0x17830000 0 0x10000>; interrupts = ; clocks = <&venc_gcon_core1_clk CLK_VEN_C1_CKE2_JPGENC>; clock-names = "jpgenc_c1"; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN1>; mediatek,larb = <&smi_larb8>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L8_JPGENC_Y_RDMA>, <&mdp_iommu M4U_PORT_L8_JPGENC_C_RDMA>, <&mdp_iommu M4U_PORT_L8_JPGENC_Q_TABLE>, <&mdp_iommu M4U_PORT_L8_JPGENC_BSDMA>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_Y_RDMA) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_C_RDMA) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_Q_TABLE) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_BSDMA) &mmqos SLAVE_COMMON(1)>; interconnect-names = "path_jpegenc_y_rdma", "path_jpegenc_c_rmda", "path_jpegenc_q_table", "path_jpegenc_bsdma"; operating-points-v2 = <&opp_table_venc>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; }; mbist@17860000 { compatible = "mediatek,mbist"; reg = <0 0x17860000 0 0x10000>; }; mbist@17c60000 { compatible = "mediatek,mbist"; reg = <0 0x17c60000 0 0x10000>; }; mtk_sec_dmaheap { compatible = "mediatek,dmaheap-region-base"; iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL0_2L_HDR>; }; mtk-sec-dmaheap-apu { compatible = "mediatek,dmaheap-apu-region-base"; iommus = <&apu_iommu0 M4U_PORT_L40_APU_CODE>; }; mtk_iommu_debug { compatible = "mediatek,mt6985-iommu-debug"; }; mtk_dmabufheap_debug0: dmaheap_test0 { compatible = "mediatek, mtk_dmabufheap, iommu0"; iommus = <&disp_iommu M4U_PORT_L0_DISP_FAKE0>; }; mtk_dmabufheap_debug1: dmaheap_test1 { compatible = "mediatek, mtk_dmabufheap, iommu1"; iommus = <&disp_iommu M4U_PORT_L1_DISP_FAKE1>; }; iommu_test { compatible = "mediatek,ktf-iommu-test"; iommus = <&disp_iommu M4U_PORT_L0_DISP_FAKE0>; }; connv3: connv3@18000000 { compatible = "mediatek,mt6985-connv3"; /* BT, WIFI, GPS, FM */ radio-support = "wifi", "bt", "md"; pinctrl-names = "connsys-pin-pmic-en-default", "connsys-pin-pmic-en-set", "connsys-pin-pmic-en-clr", "connsys-pin-pmic-faultb-default", "connsys-pin-pmic-faultb-enable", "connsys-combo-gpio-init", "connsys-combo-gpio-pre-on", "connsys-combo-gpio-on", "connsys-pin-ext32k-en-default", "connsys-pin-ext32k-en-set", "connsys-pin-ext32k-en-clr", "connsys-pin-pmic-en-default"; pinctrl-0 = <&connsys_pin_pmic_en_default>; pinctrl-1 = <&connsys_pin_pmic_en_set>; pinctrl-2 = <&connsys_pin_pmic_en_clr>; pinctrl-3 = <&connsys_pin_pmic_faultb_default>; pinctrl-4 = <&connsys_pin_pmic_faultb_enable>; pinctrl-5 = <&connsys_combo_gpio_init>; pinctrl-6 = <&connsys_combo_gpio_pre_on>; pinctrl-7 = <&connsys_combo_gpio_on>; pinctrl-8 = <&connsys_pin_ext32k_en_default>; pinctrl-9 = <&connsys_pin_ext32k_en_set>; pinctrl-10 = <&connsys_pin_ext32k_en_clr>; interrupt-parent = <&pio>; mt6376-gpio = <&pio 231 0>, <&pio 241 0>; interrupts = <231 IRQ_TYPE_EDGE_FALLING>; }; bt: bt { compatible = "mediatek,bt"; sleep-en = <1>; hub-en = <1>; baudrate = <12000000>; pinctrl-names = "bt_combo_gpio_init", "bt_combo_gpio_pre_on", "bt_combo_uart_tx_aux", "bt_combo_uart_rx_aux", "bt_rst_on", "bt_rst_off", "bt-find-my-phone-high", "bt-find-my-phone-low"; pinctrl-0 = <&bt_combo_gpio_init>; pinctrl-1 = <&bt_combo_gpio_pre_on>; pinctrl-2 = <&bt_combo_uart_tx_aux>; pinctrl-3 = <&bt_combo_uart_rx_aux>; pinctrl-4 = <&bt_rst_on>; pinctrl-5 = <&bt_rst_off>; pinctrl-6 = <&bt_find_my_phone_high>; pinctrl-7 = <&bt_find_my_phone_low>; }; wifi: wifi@18000000 { compatible = "mediatek,wifi"; reg = <0 0x18000000 0 0x700000>; interrupts = ; emi-addr = <0>; emi-size = <0x1a00000>; emi-alignment = <0x1000000>; emi-max-addr = <0xC0000000>; pinctrl-names = "wf_rst_off", "wf_rst_on", "wf_rst_pta_uart_init", "wf_rst_pta_uart_on", "wf_rst_pta_uart_off"; pinctrl-0 = <&wf_rst_off>; pinctrl-1 = <&wf_rst_on>; pinctrl-2 = <&wf_rst_pta_uart_init>; pinctrl-3 = <&wf_rst_pta_uart_on>; pinctrl-4 = <&wf_rst_pta_uart_off>; conninfra-emi-addr = <0>; conninfra-emi-size = <0xc00000>; #thermal-sensor-cells = <1>; interconnects = <&dvfsrc MT6873_MASTER_MCUSYS &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "wifi-perf-bw"; required-opps = <&dvfsrc_freq_opp0>, <&dvfsrc_freq_opp1>; }; wifi_page_pool: wifi_page_pool { compatible = "mediatek,wifi_page_pool"; emi-size = <0x8000000>; mpu-protect = <0>; dynamic-alloc = <0>; }; consys: consys@18000000 { compatible = "mediatek,mt6985-consys"; reg = <0 0x18011000 0 0x138>, /* 0 conn_cfg*/ <0 0x18060000 0 0xc08>,/* 1 conn_host_csr_top */ <0 0x18050000 0 0x2000>, /* 2 conn_infra_sysram */ <0 0x1804b000 0 0x414>, /* 3 conn_infra_bus_cr */ <0 0x18000000 0 0x480>, /* 4 conn_infra_rgu_on */ <0 0x18003000 0 0x204>, /* 5 conn_wt_slp_ctl_reg */ <0 0x18001000 0 0x658>, /* 6 conn_infra_cfg_on */ <0 0x1800e000 0 0x124>, /* 7 conn_infra_bus_cr_on */ <0 0x1804d000 0 0x41c>, /* 8 conn_infra_off_debug_ctrl_ao */ <0 0x18012000 0 0xbc>, /* 9 conn_infra_clkgen_top */ <0 0x18042000 0 0x324>, /* 10 conn_rf_spi_mst_reg */ <0 0x1002c000 0 0xb04>, /* 11 ifrbus_ao_reg */ <0 0x1c001000 0 0xfe0>, /* 12 spm */ <0 0x18070000 0 0x8004>, /* 13 conn_semaphore */ <0 0x18041000 0 0x140>, /* 14 conn_afe_ctl */ <0 0x1c00d000 0 0x7ec>, /* 15 SRCLKENRC */ <0 0x18023000 0 0x1000>; /* 16 conn_dbg_ctl */ radio-support = "gps", "mawd"; power-domains = <&scpsys MT6985_POWER_DOMAIN_CONN>; emi-addr = <0>; emi-size = <0>; ro-emi-size = <0x3c0000>; rw-emi-size = <0xd0000>; shared-emi-size = <0x180000>; mnl-mpe-emi-size = <0x2fa000>; scp-shm-size = <0x96000>; scp-remap-offset = <0x445000>; scp-remap-size = <0x520000>; gps-emi-offset = <0x4d0000>; gps-emi-size = <0x140000>; emi-alignment = <0x100000>; emi-min-addr = <0x40000000>; emi-max-addr = <0xA0000000>; }; apu_iommu0_bank1: iommu@19011000 { compatible = "mediatek,common-apu-iommu0-bank1"; mediatek,bank-id = <1>; reg = <0 0x19011000 0 0x1000>; interrupts = ; }; apu_iommu0_bank2: iommu@19012000 { compatible = "mediatek,common-apu-iommu0-bank2"; mediatek,bank-id = <2>; reg = <0 0x19012000 0 0x1000>; interrupts = ; }; apu_iommu0_bank3: iommu@19013000 { compatible = "mediatek,common-apu-iommu0-bank3"; mediatek,bank-id = <3>; reg = <0 0x19013000 0 0x1000>; interrupts = ; }; apu_iommu0_bank4: iommu@19014000 { compatible = "mediatek,common-apu-iommu0-bank4"; mediatek,bank-id = <4>; reg = <0 0x19014000 0 0x1000>; interrupts = ; }; apu_iommu0: iommu@19010000 { compatible = "mediatek,mt6985-apu-iommu0"; reg = <0 0x19010000 0 0x1000>; table_id = <1>; mediatek,apu_power = <&apusys_rv>; power-domains = <&scpsys MT6985_POWER_DOMAIN_APU>; mediatek,iommu_banks = <&apu_iommu0_bank1 &apu_iommu0_bank2 &apu_iommu0_bank3 &apu_iommu0_bank4>; interrupts = ; #iommu-cells = <1>; }; apu_iommu1_bank1: iommu@19016000 { compatible = "mediatek,common-apu-iommu1-bank1"; mediatek,bank-id = <1>; reg = <0 0x19016000 0 0x1000>; interrupts = ; }; apu_iommu1_bank2: iommu@19017000 { compatible = "mediatek,common-apu-iommu1-bank2"; mediatek,bank-id = <2>; reg = <0 0x19017000 0 0x1000>; interrupts = ; }; apu_iommu1_bank3: iommu@19018000 { compatible = "mediatek,common-apu-iommu1-bank3"; mediatek,bank-id = <3>; reg = <0 0x19018000 0 0x1000>; interrupts = ; }; apu_iommu1_bank4: iommu@19019000 { compatible = "mediatek,common-apu-iommu1-bank4"; mediatek,bank-id = <4>; reg = <0 0x19019000 0 0x1000>; interrupts = ; }; apu_iommu1: iommu@19015000 { compatible = "mediatek,mt6985-apu-iommu1"; reg = <0 0x19015000 0 0x1000>; table_id = <1>; mediatek,apu_power = <&apusys_rv>; power-domains = <&scpsys MT6985_POWER_DOMAIN_APU>; mediatek,iommu_banks = <&apu_iommu1_bank1 &apu_iommu1_bank2 &apu_iommu1_bank3 &apu_iommu1_bank4>; interrupts = ; #iommu-cells = <1>; }; keypad: kp@1c00e000 { compatible = "mediatek,kp"; reg = <0 0x1c00e000 0 0x1000>; interrupts = ; mediatek,key-debounce-ms = <1024>; mediatek,hw-map-num = <72>; mediatek,hw-init-map = <114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; clocks = <&clk26m>; clock-names = "kpd"; }; regulator_vibrator: regulator-vibrator { compatible = "regulator-vibrator"; label = "vibrator"; min-volt = <2800000>; max-volt = <3500000>; vib-supply = <&mt6373_vibr>; }; adspsys: adspsys@1e000000 { compatible = "mediatek,mt6985-adspsys"; status = "okay"; reg = <0 0x1e000000 0 0x6000>, /* CFG */ <0 0x1e00b000 0 0x5000>, /* CFG 2 */ <0 0x1e006000 0 0x100>, /* MBOX0 base */ <0 0x1e006100 0 0x4>, /* MBOX0 set */ <0 0x1e00610c 0 0x4>, /* MBOX0 clr */ <0 0x1e007000 0 0x100>, /* MBOX1 base */ <0 0x1e007100 0 0x4>, /* MBOX1 set */ <0 0x1e00710c 0 0x4>, /* MBOX1 clr */ <0 0x1e008000 0 0x100>, /* MBOX2 base */ <0 0x1e008100 0 0x4>, /* MBOX2 set */ <0 0x1e00810c 0 0x4>, /* MBOX2 clr */ <0 0x1e009000 0 0x100>, /* MBOX3 base */ <0 0x1e009100 0 0x4>, /* MBOX3 set */ <0 0x1e00910c 0 0x4>, /* MBOX3 clr */ <0 0x1c0016b0 0 0x4>; /* SPM SEMAPHORE */ reg-names = "cfg", "cfg2", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox3_base", "mbox3_set", "mbox3_clr", "spm_sema"; interrupts = , /* MBOX0 */ , /* MBOX1 */ , /* MBOX2 */ , /* MBOX3 */ ; /* DEBUG_CTRL */ interrupt-names = "mbox0", "mbox1", "mbox2", "mbox3", "debug_ctrl"; #mbox-cells = <1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ADSP_TOP_DORMANT>; clocks = <&topckgen_clk CLK_TOP_ADSP_SEL>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>, <&topckgen_clk CLK_TOP_ADSPPLL>, <&topckgen_clk CLK_TOP_AUDIO_LOCAL_BUS_SEL>, <&topckgen_clk CLK_TOP_MAINPLL_D5_D2>; clock-names = "clk_top_adsp_sel", "clk_top_clk26m", "clk_top_adsppll", "clk_top_aud_local_bus_sel", "clk_top_mainpll_d5_d2"; core-num = <2>; /* core number */ adsp-rsv-ipidma-a = <0x100000>; adsp-rsv-ipidma-b = <0x100000>; adsp-rsv-logger-a = <0x80000>; adsp-rsv-logger-b = <0x80000>; adsp-rsv-c2c = <0x40000>; adsp-rsv-dbg-dump-a = <0x80000>; adsp-rsv-dbg-dump-b = <0x80000>; adsp-rsv-core-dump-a = <0x400>; adsp-rsv-core-dump-b = <0x400>; adsp-rsv-xhci = <0x80000>; adsp-rsv-audio = <0x5c0000>; }; adsp_core0: adsp-core0@1e020000 { compatible = "mediatek,mt6985-adsp_core_0"; status = "okay"; reg = <0 0x1e050000 0 0x9000>, /* ITCM */ <0 0x1e020000 0 0x8000>; /* DTCM */ system = <0 0x50000000 0 0xc00000>; interrupts = , , ; mboxes = <&adspsys 0>, /*channel 0*/ <&adspsys 1>; /*channel 1*/ feature-control-bits = <0xa8e78fff>; }; adsp_core1: adsp-core1@1e090000 { compatible = "mediatek,mt6985-adsp_core_1"; status = "okay"; reg = <0 0x1e0c0000 0 0x9000>, /* ITCM */ <0 0x1e090000 0 0x8000>; /* DTCM */ system = <0 0x50c00000 0 0xa00000>; interrupts = , , ; mboxes = <&adspsys 2>, /*channel 2*/ <&adspsys 3>; /*channel 3*/ feature-control-bits = <0x5118700f>; }; disp_iommu_bank1: iommu@1e803000 { compatible = "mediatek,common-disp-iommu-bank1"; mediatek,bank-id = <1>; reg = <0 0x1e803000 0 0x1000>; interrupts = ; }; disp_iommu_bank2: iommu@1e804000 { compatible = "mediatek,common-disp-iommu-bank2"; mediatek,bank-id = <2>; reg = <0 0x1e804000 0 0x1000>; interrupts = ; }; disp_iommu_bank3: iommu@1e805000 { compatible = "mediatek,common-disp-iommu-bank3"; mediatek,bank-id = <3>; reg = <0 0x1e805000 0 0x1000>; interrupts = ; }; disp_iommu_bank4: iommu@1e806000 { compatible = "mediatek,common-disp-iommu-bank4"; mediatek,bank-id = <4>; reg = <0 0x1e806000 0 0x1000>; interrupts = ; }; disp_iommu: iommu@1e802000 { compatible = "mediatek,mt6985-disp-iommu"; reg = <0 0x1e802000 0 0x1000>; table_id = <0>; mediatek,larbs = <&smi_larb0 &smi_larb2 &smi_larb5>, <&smi_larb6 &smi_larb7 &smi_larb10>, <&smi_larb16 &smi_larb17 &smi_larb19>, <&smi_larb21 &smi_larb22 &smi_larb23>, <&smi_larb25 &smi_larb28 &smi_larb29>, <&smi_larb31 &smi_larb33 &smi_larb34>, <&smi_larb35>; mediatek,iommu_banks = <&disp_iommu_bank1 &disp_iommu_bank2 &disp_iommu_bank3 &disp_iommu_bank4>; interrupts = ; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_SMI>; clock-names = "bclk"; #iommu-cells = <1>; }; mdp_iommu_bank1: iommu@1e811000 { compatible = "mediatek,common-mdp-iommu-bank1"; mediatek,bank-id = <1>; reg = <0 0x1e811000 0 0x1000>; interrupts = ; }; mdp_iommu_bank2: iommu@1e812000 { compatible = "mediatek,common-mdp-iommu-bank2"; mediatek,bank-id = <2>; reg = <0 0x1e812000 0 0x1000>; interrupts = ; }; mdp_iommu_bank3: iommu@1e813000 { compatible = "mediatek,common-mdp-iommu-bank3"; mediatek,bank-id = <3>; reg = <0 0x1e813000 0 0x1000>; interrupts = ; }; mdp_iommu_bank4: iommu@1e814000 { compatible = "mediatek,common-mdp-iommu-bank4"; mediatek,bank-id = <4>; reg = <0 0x1e814000 0 0x1000>; interrupts = ; }; mdp_iommu: iommu@1e810000 { compatible = "mediatek,mt6985-mdp-iommu"; reg = <0 0x1e810000 0 0x1000>; table_id = <0>; mediatek,larbs = <&smi_larb1 &smi_larb3 &smi_larb4>, <&smi_larb8 &smi_larb9 &smi_larb11>, <&smi_larb12 &smi_larb13 &smi_larb14>, <&smi_larb15 &smi_larb17 &smi_larb18>, <&smi_larb20 &smi_larb26 &smi_larb27>, <&smi_larb30 &smi_larb32 &smi_larb35>, <&smi_larb37>; mediatek,iommu_banks = <&mdp_iommu_bank1 &mdp_iommu_bank2 &mdp_iommu_bank3 &mdp_iommu_bank4>; interrupts = ; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_SMI>; clock-names = "bclk"; #iommu-cells = <1>; }; mdpsys_config: mdpsys-config@1f000000 { compatible = "mediatek,mdpsys_config"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; clocks = <&mdpsys_config_clk CLK_MDP_APB_BUS>; clock-names = "MDP_APB_BUS"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; #address-cells = <2>; #size-cells = <2>; iommus = <&disp_iommu M4U_PORT_L2_MDP_RDMA0>, <&disp_iommu M4U_PORT_L2_MDP_RDMA1>, <&disp_iommu M4U_PORT_L2_MDP_RDMA2>, <&disp_iommu M4U_PORT_L2_MDP_RDMA3>, <&disp_iommu M4U_PORT_L2_MDP_WROT0>, <&disp_iommu M4U_PORT_L2_MDP_WROT1>; dma-mask-bit = <34>; }; mdp: mdp@1f000000 { compatible = "mediatek,mdp"; reg = <0 0x1f000000 0 0x1000>; thread-count = <24>; mboxes = <&gce 20 0 CMDQ_THR_PRIO_1>, <&gce 21 0 CMDQ_THR_PRIO_1>; mmsys-config = <&mdpsys_config>; mm-mutex = <&mdp_mutex0>; mdp-rdma0 = <&mdp_rdma0>; mdp-rdma1 = <&mdp_rdma1>; mdp-rdma2 = <&mdp_rdma2>; mdp-rdma3 = <&mdp_rdma3>; mdp-rsz0 = <&mdp_rsz0>; mdp-rsz1 = <&mdp_rsz1>; mdp-birsz0 = <&mdp_birsz0>; mdp-birsz1 = <&mdp_birsz1>; mdp-wrot0 = <&mdp_wrot0>; mdp-wrot1 = <&mdp_wrot1>; mdp-tdshp0 = <&mdp_tdshp0>; mdp-tdshp1 = <&mdp_tdshp1>; mdp-aal0 = <&mdp_aal0>; mdp-aal1 = <&mdp_aal1>; mdp-color0 = <&mdp_color0>; mdp-color1 = <&mdp_color1>; mdp-hdr0 = <&mdp_hdr0>; mdp-hdr1 = <&mdp_hdr1>; mediatek,larb = <&smi_larb2>; mdp-rdma0-sof = ; mdp-rdma1-sof = ; mdp-wrot0-sof = ; mdp-wrot1-sof = ; mdp-rdma2-sof = ; mdp-rdma3-sof = ; mdp-wrot1-write-frame-done = ; mdp-wrot0-write-frame-done = ; mdp-tdshp1-frame-done = ; mdp-tdshp-frame-done = ; mdp-rsz1-frame-done = ; mdp-rsz0-frame-done = ; mdp-rdma3-frame-done = ; mdp-rdma2-frame-done = ; mdp-rdma1-frame-done = ; mdp-rdma0-frame-done = ; mdp-hdr1-frame-done = ; mdp-hdr0-frame-done = ; mdp-color1-frame-done = ; mdp-color-frame-done = ; mdp-birsz0-frame-done = ; mdp-birsz1-frame-done = ; mdp-aal1-frame-done = ; mdp-aal-frame-done = ; mdp-wrot1-rst-done = ; mdp-wrot0-rst-done = ; mdp-rdma3-rst-done = ; mdp-rdma2-rst-done = ; mdp-rdma1-rst-done = ; mdp-rdma0-rst-done = ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA3) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT1) &mmqos SLAVE_COMMON(0)>; interconnect-names = "mdp_rdma0", "mdp_rdma1", "mdp_rdma2", "mdp_rdma3", "mdp_wrot0", "mdp_wrot1"; mdp-opp = <&opp_table_mdp>; operating-points-v2 = <&opp_table_mdp>; mdp-dvfsrc-vcore-supply = <&dvfsrc_vcore>; dre30-hist-sram-start = /bits/ 16 <1536>; }; mdp_mutex0: mdp-mutex0@1f001000 { compatible = "mediatek,mdp_mutex0"; reg = <0 0x1f001000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_MUTEX0>; clock-names = "MDP_MUTEX0"; }; mdp_rdma0: mdp-rdma0@1f003000 { compatible = "mediatek,mdp_rdma0"; reg = <0 0x1f003000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RDMA0>; clock-names = "MDP_RDMA0"; }; mdp_rdma1: mdp-rdma1@1f004000 { compatible = "mediatek,mdp_rdma1"; reg = <0 0x1f004000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RDMA1>; clock-names = "MDP_RDMA1"; }; mdp_hdr0: mdp-hdr0@1f005000 { compatible = "mediatek,mdp_hdr0", "mediatek,mdp-tuning-mdp_hdr0"; reg = <0 0x1f005000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_HDR0>; clock-names = "MDP_HDR0"; }; mdp_hdr1: mdp-hdr1@1f006000 { compatible = "mediatek,mdp_hdr1", "mediatek,mdp-tuning-mdp_hdr1"; reg = <0 0x1f006000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_HDR1>; clock-names = "MDP_HDR1"; }; mdp_aal0: mdp-aal0@1f007000 { compatible = "mediatek,mdp_aal0", "mediatek,mdp-tuning-mdp_aal0"; reg = <0 0x1f007000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_AAL0>; clock-names = "MDP_AAL0"; }; mdp_aal1: mdp-aal1@1f008000 { compatible = "mediatek,mdp_aal1", "mediatek,mdp-tuning-mdp_aal1"; reg = <0 0x1f008000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_AAL1>; clock-names = "MDP_AAL1"; }; mdp_rsz0: mdp-rsz0@1f009000 { compatible = "mediatek,mdp_rsz0"; reg = <0 0x1f009000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RSZ0>; clock-names = "MDP_RSZ0"; }; mdp_rsz1: mdp-rsz1@1f00a000 { compatible = "mediatek,mdp_rsz1"; reg = <0 0x1f00a000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RSZ1>; clock-names = "MDP_RSZ1"; }; mdp_tdshp0: mdp-tdshp0@1f00b000 { compatible = "mediatek,mdp_tdshp0", "mediatek,mdp-tuning-mdp_tdshp0"; reg = <0 0x1f00b000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_TDSHP0>; clock-names = "MDP_TDSHP0"; }; mdp_tdshp1: mdp-tdshp1@1f00c000 { compatible = "mediatek,mdp_tdshp1", "mediatek,mdp-tuning-mdp_tdshp1"; reg = <0 0x1f00c000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_TDSHP1>; clock-names = "MDP_TDSHP1"; }; mdp_color0: mdp-color0@1f00d000 { compatible = "mediatek,mdp_color0", "mediatek,mdp-tuning-mdp_color0"; reg = <0 0x1f00d000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_COLOR0>; clock-names = "MDP_COLOR0"; }; mdp_color1: mdp-color1@1f00e000 { compatible = "mediatek,mdp_color1", "mediatek,mdp-tuning-mdp_color1"; reg = <0 0x1f00e000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_COLOR1>; clock-names = "MDP_COLOR1"; }; mdp_wrot0: mdp-wrot0@1f00f000 { compatible = "mediatek,mdp_wrot0"; reg = <0 0x1f00f000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_WROT0>; clock-names = "MDP_WROT0"; }; mdp_wrot1: mdp-wrot1@1f010000 { compatible = "mediatek,mdp_wrot1"; reg = <0 0x1f010000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_WROT1>; clock-names = "MDP_WROT1"; }; mdp_rdma2: mdp-rdma2@1f011000 { compatible = "mediatek,mdp_rdma2"; reg = <0 0x1f011000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RDMA2>; clock-names = "MDP_RDMA2"; }; mdp_rdma3: mdp-rdma3@1f012000 { compatible = "mediatek,mdp_rdma3"; reg = <0 0x1f012000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_RDMA3>; clock-names = "MDP_RDMA3"; }; mdp_birsz0: mdp-birsz0@1f018000 { compatible = "mediatek,mdp_birsz0"; reg = <0 0x1f018000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_BIRSZ0>; clock-names = "MDP_BIRSZ0"; }; mdp_birsz1: mdp-birsz1@1f019000 { compatible = "mediatek,mdp_birsz1"; reg = <0 0x1f019000 0 0x1000>; clocks = <&mdpsys_config_clk CLK_MDP_BIRSZ1>; clock-names = "MDP_BIRSZ1"; }; mmlsys_config: mmlsys-config@1f800000 { compatible = "mediatek,mt6985-mml"; reg = <0 0x1f800000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_APB_BUS>, <&mdpsys1_config_clk CLK_MDP1_MDP_DLI_ASYNC0>, <&mdpsys1_config_clk CLK_MDP1_MDP_DLI_ASYNC1>, <&mdpsys1_config_clk CLK_MDP1_MDP_DLO_ASYNC0>, <&mdpsys1_config_clk CLK_MDP1_MDP_DLO_ASYNC1>; clock-names = "apb_bus", "dli0", "dli1", "dlo0", "dlo1"; /* as mml device */ comp-count = ; topology = "mt6985"; mboxes = <&gce 16 400 CMDQ_THR_PRIO_1>, <&gce 17 500 CMDQ_THR_PRIO_1>, <&gce 18 400 CMDQ_THR_PRIO_1>, <&gce 19 500 CMDQ_THR_PRIO_1>; /* as mmlsys */ comp-ids = , , , , , , , , , , ; comp-types = , , , , , , , , , , ; comp-names = "mmlsys", "dli0", "dli1", "dli0-sel", "dli1-sel", "pq0-sout", "pq1-sout", "dl0-sout", "dl1-sout", "dlo0", "dlo1"; mmlsys-clock-names = "apb_bus"; dli0-clock-names = "dli0"; dli1-clock-names = "dli1"; dlo0-clock-names = "dlo0"; dlo1-clock-names = "dlo1"; /* as sys component */ mux-pins = /bits/ 16 < 0 MML_RDMA0 MML_DLI0_SEL MML_MUX_SLIN MML_DLI0_SEL_IN 1 MML_DLI0 MML_DLI0_SEL MML_MUX_SLIN MML_DLI0_SEL_IN /* 2 MML_DLI2 MML_DLI0_SEL MML_MUX_SLIN MML_DLI0_SEL_IN */ /* 3 MML_ISP0 MML_DLI0_SEL MML_MUX_SLIN MML_DLI0_SEL_IN */ /* 4 MML_ISP0 MML_DLI0_SEL MML_MUX_SLIN MML_DLI0_SEL_IN */ 0 MML_RDMA1 MML_DLI1_SEL MML_MUX_SLIN MML_DLI1_SEL_IN 1 MML_DLI1 MML_DLI1_SEL MML_MUX_SLIN MML_DLI1_SEL_IN /* 2 MML_DLI3 MML_DLI1_SEL MML_MUX_SLIN MML_DLI1_SEL_IN */ /* 3 MML_ISP3 MML_DLI1_SEL MML_MUX_SLIN MML_DLI1_SEL_IN */ /* 4 MML_ISP0 MML_DLI1_SEL MML_MUX_SLIN MML_DLI1_SEL_IN */ 0 MML_DLI0_SEL MML_HDR0 MML_MUX_MOUT MML_RDMA0_MOUT_EN 1 MML_DLI0_SEL MML_DLO0_SOUT MML_MUX_MOUT MML_RDMA0_MOUT_EN /* 2 MML_DLI0_SEL MML_HDR1 MML_MUX_MOUT MML_RDMA0_MOUT_EN */ 3 MML_DLI0_SEL MML_RSZ2 MML_MUX_MOUT MML_RDMA0_MOUT_EN 0 MML_DLI1_SEL MML_HDR1 MML_MUX_MOUT MML_RDMA1_MOUT_EN 1 MML_DLI1_SEL MML_DLO1_SOUT MML_MUX_MOUT MML_RDMA1_MOUT_EN /* 2 MML_DLI1_SEL MML_HDR0 MML_MUX_MOUT MML_RDMA1_MOUT_EN */ 3 MML_DLI1_SEL MML_RSZ3 MML_MUX_MOUT MML_RDMA1_MOUT_EN 0 MML_DLI0_SEL MML_HDR0 MML_MUX_SLIN MML_PQ0_SEL_IN /* 1 MML_DLI1_SEL MML_HDR0 MML_MUX_SLIN MML_PQ0_SEL_IN */ 0 MML_DLI1_SEL MML_HDR1 MML_MUX_SLIN MML_PQ1_SEL_IN /* 1 MML_DLI0_SEL MML_HDR1 MML_MUX_SLIN MML_PQ1_SEL_IN */ 0 MML_DLI0_SEL MML_DLO0_SOUT MML_MUX_SLIN MML_WROT0_SEL_IN 1 MML_PQ0_SOUT MML_DLO0_SOUT MML_MUX_SLIN MML_WROT0_SEL_IN /* 2 MML_PQ1_SOUT MML_DLO0_SOUT MML_MUX_SLIN MML_WROT0_SEL_IN */ 0 MML_DLI1_SEL MML_DLO1_SOUT MML_MUX_SLIN MML_WROT1_SEL_IN 1 MML_PQ1_SOUT MML_DLO1_SOUT MML_MUX_SLIN MML_WROT1_SEL_IN /* 2 MML_PQ0_SOUT MML_DLO1_SOUT MML_MUX_SLIN MML_WROT1_SEL_IN */ 0 MML_PQ0_SOUT MML_DLO0_SOUT MML_MUX_SOUT MML_PQ0_SOUT_SEL /* 1 MML_PQ0_SOUT MML_DLO1_SOUT MML_MUX_SOUT MML_PQ0_SOUT_SEL */ 0 MML_PQ0_SOUT MML_DLO1_SOUT MML_MUX_SOUT MML_PQ1_SOUT_SEL /* 1 MML_PQ0_SOUT MML_DLO0_SOUT MML_MUX_SOUT MML_PQ1_SOUT_SEL */ 0 MML_DLO0_SOUT MML_WROT0 MML_MUX_SOUT MML_DLO0_SOUT_SEL 1 MML_DLO0_SOUT MML_DLO0 MML_MUX_SOUT MML_DLO0_SOUT_SEL /* 2 MML_DLO0_SOUT MML_DLO2 MML_MUX_SOUT MML_DLO0_SOUT_SEL */ 0 MML_DLO1_SOUT MML_WROT1 MML_MUX_SOUT MML_DLO1_SOUT_SEL 1 MML_DLO1_SOUT MML_DLO1 MML_MUX_SOUT MML_DLO1_SOUT_SEL /* 2 MML_DLO1_SOUT MML_DLO3 MML_MUX_SOUT MML_DLO1_SOUT_SEL */ 0 MML_RDMA0 MML_WROT0 MML_MUX_MOUT MML_BYP0_MOUT_EN 1 MML_RDMA0 MML_RSZ2 MML_MUX_MOUT MML_BYP0_MOUT_EN 2 MML_RDMA0 MML_DLI0_SEL MML_MUX_MOUT MML_BYP0_MOUT_EN 0 MML_RDMA1 MML_WROT1 MML_MUX_MOUT MML_BYP1_MOUT_EN 1 MML_RDMA1 MML_RSZ3 MML_MUX_MOUT MML_BYP1_MOUT_EN 2 MML_RDMA1 MML_DLI1_SEL MML_MUX_MOUT MML_BYP1_MOUT_EN 0 MML_RDMA0 MML_WROT0 MML_MUX_SLIN MML_BYP0_SEL_IN 1 MML_DLO0_SOUT MML_WROT0 MML_MUX_SLIN MML_BYP0_SEL_IN 0 MML_RDMA1 MML_WROT1 MML_MUX_SLIN MML_BYP1_SEL_IN 1 MML_DLO1_SOUT MML_WROT1 MML_MUX_SLIN MML_BYP1_SEL_IN 0 MML_DLI0_SEL MML_RSZ2 MML_MUX_SLIN MML_RSZ2_SEL_IN 1 MML_RDMA0 MML_RSZ2 MML_MUX_SLIN MML_RSZ2_SEL_IN /* 2 IMG_DL0 MML_RSZ2 MML_MUX_SLIN MML_RSZ2_SEL_IN */ /* 3 IMG_DL1 MML_RSZ2 MML_MUX_SLIN MML_RSZ2_SEL_IN */ 4 MML_AAL0 MML_RSZ2 MML_MUX_SLIN MML_RSZ2_SEL_IN 0 MML_DLI1_SEL MML_RSZ3 MML_MUX_SLIN MML_RSZ3_SEL_IN 1 MML_RDMA1 MML_RSZ3 MML_MUX_SLIN MML_RSZ3_SEL_IN /* 2 IMG_DL1 MML_RSZ2 MML_MUX_SLIN MML_RSZ3_SEL_IN */ /* 3 IMG_DL0 MML_RSZ2 MML_MUX_SLIN MML_RSZ3_SEL_IN */ 4 MML_AAL1 MML_RSZ2 MML_MUX_SLIN MML_RSZ3_SEL_IN 0 MML_HDR0 MML_AAL0 MML_MUX_SOUT MML_HDR0_SOUT_SEL 1 MML_HDR0 MML_COLOR0 MML_MUX_SOUT MML_HDR0_SOUT_SEL 0 MML_HDR1 MML_AAL1 MML_MUX_SOUT MML_HDR1_SOUT_SEL 1 MML_HDR1 MML_COLOR1 MML_MUX_SOUT MML_HDR1_SOUT_SEL 0 MML_HDR0 MML_AAL0 MML_MUX_SLIN MML_AAL0_SEL_IN 1 MML_COLOR0 MML_AAL0 MML_MUX_SLIN MML_AAL0_SEL_IN 0 MML_HDR1 MML_AAL1 MML_MUX_SLIN MML_AAL1_SEL_IN 1 MML_COLOR1 MML_AAL1 MML_MUX_SLIN MML_AAL1_SEL_IN 0 MML_COLOR0 MML_PQ0_SOUT MML_MUX_SOUT MML_TDSHP0_SOUT_SEL 1 MML_TDSHP0 MML_PQ0_SOUT MML_MUX_SOUT MML_TDSHP0_SOUT_SEL 0 MML_COLOR1 MML_PQ1_SOUT MML_MUX_SOUT MML_TDSHP1_SOUT_SEL 1 MML_TDSHP1 MML_PQ1_SOUT MML_MUX_SOUT MML_TDSHP1_SOUT_SEL 0 MML_TDSHP0 MML_COLOR0 MML_MUX_SLIN MML_COLOR0_SEL_IN 1 MML_HDR0 MML_COLOR0 MML_MUX_SLIN MML_COLOR0_SEL_IN 0 MML_TDSHP1 MML_COLOR1 MML_MUX_SLIN MML_COLOR1_SEL_IN 1 MML_HDR1 MML_COLOR1 MML_MUX_SLIN MML_COLOR1_SEL_IN 0 MML_COLOR0 MML_PQ0_SOUT MML_MUX_SOUT MML_COLOR0_SOUT_SEL 1 MML_COLOR0 MML_AAL0 MML_MUX_SOUT MML_COLOR0_SOUT_SEL 0 MML_COLOR1 MML_PQ1_SOUT MML_MUX_SOUT MML_COLOR1_SOUT_SEL 1 MML_COLOR1 MML_AAL1 MML_MUX_SOUT MML_COLOR1_SOUT_SEL 0 MML_COLOR0 MML_PQ0_SOUT MML_MUX_SLIN MML_TDSHP0_SEL_IN 1 MML_TDSHP0 MML_PQ0_SOUT MML_MUX_SLIN MML_TDSHP0_SEL_IN 0 MML_COLOR1 MML_PQ1_SOUT MML_MUX_SLIN MML_TDSHP1_SEL_IN 1 MML_TDSHP1 MML_PQ1_SOUT MML_MUX_SLIN MML_TDSHP1_SEL_IN 0 MML_AAL0 MML_RSZ0 MML_MUX_MOUT MML_AAL0_MOUT_EN 1 MML_AAL0 MML_RSZ2 MML_MUX_MOUT MML_AAL0_MOUT_EN 0 MML_AAL1 MML_RSZ1 MML_MUX_MOUT MML_AAL1_MOUT_EN 1 MML_AAL1 MML_RSZ3 MML_MUX_MOUT MML_AAL1_MOUT_EN>; dbg-reg-names = "MMLSYS_MISC", "CG_CON0", "CG_SET0", "CG_CLR0", "CG_CON1", "CG_SET1", "CG_CLR1", "SW0_RST_B", "SW1_RST_B", "MOUT_RST", "EVENT_GCED_EN", "IN_LINE_READY_SEL", "SMI_LARB_GREQ", "BYPASS_MUX_SHADOW", "DLI0_SEL_IN", "DLI1_SEL_IN", "RDMA0_MOUT_EN", "RDMA1_MOUT_EN", "PQ0_SEL_IN", "PQ1_SEL_IN", "WROT0_SEL_IN", "WROT1_SEL_IN", "PQ0_SOUT_SEL", "PQ1_SOUT_SEL", "DLO0_SOUT_SEL", "DLO1_SOUT_SEL", "BYP0_MOUT_EN", "BYP1_MOUT_EN", "BYP0_SEL_IN", "BYP1_SEL_IN", "RSZ2_SEL_IN", "RSZ3_SEL_IN", "HDR0_SOUT_SEL", "HDR1_SOUT_SEL", "AAL0_SEL_IN", "AAL1_SEL_IN", "TDSHP0_SOUT_SEL", "TDSHP1_SOUT_SEL", "COLOR0_SEL_IN", "COLOR1_SEL_IN", "COLOR0_SOUT_SEL", "COLOR1_SOUT_SEL", "TDSHP0_SEL_IN", "TDSHP1_SEL_IN", "AAL0_MOUT_EN", "AAL1_MOUT_EN", "MOUT_MASK0", "MOUT_MASK1", "MOUT_MASK2", "DL_IN_RELAY0_SIZE", "DL_IN_RELAY1_SIZE", "DL_OUT_RELAY0_SIZE", "DL_OUT_RELAY1_SIZE", "DLI_ASYNC0_STATUS0", "DLI_ASYNC0_STATUS1", "DLI_ASYNC1_STATUS0", "DLI_ASYNC1_STATUS1", "DLO_ASYNC0_STATUS0", "DLO_ASYNC0_STATUS1", "DLO_ASYNC1_STATUS0", "DLO_ASYNC1_STATUS1", "DLI_ASYNC3_STATUS0", "DLI_ASYNC3_STATUS1", "DLO_ASYNC3_STATUS0", "DLO_ASYNC3_STATUS1", "DL_VALID0", "DL_VALID1", "DL_VALID2", "DL_VALID3", "DL_READY0", "DL_READY1", "DL_READY2", "DL_READY3", "RDMA0_AIDSEL", "RDMA1_AIDSEL", "WROT0_AIDSEL", "WROT1_AIDSEL"; dbg-reg-offsets = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; aid-sel-engine = < MML_RDMA0 MML_RDMA0_AIDSEL MML_RDMA1 MML_RDMA1_AIDSEL MML_RDMA2 MML_RDMA2_AIDSEL MML_RDMA3 MML_RDMA3_AIDSEL MML_WROT0 MML_WROT0_AIDSEL MML_WROT1 MML_WROT1_AIDSEL MML_WROT2 MML_WROT2_AIDSEL MML_WROT3 MML_WROT3_AIDSEL>; racing-enable; event-ir-mml-ready = /bits/ 16 ; event-ir-disp-ready = /bits/ 16 ; event-ir-mml-stop = /bits/ 16 ; event-ir-eof = /bits/ 16 ; event-racing-pipe0 = /bits/ 16 ; event-racing-pipe1 = /bits/ 16 ; event-racing-pipe1-next = /bits/ 16 ; /* sys register offset */ ready-sel = /bits/ 16 ; /* as dl component */ dli0-dl-relay = /bits/ 16 ; dli1-dl-relay = /bits/ 16 ; dlo0-dl-relay = /bits/ 16 ; dlo1-dl-relay = /bits/ 16 ; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_DISP_FAKE0)>; sspm-aid-enable; operating-points-v2 = <&opp_table_mdp>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; }; mml-test { compatible = "mediatek,mml-test"; mediatek,mml = <&mmlsys_config>; }; mml-ait { compatible = "mediatek,mml-ait"; mediatek,mml = <&mmlsys_config>; }; mml_mutex0: mml-mutex0@1f801000 { compatible = "mediatek,mt6985-mml_mutex"; reg = <0 0x1f801000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_MUTEX0>; clock-names = "mutex0"; comp-ids = ; comp-names = "mutex0"; mutex-comps = "rdma0", "rdma1", "hdr0", "hdr1", "aal0", "aal1", "rsz0", "rsz1", "tdshp0", "tdshp1", "color0", "color1", "wrot0", "wrot1", "rdma2", "rdma3", "dli-async0", "dli-async1", "dlo-async0", "dlo-async1", "rsz2", "rsz3", "wrot2", "wrot3", "birsz0", "birsz1"; rdma0 = ; rdma1 = ; hdr0 = ; hdr1 = ; aal0 = ; aal1 = ; rsz0 = ; rsz1 = ; tdshp0 = ; tdshp1 = ; color0 = ; color1 = ; wrot0 = ; wrot1 = ; rdma2 = ; rdma3 = ; dli-async0 = ; dli-async1 = ; dlo-async0 = ; dlo-async1 = ; rsz2 = ; rsz3 = ; wrot2 = ; wrot3 = ; birsz0 = ; birsz1 = ; mutex-ids = ; }; mml_rdma0: mml-rdma0@1f803000 { compatible = "mediatek,mt6985-mml_rdma"; reg = <0 0x1f803000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RDMA0>; clock-names = "rdma0"; comp-ids = ; comp-names = "rdma0"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_RDMA0)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_RDMA0>; event-frame-done = /bits/ 16 ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA0) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; mml_rdma1: mml-rdma1@1f804000 { compatible = "mediatek,mt6985-mml_rdma"; reg = <0 0x1f804000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RDMA1>; clock-names = "rdma1"; comp-ids = ; comp-names = "rdma1"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_RDMA1)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_RDMA1>; event-frame-done = /bits/ 16 ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA1) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; mml_hdr0: mml-hdr0@1f805000 { compatible = "mediatek,mt6985-mml_hdr", "mediatek,mml-tuning-mml_hdr0"; reg = <0 0x1f805000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_HDR0>; clock-names = "hdr0"; comp-ids = ; comp-names = "hdr0"; }; mml_hdr1: mml-hdr1@1f806000 { compatible = "mediatek,mt6985-mml_hdr", "mediatek,mml-tuning-mml_hdr1"; reg = <0 0x1f806000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_HDR1>; clock-names = "hdr1"; comp-ids = ; comp-names = "hdr1"; }; mml_aal0: mml-aal0@1f807000 { compatible = "mediatek,mt6985-mml_aal", "mediatek,mml-tuning-mml_aal0"; reg = <0 0x1f807000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_AAL0>; clock-names = "aal0"; comp-ids = ; comp-names = "aal0"; sram-curve-base = /bits/ 32 <4608>; sram-his-base = /bits/ 32 <1536>; }; mml_aal1: mml-aal1@1f808000 { compatible = "mediatek,mt6985-mml_aal", "mediatek,mml-tuning-mml_aal1"; reg = <0 0x1f808000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_AAL1>; clock-names = "aal1"; comp-ids = ; comp-names = "aal1"; sram-curve-base = /bits/ 32 <4608>; sram-his-base = /bits/ 32 <1536>; }; mml_rsz0: mml-rsz0@1f809000 { compatible = "mediatek,mt6985-mml_rsz"; reg = <0 0x1f809000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RSZ0>; clock-names = "rsz0"; comp-ids = ; comp-names = "rsz0"; }; mml_rsz1: mml-rsz1@1f80a000 { compatible = "mediatek,mt6985-mml_rsz"; reg = <0 0x1f80a000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RSZ1>; clock-names = "rsz1"; comp-ids = ; comp-names = "rsz1"; }; mml_tdshp0: mml-tdshp0@1f80b000 { compatible = "mediatek,mt6985-mml_tdshp", "mediatek,mml-tuning-mml_tdshp0"; reg = <0 0x1f80b000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_TDSHP0>; clock-names = "tdshp0"; comp-ids = ; comp-names = "tdshp0"; }; mml_tdshp1: mml-tdshp1@1f80c000 { compatible = "mediatek,mt6985-mml_tdshp", "mediatek,mml-tuning-mml_tdshp1"; reg = <0 0x1f80c000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_TDSHP1>; clock-names = "tdshp1"; comp-ids = ; comp-names = "tdshp1"; }; mml_color0: mml-color0@1f80d000 { compatible = "mediatek,mt6985-mml_color", "mediatek,mml-tuning-mml_color0"; reg = <0 0x1f80d000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_COLOR0>; clock-names = "color0"; comp-ids = ; comp-names = "color0"; }; mml_color1: mml-color1@1f80e000 { compatible = "mediatek,mt6985-mml_color", "mediatek,mml-tuning-mml_color1"; reg = <0 0x1f80e000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_COLOR1>; clock-names = "color1"; comp-ids = ; comp-names = "color1"; }; mml_wrot0: mml-wrot0@1f80f000 { compatible = "mediatek,mt6985-mml_wrot"; reg = <0 0x1f80f000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_WROT0>; clock-names = "wrot0"; comp-ids = ; comp-names = "wrot0"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_WROT0)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_WROT0>; event-frame-done = /bits/ 16 ; event-bufa = /bits/ 16 ; event-bufb = /bits/ 16 ; event-buf-next = /bits/ 16 ; inlinerot = <&inlinerot0>, <&inlinerot1>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_WROT0) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; mml_wrot1: mml-wrot1@1f810000 { compatible = "mediatek,mt6985-mml_wrot"; reg = <0 0x1f810000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_WROT1>; clock-names = "wrot1"; comp-ids = ; comp-names = "wrot1"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_WROT1)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_WROT1>; event-frame-done = /bits/ 16 ; event-bufa = /bits/ 16 ; event-bufb = /bits/ 16 ; event-buf-next = /bits/ 16 ; inlinerot = <&inlinerot0>, <&inlinerot1>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_WROT1) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; mml_rdma2: mml-rdma2@1f811000 { compatible = "mediatek,mt6985-mml_pq_rdma"; reg = <0 0x1f811000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RDMA2>; clock-names = "rdma2"; comp-ids = ; comp-names = "rdma2"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_RDMA2)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_RDMA2>; event-frame-done = /bits/ 16 ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA2) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; mml_rdma3: mml-rdma3@1f812000 { compatible = "mediatek,mt6985-mml_pq_rdma"; reg = <0 0x1f812000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RDMA3>; clock-names = "rdma3"; comp-ids = ; comp-names = "rdma3"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_RDMA3)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_RDMA3>; event-frame-done = /bits/ 16 ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA3) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; mml_rsz2: mml-rsz2@1f813000 { compatible = "mediatek,mt6985-mml_rsz2"; reg = <0 0x1f813000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RSZ2>; clock-names = "rsz2"; comp-ids = ; comp-names = "rsz2"; }; mml_rsz3: mml-rsz3@1f814000 { compatible = "mediatek,mt6985-mml_rsz2"; reg = <0 0x1f814000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_RSZ3>; clock-names = "rsz3"; comp-ids = ; comp-names = "rsz3"; }; mml_wrot2: mml-wrot2@1f815000 { compatible = "mediatek,mt6985-mml_wrot"; reg = <0 0x1f815000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_WROT2>; clock-names = "wrot2"; comp-ids = ; comp-names = "wrot2"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_WDMA2)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_WDMA2>; event-frame-done = /bits/ 16 ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_WDMA2) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; mml_wrot3: mml-wrot3@1f816000 { compatible = "mediatek,mt6985-mml_wrot"; reg = <0 0x1f816000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_WROT3>; clock-names = "wrot3"; comp-ids = ; comp-names = "wrot3"; mediatek,larb = <&smi_larb3 MTK_M4U_TO_PORT(M4U_PORT_L3_MDP_WDMA3)>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L3_MDP_WDMA3>; event-frame-done = /bits/ 16 ; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L3_MDP_WDMA3) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mml_dma"; }; hre_top_mdpsys@1f817000 { compatible = "mediatek,hre_top_mdpsys"; reg = <0 0x1f817000 0 0x1000>; }; mml_birsz0: mml-birsz0@1f818000 { compatible = "mediatek,mt6985-mml_birsz"; reg = <0 0x1f818000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_BIRSZ0>; clock-names = "birsz0"; comp-ids = ; comp-names = "birsz0"; }; mml_birsz1: mml-birsz1@1f819000 { compatible = "mediatek,mt6985-mml_birsz"; reg = <0 0x1f819000 0 0x1000>; clocks = <&mdpsys1_config_clk CLK_MDP1_MDP_BIRSZ1>; clock-names = "birsz1"; comp-ids = ; comp-names = "birsz1"; }; uarthub: uarthub@11005000 { compatible = "mediatek,mt6985-uarthub"; interrupts = ; /*uarthub irq*/ clocks = <&apmixedsys_clk CLK_APMIXED_UNIVPLL>; clock-names = "univpll"; }; usb_offload: usb_offload { compatible = "mediatek,usb-offload"; xhci_host = <&usb_host>; }; ssusb: usb0@11201000 { compatible = "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; vusb33-supply = <&mt6373_vusb>; interrupts = ; phy-cells = <1>; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; clocks = <&topckgen_clk CLK_TOP_USB_TOP_SEL>, <&topckgen_clk CLK_TOP_USB_XHCI_SEL>, <&pericfg_ao_clk CLK_PERAO_SSUSB0_FRMCNT>; clock-names = "sys_ck", "host_ck", "frmcnt_ck"; #address-cells = <2>; #size-cells = <2>; ranges; dr_mode = "otg"; maximum-speed = "high-speed"; mediatek,force-vbus; mediatek,clk-mgr; mediatek,usb3-drd; mediatek,noise-still-tr; mediatek,gen1-txdeemph; mediatek,hwrscs-vers = <1>; mediatek,syscon-wakeup = <&pericfg_ao_clk 0x200 103>; wakeup-source; mediatek,vs-voter = <&pmic 0x149a 0x1 1>; mediatek,uds = <&usb_dp_selector 19>; usb-role-switch; cdp-block; port { mtu3_drd_switch: endpoint { remote-endpoint = <&usb_role>; }; }; usb_host: xhci0@11200000 { compatible = "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x1000>; reg-names = "mac"; interrupts = ; clocks = <&clk26m>; clock-names = "sys_ck"; mediatek,usb-offload = <&usb_offload>; status = "okay"; }; }; ssusb1: usb1@11211000 { compatible = "mediatek,mtu3"; reg = <0 0x11211000 0 0x2e00>, <0 0x11213e00 0 0x0100>; reg-names = "mac", "ippc"; vusb33-supply = <&mt6373_vusb>; interrupts = ; phy-cells = <1>; phys = <&u2port1 PHY_TYPE_USB2>; clocks = <&topckgen_clk CLK_TOP_USB_TOP_1P_SEL>, <&topckgen_clk CLK_TOP_USB_XHCI_1P_SEL>, <&pericfg_ao_clk CLK_PERAO_SSUSB1_FRMCNT>; clock-names = "sys_ck", "host_ck", "frmcnt_ck"; #address-cells = <2>; #size-cells = <2>; ranges; dr_mode = "otg"; maximum-speed = "high-speed"; mediatek,force-vbus; mediatek,clk-mgr; mediatek,noise-still-tr; mediatek,hwrscs-vers = <1>; mediatek,vs-voter = <&pmic 0x149a 0x1 1>; usb-role-switch; port { mtu3_drd_switch1: endpoint { remote-endpoint = <&usb_role1>; }; }; usb_host1: xhci1@11210000 { compatible = "mediatek,mtk-xhci-p1"; reg = <0 0x11210000 0 0x1000>; reg-names = "mac"; interrupts = ; clocks = <&clk26m>; clock-names = "sys_ck"; status = "okay"; }; }; u3phy: usb-phy0@11e40000 { compatible = "mediatek,xsphy"; reg = <0 0x11e43000 0 0x200>; #address-cells = <2>; #size-cells = <2>; ranges; u2port0: usb2-phy0@11e40000 { reg = <0 0x11e40000 0 0x400>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; usb2jtag = <&vlpcfg_bus 2>; nvmem-cells = <&u2_phy_data>, <&u2_phy_data>; nvmem-cell-names = "intr_cal", "term_cal"; nvmem-cell-masks = <0x3f 0xf00>; mediatek,efuse-intr = <0x25>; mediatek,efuse-term = <0x8>; mediatek,eye-vrt = <0x2>; mediatek,eye-vrt-host = <0x2>; mediatek,rx-sqth = <0x5>; mediatek,discth = <0xb>; mediatek,pll-fbksel = <0x0>; mediatek,pll-posdiv = <0x0>; mediatek,lpm-parameter = <0x19 0x1e 0x1e>; }; u3port0: usb3-phy0@11e43000 { reg = <0 0x11e43400 0 0x500>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; }; }; u3phy1: usb-phy1@11e30000 { compatible = "mediatek,xsphy"; reg = <0 0x11e33000 0 0x200>; #address-cells = <2>; #size-cells = <2>; ranges; u2port1: usb2-phy1@11e30000 { reg = <0 0x11e30000 0 0x400>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; nvmem-cells = <&u2_phy_data>, <&u2_phy_data>; nvmem-cell-names = "intr_cal", "term_cal"; nvmem-cell-masks = <0x3f0000 0xf000000>; mediatek,efuse-intr = <0x25>; mediatek,efuse-term = <0x8>; mediatek,eye-vrt = <0x2>; mediatek,eye-vrt-host = <0x2>; mediatek,rx-sqth = <0x5>; mediatek,discth = <0xb>; mediatek,pll-fbksel = <0x0>; mediatek,pll-posdiv = <0x0>; mediatek,lpm-parameter = <0x19 0x1e 0x1e>; }; }; u3fpgaphy: u3fpgaphy { compatible = "mediatek,fpga-u3phy"; mediatek,ippc = <0x11203e00>; #address-cells = <2>; #size-cells = <2>; fpga_i2c_physical_base = <0x11d01000>; status = "disabled"; u3fpgaport0: u3fpgaport0 { chip-id= <0xa60931a>; port = <0>; pclk_phase = <23>; #phy-cells = <1>; }; }; typec_mux_switch: typec_mux_switch { compatible = "mediatek,typec_mux_switch"; status = "okay"; }; usb_dp_selector: usb_dp_selector@10005600 { compatible = "mediatek,usb_dp_selector"; reg = <0 0x10005600 0 0x4>; reg-names = "usb_dp_reg"; mediatek,uds-ver = <2>; status = "okay"; }; pcie0: pcie@112f0000 { device_type = "pci"; compatible = "mediatek,mt6985-pcie"; reg = <0 0x112f0000 0 0x4000>; reg-names = "pcie-mac"; #address-cells = <3>; #size-cells = <2>; interrupts = ; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x30000000 0x0 0x30000000 0 0x3C00000>, <0x81000000 0 0x33C00000 0x0 0x33C00000 0 0x0400000>; status = "disabled"; linux,pci-domain = <0>; mediatek,peri-reset-dis; mediatek,dvfs-req-dis; mediatek,suspend-mode-l12; clocks = <&pextpcfg_ao_clk CLK_PEXT_MAC0_26M>, <&pextpcfg_ao_clk CLK_PEXT_MAC0_P1_PCLK_250M>, <&pextpcfg_ao_clk CLK_PEXT_MAC0_GFMUX_TL>, <&pextpcfg_ao_clk CLK_PEXT_MAC0_FMEM>, <&pextpcfg_ao_clk CLK_PEXT_MAC0_HCLK>, <&pextpcfg_ao_clk CLK_PEXT_PHY0_REF>; power-domains = <&scpsys MT6985_POWER_DOMAIN_PEXTP_MAC0_SHUTDOWN>, <&scpsys MT6985_POWER_DOMAIN_PEXTP_PHY0>; power-domain-names = "pd_mac", "pd_phy"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, <0 0 0 2 &pcie_intc0 1>, <0 0 0 3 &pcie_intc0 2>, <0 0 0 4 &pcie_intc0 3>; pcie_intc0: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; pcie1: pcie@112f8000 { device_type = "pci"; compatible = "mediatek,mt6985-pcie"; reg = <0 0x112f8000 0 0x4000>; reg-names = "pcie-mac"; #address-cells = <3>; #size-cells = <2>; interrupts = ; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x34000000 0x0 0x34000000 0 0x3C00000>, <0x81000000 0 0x37C00000 0x0 0x37C00000 0 0x0400000>; status = "disabled"; linux,pci-domain = <1>; mediatek,peri-reset-dis; mediatek,dvfs-req-dis; clocks = <&pextpcfg_ao_clk CLK_PEXT_MAC1_26M>, <&pextpcfg_ao_clk CLK_PEXT_MAC1_P1_PCLK_250M>, <&pextpcfg_ao_clk CLK_PEXT_MAC1_GFMUX_TL>, <&pextpcfg_ao_clk CLK_PEXT_MAC1_FMEM>, <&pextpcfg_ao_clk CLK_PEXT_MAC1_HCLK>, <&pextpcfg_ao_clk CLK_PEXT_PHY1_REF>; power-domains = <&scpsys MT6985_POWER_DOMAIN_PEXTP_MAC1_SHUTDOWN>, <&scpsys MT6985_POWER_DOMAIN_PEXTP_PHY1>; power-domain-names = "pd_mac", "pd_phy"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, <0 0 0 2 &pcie_intc1 1>, <0 0 0 3 &pcie_intc1 2>, <0 0 0 4 &pcie_intc1 3>; pcie_intc1: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; spmi: spmi@1c804000 { compatible = "mediatek,mt6985-spmi"; reg = <0 0x1c804000 0 0x0008ff>, <0 0x1c801000 0 0x000100>, <0 0x0d0a0000 0 0x0000dc>; reg-names = "pmif", "spmimst"; interrupts-extended = <&pio 253 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "rcs_irq", "pmif_irq"; interrupt-controller; #interrupt-cells = <1>; irq_event_en = <0xc0000000 0x0 0x0 0x1f8 0x0>; swinf_ch_start = <11>; ap_swinf_no = <2>; #address-cells = <2>; #size-cells = <0>; }; spmi_pmif_mpu: spmi_pmif_mpu@1c804900 { compatible = "mediatek,mt6985-spmi_pmif_mpu"; reg = <0 0x1c804900 0 0x000500>; reg-names = "pmif_mpu"; mediatek,pmic-all-rgn-en = <0x1863f4>; mediatek,kernel-enable-time = <0x3c>; }; mmc1: mmc@11240000 { compatible = "mediatek,mt6985-mmc"; reg = <0 0x11240000 0 0x1000>, <0 0x11e00000 0 0x1000>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>, <&topckgen_clk CLK_TOP_MSDC_MACRO_SEL>, <&pericfg_ao_clk CLK_PERAO_MSDC1_F>, <&pericfg_ao_clk CLK_PERAO_MSDC1_H>, <&pericfg_ao_clk CLK_PERAO_MSDC1>; clock-names = "source", "macro", "axi_cg", "hclk", "source_cg"; status = "disabled"; }; mmc2: mmc@11242000 { compatible = "mediatek,mt6985-mmc"; reg = <0 0x11242000 0 0x1000>, <0 0x11b60000 0 0x1000>; interrupts = ; clocks = <&topckgen_clk CLK_TOP_MSDC30_2_SEL>, <&topckgen_clk CLK_TOP_MSDC_MACRO_SEL>, <&pericfg_ao_clk CLK_PERAO_MSDC2_F>, <&pericfg_ao_clk CLK_PERAO_MSDC2_H>, <&pericfg_ao_clk CLK_PERAO_MSDC2>; clock-names = "source", "macro", "axi_cg", "hclk", "source_cg"; status = "disabled"; }; ufsphy: ufsphy@112a0000 { compatible = "mediatek,mt8183-ufsphy"; #phy-cells = <0>; mphy-ver = <1>; ranges; reg = <0 0x112a0000 0 0x1000>, <0 0x1c001000 0 0x1000>; power-domains = <&scpsys MT6985_POWER_DOMAIN_UFS0_PHY_SHUTDOWN>; /* @CONFIG_UFS_MEDIATEK_INTERNAL */ mediatek,pm-forbidden-on-hwver = <0xca00>; bootmode = <&chosen>; }; ufshci: ufshci@112b0000 { compatible = "mediatek,mt8183-ufshci"; reg = <0 0x112b0000 0 0x2300>; phys = <&ufsphy>; interrupts = , , , , , , , , ; clocks = <&topckgen_clk CLK_TOP_U_SEL>, <&topckgen_clk CLK_TOP_MAINPLL_D4_D2>, <&topckgen_clk CLK_TOP_MMPLL_D6>, <&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>, <&topckgen_clk CLK_TOP_U_MBIST_SEL>, <&ufscfg_ao_clk CLK_UFSAO_UNIPRO_TX_SYM>, <&ufscfg_ao_clk CLK_UFSAO_UNIPRO_RX_SYM0>, <&ufscfg_ao_clk CLK_UFSAO_UNIPRO_RX_SYM1>, <&ufscfg_ao_clk CLK_UFSAO_UNIPRO_SYS>, <&ufscfg_pdn_clk CLK_UFSPDN_UFSHCI_UFS>, <&ufscfg_pdn_clk CLK_UFSPDN_UFSHCI_AES>; clock-names = "ufs_sel", "ufs_sel_min_src", "ufs_sel_max_src", "ufs_fde", "ufs_mbist", "unipro_tx_sym", "unipro_rx_sym0", "unipro_rx_sym1", "unipro_sys", "ufshci_ufs", "ufshci_aes"; freq-table-hz = <273000000 458333313>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_UFS0_SHUTDOWN>; vcc-supply = <&mt6363_vemc>; vccq-supply = <&mt6373_vbuck7>; resets = <&ufscfgao_rst 0>, <&ufscfgao_rst 1>, <&ufscfgpdn_rst 0>, <&ufscfgpdn_rst 1>; reset-names = "unipro_rst", "mphy_rst", "crypto_rst", "hci_rst"; bootmode = <&chosen>; mediatek,ufs-qos; mediatek,ufs-pmc-via-fastauto; mediatek,ufs-mphy-debug; mediatek,ufs-tx-skew-fix; /* mcq setting */ mediatek,ufs-mcq-enabled; mediatek,ufs-mcq-hwq-count = <8>; mediatek,ufs-mcq-q-depth = <32>; mediatek,ufs-mcq-intr-count = <8>; /* @CONFIG_UFS_MEDIATEK_INTERNAL */ mediatek,ufs-mcq-disable-on-hwver = <0xca00>; }; mgm: mgm { compatible = "arm,physical-memory-group-manager"; }; gpu_protected_memory_allocator: protected-memory-allocator@13c00000 { compatible = "arm,protected-memory-allocator"; reg = <0 0x13c00000 0 0x30000>; reg-names = "gpueb_base"; gpr-offset = <0x2fd1c>; gpr-id = <6>; gmpu-table-size = <0x0>; protected-reserve-size = <0x800000>; }; mali: mali@13000000 { compatible = "mediatek,mali", "arm,mali-valhall"; reg = <0 0x13000000 0 0x480000>; l2-hash-values = <0xb 0xe 0x0>; physical-memory-group-manager = <&mgm>; interrupts = , , , , ; interrupt-names = "GPU", "MMU", "JOB", "EVENT", "PWR"; system-coherency = <0>; protected-memory-allocator = <&gpu_protected_memory_allocator>; operating-points-v2 = <&gpu_mali_opp>; #cooling-cells = <2>; ged-supply = <&ged>; firmware_idle_hytseresis_time_ms = <0>; sleep-mode-enable = <0xff>; pending-submission-mode = <1>; default-glb-pwroff-timeout-us = <300>; }; gpu_mali_opp: opp-table0 { compatible = "operating-points-v2"; opp00 { opp-hz = /bits/ 64 <981000000>; opp-microvolt = <800000>; }; opp01 { opp-hz = /bits/ 64 <965000000>; opp-microvolt = <793750>; }; opp02 { opp-hz = /bits/ 64 <949000000>; opp-microvolt = <787500>; }; opp03 { opp-hz = /bits/ 64 <934000000>; opp-microvolt = <781250>; }; opp04 { opp-hz = /bits/ 64 <918000000>; opp-microvolt = <775000>; }; opp05 { opp-hz = /bits/ 64 <903000000>; opp-microvolt = <768750>; }; opp06 { opp-hz = /bits/ 64 <887000000>; opp-microvolt = <762500>; }; opp07 { opp-hz = /bits/ 64 <872000000>; opp-microvolt = <756250>; }; opp08 { opp-hz = /bits/ 64 <856000000>; opp-microvolt = <750000>; }; opp09 { opp-hz = /bits/ 64 <841000000>; opp-microvolt = <743750>; }; opp10 { opp-hz = /bits/ 64 <825000000>; opp-microvolt = <737500>; }; opp11 { opp-hz = /bits/ 64 <809000000>; opp-microvolt = <731250>; }; opp12 { opp-hz = /bits/ 64 <794000000>; opp-microvolt = <725000>; }; opp13 { opp-hz = /bits/ 64 <778000000>; opp-microvolt = <718750>; }; opp14 { opp-hz = /bits/ 64 <763000000>; opp-microvolt = <712500>; }; opp15 { opp-hz = /bits/ 64 <747000000>; opp-microvolt = <706250>; }; opp16 { opp-hz = /bits/ 64 <732000000>; opp-microvolt = <700000>; }; opp17 { opp-hz = /bits/ 64 <716000000>; opp-microvolt = <693750>; }; opp18 { opp-hz = /bits/ 64 <701000000>; opp-microvolt = <687500>; }; opp19 { opp-hz = /bits/ 64 <685000000>; opp-microvolt = <681250>; }; opp20 { opp-hz = /bits/ 64 <670000000>; opp-microvolt = <675000>; }; opp21 { opp-hz = /bits/ 64 <652000000>; opp-microvolt = <668750>; }; opp22 { opp-hz = /bits/ 64 <635000000>; opp-microvolt = <662500>; }; opp23 { opp-hz = /bits/ 64 <617000000>; opp-microvolt = <656250>; }; opp24 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <650000>; }; opp25 { opp-hz = /bits/ 64 <582000000>; opp-microvolt = <643750>; }; opp26 { opp-hz = /bits/ 64 <565000000>; opp-microvolt = <637500>; }; opp27 { opp-hz = /bits/ 64 <547000000>; opp-microvolt = <631250>; }; opp28 { opp-hz = /bits/ 64 <530000000>; opp-microvolt = <625000>; }; opp29 { opp-hz = /bits/ 64 <512000000>; opp-microvolt = <618750>; }; opp30 { opp-hz = /bits/ 64 <495000000>; opp-microvolt = <612500>; }; opp31 { opp-hz = /bits/ 64 <477000000>; opp-microvolt = <606250>; }; opp32 { opp-hz = /bits/ 64 <460000000>; opp-microvolt = <600000>; }; opp33 { opp-hz = /bits/ 64 <442000000>; opp-microvolt = <593750>; }; opp34 { opp-hz = /bits/ 64 <425000000>; opp-microvolt = <587500>; }; opp35 { opp-hz = /bits/ 64 <407000000>; opp-microvolt = <581250>; }; opp36 { opp-hz = /bits/ 64 <390000000>; opp-microvolt = <575000>; }; opp37 { opp-hz = /bits/ 64 <376000000>; opp-microvolt = <568750>; }; opp38 { opp-hz = /bits/ 64 <362000000>; opp-microvolt = <562500>; }; opp39 { opp-hz = /bits/ 64 <348000000>; opp-microvolt = <556250>; }; opp40 { opp-hz = /bits/ 64 <334000000>; opp-microvolt = <550000>; }; opp41 { opp-hz = /bits/ 64 <320000000>; opp-microvolt = <543750>; }; opp42 { opp-hz = /bits/ 64 <307000000>; opp-microvolt = <537500>; }; opp43 { opp-hz = /bits/ 64 <293000000>; opp-microvolt = <531250>; }; opp44 { opp-hz = /bits/ 64 <279000000>; opp-microvolt = <525000>; }; opp45 { opp-hz = /bits/ 64 <265000000>; opp-microvolt = <518750>; }; opp46 { opp-hz = /bits/ 64 <251000000>; opp-microvolt = <512500>; }; opp47 { opp-hz = /bits/ 64 <237000000>; opp-microvolt = <506250>; }; opp48 { opp-hz = /bits/ 64 <224000000>; opp-microvolt = <500000>; }; }; gpu-fdvfs@112000 { compatible = "mediatek,gpu_fdvfs"; reg = <0 0x112000 0 0x400>; fdvfs-policy-support = <0>; gpu-freq-notify-support = <1>; }; gpu_afs: gpu-afs { compatible = "mediatek,gpu_afs"; afs-policy-support = <1>; }; gpu_qos: gpu-qos { compatible = "mediatek,gpu_qos"; qos-sysram-support = <1>; }; gpu_dcs: gpu-dcs { compatible = "mediatek,gpu_dcs"; dcs-policy-support = <1>; virtual-opp-support = <0x420>; }; gpueb: gpueb@13c00000 { compatible = "mediatek,gpueb"; gpueb-support = <1>; gpueb-logger-support = <0>; mbox_count = <1>; mbox_size = <160>; /* 160 slot * 4 = 640 byte */ slot_size = <4>; /* 1 slot = 4 bytes */ ts_mbox = <0>; /* mbox for timersync */ /* id, mbox, send_size */ send_table = <0 0 4>, <1 0 6>, <2 0 3>, <3 0 6>, <4 0 9>, <5 0 4>, <6 0 6>, <7 0 6>, <8 0 1>, <9 0 4>, <10 0 3>; send_name_table = "IPI_ID_FAST_DVFS_EVENT", "IPI_ID_GPUFREQ", "IPI_ID_SLEEP", "IPI_ID_TIMER", "IPI_ID_FHCTL", "IPI_ID_CCF", "IPI_ID_GPUMPU", "IPI_ID_FAST_DVFS", "CH_IPIR_C_MET", /* = IPIS_C_MET on gpueb side */ "CH_IPIS_C_MET", /* = IPIR_C_MET on gpueb side */ "IPI_ID_BRISKET"; /* id, mbox, recv_size, recv_opt */ recv_table = <0 0 4 0>, <1 0 6 1>, <2 0 1 0>, <3 0 1 0>, <4 0 1 1>, <5 0 4 1>, <6 0 1 1>, <7 0 6 1>, <8 0 4 0>, <9 0 1 1>, <10 0 3 1>; recv_name_table = "IPI_ID_FAST_DVFS_EVENT", "IPI_ID_GPUFREQ", "IPI_ID_SLEEP", "IPI_ID_TIMER", "IPI_ID_FHCTL", "IPI_ID_CCF", "IPI_ID_GPUMPU", "IPI_ID_FAST_DVFS", "CH_IPIR_C_MET", /* = IPIS_C_MET on gpueb side */ "CH_IPIS_C_MET", /* = IPIR_C_MET on gpueb side */ "IPI_ID_BRISKET"; reg = <0 0x13c00000 0 0x30000>, <0 0x13c2fd1c 0 0x64>, <0 0x13c60000 0 0x2000>, <0 0x13c2fd80 0 0x280>, <0 0x13c62004 0 0x4>, <0 0x13c62074 0 0x4>, <0 0x13c62000 0 0x4>, <0 0x13c62078 0 0x4>; reg-names = "gpueb_base", "gpueb_gpr_base", "gpueb_reg_base", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_send", "mbox0_recv"; interrupts = ; interrupt-names = "mbox0"; gpueb_mem_table = <0 0x4000>, /* 16KB */ <1 0x180000>; /* 1.5MB */ gpueb_mem_name_table = "MEM_ID_GPUFREQ", /* GPUFREQ */ "MEM_ID_LOG"; /* LOGGER */ }; gpufreq: gpufreq { compatible = "mediatek,gpufreq"; reg = <0 0x13fbf000 0 0x1000>, /* MFG_TOP_CONFIG */ <0 0x13fa0000 0 0x400>, /* MFG_PLL */ <0 0x13fa0c00 0 0x400>, /* MFGSC_PLL */ <0 0x13f90000 0 0x10000>, /* MFG_RPC */ <0 0x1c001000 0 0x1000>, /* SLEEP */ <0 0x10000000 0 0x1000>, /* TOPCKGEN */ <0 0x1021c000 0 0x1000>, /* NTH_EMICFG */ <0 0x1021e000 0 0x1000>, /* STH_EMICFG */ <0 0x10270000 0 0x1000>, /* NTH_EMICFG_AO_MEM */ <0 0x1030e000 0 0x1000>, /* STH_EMICFG_AO_MEM */ <0 0x1002c000 0 0x1000>, /* IFRBUS_AO */ <0 0x10023000 0 0x1000>, /* INFRA_AO_DEBUG_CTRL */ <0 0x1002b000 0 0x1000>, /* INFRA_AO1_DEBUG_CTRL */ <0 0x10042000 0 0x1000>, /* NTH_EMI_AO_DEBUG_CTRL */ <0 0x10028000 0 0x1000>, /* STH_EMI_AO_DEBUG_CTRL */ <0 0x11e80000 0 0x1000>, /* EFUSE */ <0 0x13fb9c00 0 0x100>, /* MFG_CPE_CTRL_MCU */ <0 0x13fb6000 0 0x1000>, /* MFG_CPE_SENSOR */ <0 0x13fbc000 0 0x1000>, /* MFG_SECURE */ <0 0x1000d000 0 0x1000>, /* DRM_DEBUG */ <0 0x13fe0000 0 0x1000>, /* MFG_IPS */ <0 0x10219000 0 0x1000>, /* EMI_REG */ <0 0x1021d000 0 0x1000>, /* SUB_EMI_REG */ <0 0x1025e000 0 0x1000>, /* NEMI_MI32_SMI_SUB */ <0 0x1025f000 0 0x1000>, /* NEMI_MI33_SMI_SUB */ <0 0x10309000 0 0x1000>, /* SEMI_MI32_SMI_SUB */ <0 0x1030a000 0 0x1000>, /* SEMI_MI33_SMI_SUB */ <0 0x00118800 0 0x2000>; /* SYSRAM_MFG_HISTORY */ reg-names = "mfg_top_config", "mfg_pll", "mfgsc_pll", "mfg_rpc", "sleep", "topckgen", "nth_emicfg", "sth_emicfg", "nth_emicfg_ao_mem", "sth_emicfg_ao_mem", "ifrbus_ao", "infra_ao_debug_ctrl", "infra_ao1_debug_ctrl", "nth_emi_ao_debug_ctrl", "sth_emi_ao_debug_ctrl", "efuse", "mfg_cpe_ctrl_mcu", "mfg_cpe_sensor", "mfg_secure", "drm_debug", "mfg_ips", "emi_reg", "sub_emi_reg", "nemi_mi32_smi_sub", "nemi_mi33_smi_sub", "semi_mi32_smi_sub", "semi_mi33_smi_sub", "sysram_mfg_history"; vgpu-supply = <&mt6373_vbuck4>; vstack-supply = <&mt6373_vbuck2>; vsram-supply = <&mt6373_vsram_digrf_aif>; gpufreq_wrapper-supply = <&gpufreq_wrapper>; }; gpufreq_wrapper: gpufreq_wrapper { compatible = "mediatek,gpufreq_wrapper"; gpufreq-version = <2>; dual-buck = <1>; gpueb-support = <1>; gpufreq-bringup = <0>; }; ged: ged { compatible = "mediatek,ged"; gpufreq-supply = <&gpufreq>; nvmem-cells = <&efuse_segment>; nvmem-cell-names = "mt6985_efuse_segment_cell"; }; srclken_rc: srclken-rc@1c00d000 { compatible = "mediatek,srclken-rc"; reg = <0 0x1c00d000 0 0x100>, <0 0x1c00d100 0 0x700>; mediatek,subsys-ctl = "suspend", "md1", "md2", "md3", "rf", "mmwave", "gps", "pcie", "rsv", "mcu", "co-ant", "nfc", "spm", "ufs"; suspend-ctl = "XO_BBCK1"; md1-ctl = "XO_RFCK2A"; gps-ctl = "XO_RFCK2B"; mcu-ctl = "XO_BBCK2"; pcie_ctl = "XO_BBCK2"; nfc-ctl = "XO_BBCK4"; ufs-ctl = "XO_RFCK1B"; mediatek,srclken-rc-broadcast; mediatek,enable; }; gpio_keys: gpio-keys { compatible = "gpio-keys"; status = "disabled"; }; }; scp: scp@1c700000 { compatible = "mediatek,scp"; status = "okay"; reg = <0 0x1c400000 0 0x300000>, /* tcm */ <0 0x1c724000 0 0x1000>, /* cfg */ <0 0x1c721000 0 0x1000>, /* clk*/ <0 0x1c730000 0 0x1000>, /* cfg core0 */ <0 0x1c740000 0 0x1000>, /* cfg core1 */ <0 0x1c752000 0 0x1000>, /* bus tracker */ <0 0x1c760000 0 0x40000>, /* llc */ <0 0x1c7a5000 0 0x4>, /* cfg_sec */ <0 0x1c7fb000 0 0x100>, /* mbox0 base */ <0 0x1c7fb100 0 0x4>, /* mbox0 set */ <0 0x1c7fb10c 0 0x4>, /* mbox0 clr */ <0 0x1c7a5020 0 0x4>, /* mbox0 init */ <0 0x1c7fc000 0 0x100>, /* mbox1 base */ <0 0x1c7fc100 0 0x4>, /* mbox1 set */ <0 0x1c7fc10c 0 0x4>, /* mbox1 clr */ <0 0x1c7a5024 0 0x4>, /* mbox1 init */ <0 0x1c7fd000 0 0x100>, /* mbox2 base */ <0 0x1c7fd100 0 0x4>, /* mbox2 set */ <0 0x1c7fd10c 0 0x4>, /* mbox2 clr */ <0 0x1c7a5028 0 0x4>, /* mbox2 init */ <0 0x1c7fe000 0 0x100>, /* mbox3 base */ <0 0x1c7fe100 0 0x4>, /* mbox3 set */ <0 0x1c7fe10c 0 0x4>, /* mbox3 clr */ <0 0x1c7a502c 0 0x4>, /* mbox3 init */ <0 0x1c7ff000 0 0x100>, /* mbox4 base */ <0 0x1c7ff100 0 0x4>, /* mbox4 set */ <0 0x1c7ff10c 0 0x4>, /* mbox4 clr */ <0 0x1c7a5030 0 0x4>; /* mbox4 init */ reg-names = "scp_sram_base", "scp_cfgreg", "scp_clkreg", "scp_cfgreg_core0", "scp_cfgreg_core1", "scp_bus_tracker", "scp_l1creg", "scp_cfgreg_sec", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_init", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_init", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_init", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_init", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_init"; interrupts = , , , , , , ; interrupt-names = "ipc0", "ipc1", "mbox0", "mbox1", "mbox2", "mbox3", "mbox4"; core_0 = "enable"; scp-hwvoter = "enable"; scp_sramSize = <0x00300000>; core_nums = <2>; /* core number */ twohart = <1>; /* two hart arch */ mbox_count = <5>; /* id, mbox, send_size*/ send_table = < 0 0 11>,/* IPI_OUT_AUDIO_VOW_1 */ <14 0 1>,/* IPI_OUT_DVFS_SET_FREQ_1 */ <15 0 2>,/* IPI_OUT_C_SLEEP_1 */ <16 0 1>,/* IPI_OUT_TEST_1 */ //<24 0 6>,/* IPI_OUT_SCP_MPOOL_1 */ <17 1 6>,/* IPI_OUT_LOGGER_CTRL */ <18 1 2>,/* IPI_OUT_SCPCTL_1 */ <46 1 1>,/* IPI_OUT_SCP_PM_NOTIFY_1 */ < 4 2 1>,/* IPI_OUT_DVFS_SET_FREQ_0 */ < 5 2 2>,/* IPI_OUT_C_SLEEP_0 */ < 6 2 1>,/* IPI_OUT_TEST_0 */ //<11 2 6>,/* IPI_OUT_SCP_MPOOL_0 */ <33 2 16>,/* IPI_OUT_SCP_CONNSYS */ < 3 3 4>,/* IPI_OUT_APCCCI_0 */ <37 3 1>,/* IPI_OUT_SCP_AOD */ <26 3 9>,/* IPI_OUT_AUDIO_ULTRA_SND_0 */ <35 3 2>,/* IPI_OUT_C_SCP_HWVOTER_DEBUG */ <39 3 4>,/* IPI_OUT_AOV_SCP */ <43 3 4>,/* IPI_OUT_NPU_SCP */ <45 3 1>,/* IPI_OUT_SCP_PM_NOTIFY_0 */ <29 4 16>,/* IPI_OUT_SENSOR_CTRL */ <31 4 7>;/* IPI_OUT_SENSOR_NOTIFY */ #recv_cells_mode = <1>; /* mode 0 or no defined #recv_cells_mode => 4 elements : id, mbox, * recv_size, recv_opt */ /* mode 1 => 7 elements : id, mbox, recv_size, recv_opt, lock, buf_full_opt, * cb_ctx_opt */ recv_table = < 1 0 2 0 0 0 0>,/* IPI_IN_AUDIO_VOW_ACK_1 */ < 2 0 26 0 0 0 0>,/* IPI_IN_AUDIO_VOW_1 */ <36 0 1 0 0 0 0>,/* IPI_IN_AUDIO_ACDDET_1 */ <15 0 1 1 0 0 0>,/* IPI_OUT_C_SLEEP_1 */ //<25 0 6 0 0 0 0>,/* IPI_IN_SCP_MPOOL_1 */ <20 1 10 0 0 0 0>,/* IPI_IN_SCP_ERROR_INFO_1 */ <21 1 6 0 0 0 0>,/* IPI_IN_LOGGER_CTRL */ <22 1 1 0 0 0 0>,/* IPI_IN_SCP_READY_1 */ < 5 2 1 1 0 0 0>,/* IPI_OUT_C_SLEEP_0 */ < 8 2 10 0 0 0 0>,/* IPI_IN_SCP_ERROR_INFO_0 */ //<12 2 6 0 0 0 0>,/* IPI_IN_SCP_MPOOL_0 */ <34 2 16 0 0 0 0>,/* IPI_IN_SCP_CONNSYS */ < 7 3 2 0 0 0 0>,/* IPI_IN_APCCCI_0 */ <38 3 1 0 0 0 0>,/* IPI_IN_SCP_AOD */ <28 3 5 0 0 0 0>,/* IPI_IN_AUDIO_ULTRA_SND_0 */ <27 3 2 0 0 0 0>,/* IPI_IN_AUDIO_ULTRA_SND_ACK_0 */ <35 3 4 1 0 0 0>,/* IPI_OUT_C_SCP_HWVOTER_DEBUG */ <40 3 4 0 0 0 0>,/* IPI_IN_SCP_AOV */ <44 3 4 0 0 0 0>,/* IPI_IN_SCP_NPU */ <30 4 2 0 0 0 0>,/* IPI_IN_SENSOR_CTRL */ <32 4 7 0 0 0 0>;/* IPI_IN_SENSOR_NOTIFY */ //legacy_table = <11>, /* out_id_0 IPI_OUT_SCP_MPOOL_0 */ // <24>, /* out_id_1 IPI_OUT_SCP_MPOOL_1 */ // <12>, /* in_id_0 IPI_IN_SCP_MPOOL_0 */ // <12>, /* in_id_1 IPI_IN_SCP_MPOOL_0 */ // <6>, /* out_size */ // <6>; /* in_size */ /* feature, frequecy, coreid */ scp_feature_tbl = < 0 40 1>, /* vow */ < 1 29 0>, /* sensor */ < 2 26 0>, /* flp */ < 3 0 0>, /* rtos */ < 4 200 1>, /* speaker */ < 5 0 0>, /* vcore */ < 6 135 1>, /* barge in */ < 7 10 1>, /* vow dump */ < 8 80 1>, /* vow vendor M */ < 9 43 1>, /* vow vendor A */ <10 22 1>, /* vow vendor G */ <11 20 1>, /* vow dual mic */ <12 100 1>, /* vow dual mic barge in */ <13 200 0>; /* ultrasound */ scp-dram-region = "enable"; /* enable scp dram region manage */ scp-protect = "enable"; /* enable scp protections */ secure_dump = "enable"; /* enable dump via secure world*/ secure_dump_size = <0x480000>; scp_pm_notify = "enable"; scp-thermal-wq = "enable"; scp_aovmem_key = "mediatek,scp_aov_reserved"; scp_mem_key = "mediatek,reserve-memory-scp_share"; /* feature ID, size, alignment */ scp-mem-tbl = <0 0x0 0x0>, /* secure dump, its size is in secure_dump_size */ <1 0xca700 0x0>, /* vow */ <2 0x100000 0x0>, /* sensor main*/ <3 0x180000 0x0>, /* logger */ <4 0x19000 0x0>, /* audio */ <5 0xa000 0x0>, /* vow bargein */ <7 0x1a000 0x0>, /* ultrasound*/ <8 0x10000 0x0>, /* sensor supper*/ <9 0x1000 0x0>, /* sensor list */ <10 0x2000 0x0>, /* sensor debug */ <11 0x100 0x0>, /* sensor custom writer */ <12 0x100 0x0>, /* sensor custom reader */ <13 0x480000 0x0>, /* aov */ <15 0x10000 0x0>; /* aod */ memorydump = <0x300000>, /* l2tcm */ <0x03c000>, /* l1c */ <0x003c00>, /* regdump */ <0x000400>, /* trace buffer */ <0x100000>; /* dram */ scp-resource-dump = "enable"; /* enable dump scp related resource */ /* regulator */ scp-supply-num = <3>; /* total number of scp related regulator */ vscp0-supply = <&mt6363_vbuck4>; vscp1-supply = <&mt6363_vsram_apu>; vscp2-supply = <&mt6363_vs3>; /* dump register */ /* cell means register info (address,size), not total reg num */ scp-resource-reg-dump-cell = <2>; scp-resource-reg-dump = <0x1C013008 0x4>, <0x1C001908 0x4>, <0x1C001818 0x4>; }; scp_clk_ctrl: scp-clk-ctrl@1c721000 { compatible = "mediatek,scp-clk-ctrl", "syscon"; reg = <0 0x1c721000 0 0x1000>; /* scp clk */ }; scp-dvfs { compatible = "mediatek,scp-dvfs"; clocks = <&vlp_cksys_clk CLK_VLP_CK_SCP_SEL>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>, <&topckgen_clk CLK_TOP_UNIVPLL_D4>, /* 624M */ <&topckgen_clk CLK_TOP_UNIVPLL_D3>, <&topckgen_clk CLK_TOP_MAINPLL_D3>, /* 728M */ <&topckgen_clk CLK_TOP_UNIVPLL_D6>, <&topckgen_clk CLK_TOP_APLL1>, <&topckgen_clk CLK_TOP_MAINPLL_D4>, <&topckgen_clk CLK_TOP_MAINPLL_D7>, <&topckgen_clk CLK_TOP_OSC_D20>; clock-names = "clk_mux", "clk_pll_0", "clk_pll_1", "clk_pll_2", "clk_pll_3", "clk_pll_4", "clk_pll_5", "clk_pll_6", "clk_pll_7", "clk_pll_8"; scp-cores = <2>; vlp-support; vlpck-support; dvfs-opp = /* vscp vsram dvfsrc_opp spm_vcore freq mux resource */ < 575000 750000 0xff 0xfff 300 0 0x0>, < 650000 750000 0xff 0xfff 500 0 0x0>, < 750000 750000 0xff 0xfff 700 0 0x0>; do-ulposc-cali; fmeter-clksys = <&vlp_cksys_clk>; ulposc-clksys = <&vlp_cksys_clk>; scp-clk-ctrl = <&scp_clk_ctrl>; scp-clk-hw-ver = "v1"; ulposc-cali-ver = "v2"; ulposc-cali-num = <4>; ulposc-cali-target = <300 500 620 700>; ulposc-cali-config = /* con0 con1 con2 */ <0x02e292c0 0x2400 0xc>, <0x050a92c0 0x2400 0xc>, <0x064a92c0 0x2400 0xc>, <0x071292c0 0x2400 0xc>; clk-dbg-ver = "v2"; ccf-fmeter-support; scp-dvfs-flag = "enable"; /* enable/disable */ }; gce: gce@1e980000 { compatible = "mediatek,mt6985-gce"; reg = <0 0x1e980000 0 0x4000>; interrupts = ; #mbox-cells = <3>; #gce-event-cells = <1>; #gce-subsys-cells = <2>; default-tokens = /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 ; append-by-event; mboxes = <&gce 13 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; mediatek,smi = <&smi_mdp_2x1_subcommon>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "gce","gce-timer"; prebuilt-enable; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L39_GCE_DM>; dma-mask-bit = <34>; }; gce_sec: gce_mbox_sec@1e980000 { compatible = "mediatek,mailbox-gce-sec"; reg = <0 0x1e980000 0 0x4000>; #mbox-cells = <3>; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; mboxes = <&gce 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>; clock-names = "gce"; dma-mask-bit = <34>; }; gce_m: gce@1e990000 { compatible = "mediatek,mt6985-gce"; reg = <0 0x1e990000 0 0x4000>; interrupts = ; #mbox-cells = <3>; #gce-event-cells = <1>; #gce-subsys-cells = <2>; default-tokens = /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 ; append-by-event; mboxes = <&gce_m 13 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; mediatek,smi = <&smi_mdp_2x1_subcommon>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "gce","gce-timer"; prebuilt-enable; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L39_GCE_MM>; dma-mask-bit = <34>; }; gce_m_sec: gce_mbox_m_sec@1e990000 { compatible = "mediatek,mailbox-gce-sec"; reg = <0 0x1e990000 0 0x4000>; #mbox-cells = <3>; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; mboxes = <&gce_m 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_M>; clock-names = "gce"; dma-mask-bit = <34>; }; cmdq-test { compatible = "mediatek,cmdq-test"; mediatek,gce = <&gce_m>; mediatek,gce-subsys = <99>, ; mboxes = <&gce_m 12 0 CMDQ_THR_PRIO_1>, <&gce 12 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>, <&gce_m_sec 9 0 CMDQ_THR_PRIO_1>; token-user0 = /bits/ 16 ; token-gpr-set4 = /bits/ 16 ; token-tzmp-aie-wait = /bits/ 16 ; }; mminfra-imax { compatible = "mediatek,mminfra-imax"; reg = <0 0x14400000 0 0x1000>, /* dispsys */ <0 0x14600000 0 0x1000>, /* dispsys1 */ <0 0x1f000000 0 0x1000>, /* mdpsys */ <0 0x1f800000 0 0x1000>, /* mdpsys1 */ <0 0x1440c000 0 0x1000>, /* disp_larb_0 */ <0 0x1440d000 0 0x1000>, /* disp_larb_1 */ <0 0x1460c000 0 0x1000>, /* disp_larb_2 */ <0 0x1460d000 0 0x1000>, /* disp_larb_3 */ <0 0x1f002000 0 0x1000>, /* mdp_larb_0 */ <0 0x1f802000 0 0x1000>; /* mdp_larb_1 */ disp-larb0-fake-port = <8>; disp-larb1-fake-port = <7>; disp-larb2-fake-port = <8>; disp-larb3-fake-port = <7>; mdp-larb0-fake-port = <2>; mdp-larb1-fake-port = <2>; mm-sram-base = <0x0f000000>; reg-names = "dispsys", "dispsys1", "mdpsys", "mdpsys1", "disp_larb_0", "disp_larb_1", "disp_larb_2", "disp_larb_3", "mdp_larb_0", "mdp_larb_1"; }; connfem: connfem { compatible = "mediatek,mt6985-connfem"; }; swpm: swpm { compatible = "mediatek,mtk-swpm"; pmu-boundary-num = <0>; pmu-dsu-support = <1>; pmu-dsu-type = <11>; }; gps: gps@18c00000 { compatible = "mediatek,mt6985-gps"; reg = <0 0x18000000 0 0x100000>, <0 0x18c00000 0 0x100000>, <0 0x18d00000 0 0x100000>, <0 0x1c000000 0 0x4>, <0 0x1c805028 0 0x4>, <0 0x1c805030 0 0x4>, <0 0x1c8050cc 0 0x28>; reg-names = "conn_infra_base", "conn_gps_base", "conn_dyn_base", "status_dummy_cr", "tia2_gps_on", "tia2_gps_rc_sel", "tia2_gps_debug"; interrupts = , , , , , , , , , , /* gps mcu wdt irq */ ; emi-connac-ver = <2>; emi-addr = <0>; emi-size = <0x100000>; emi-alignment = <0x100000>; emi-max-addr = <0xc0000000>; b13b14-status-addr = <0x1c000008>; }; sleep@1c001000 { compatible = "mediatek,sleep"; reg = <0 0x1c001000 0 0x1000>; interrupts = ; }; mtk_lpm: mtk_lpm { compatible = "mediatek,mtk-lpm"; #address-cells = <2>; #size-cells = <2>; ranges; lpm-kernel-suspend = <0>; suspend-method = "enable"; logger-enable-states = "mcusysoff_l", "mcusysoff_m", "mcusysoff_b", "system_mem", "system_pll", "system_bus", "system_vcore"; irq-remain = <&edge_keypad>, <&level_apdma>, <&level_ufshci>, <&level_usb_host>, <&level_apusys_rv_mbox0 &level_apusys_rv_mbox1>, <&level_vcpsys_rv_mbox0>, <&level_disp_ccorr0_0>; resource-ctrl = <&bus26m &infra &syspll>, <&dram_s0 &dram_s1>; constraints = <&rc_bus26m &rc_syspll &rc_vcore>; spm-cond = <&spm_cond_pll>; cg-shift = <0>; /* cg blocking index */ pll-shift = <0>; /* pll blocking index */ power-gs = <0>; mcusys-cnt-chk = <1>; hwreq = "hw_cg", "peri_req"; cpupm_sysram: cpupm-sysram@0011b000 { compatible = "mediatek,cpupm-sysram"; reg = <0 0x0011b000 0 0x500>; }; mcusys_ctrl: mcusys-ctrl@0c040000 { compatible = "mediatek,mcusys-ctrl"; reg = <0 0x0c040000 0 0x1000>; }; lpm_sysram: lpm_sysram@0011b500 { compatible = "mediatek,lpm-sysram"; reg = <0 0x0011b500 0 0x300>; }; irq-remain-list { edge_keypad: edge_keypad { target = <&keypad>; value = <1 0 0 0x04>; }; level_apdma: level_apdma { target = <&apdma>; value = <0 0 0 0>; }; level_ufshci: level_ufshci { target = <&ufshci>; value = <0 0 0 0>; }; level_usb_host: level_usb_host { target = <&usb_host>; value = <0 0 0 0>; }; level_apusys_rv_mbox0: level-apusys-rv-mbox0 { target = <&apusys_rv>; value = <0 1 0 0>; }; level_apusys_rv_mbox1: level-apusys-rv-mbox1 { target = <&apusys_rv>; value = <0 2 0 0>; }; level_vcpsys_rv_mbox0: level-vcpsys-rv-mbox0 { target = <&vcp>; value = <0 2 0 0>; }; level_disp_ccorr0_0: level-disp-ccorr0-0 { target = <&disp_ccorr0_0>; value = <0 0 0 0>; }; }; resource-ctrl-list { bus26m: bus26m { id = <0x00000000>; value = <0>; }; infra: infra { id = <0x00000001>; value = <0>; }; syspll: syspll { id = <0x00000002>; value = <0>; }; dram_s0: dram_s0 { id = <0x00000003>; value = <0>; }; dram_s1: dram_s1 { id = <0x00000004>; value = <0>; }; spm_vcore: spm_vcore { id = <0x00000005>; value = <0>; }; spm_emi: spm_emi { id = <0x00000006>; value = <0>; }; spm_pmic: spm_pmic { id = <0x00000007>; value = <0>; }; }; constraint-list { rc_syspll: rc_syspll { rc-name = "syspll"; id = <0x00000002>; value = <1>; cond-info = <1>; }; rc_bus26m: rc_bus26m { rc-name = "bus26m"; id = <0x00000001>; value = <1>; cond-info = <1>; }; rc_vcore: rc_vcore { rc-name = "vcore"; id = <0x00000000>; value = <1>; cond-info = <1>; }; }; spm-cond-list { spm_cond_pll: spm_cond_pll { pll-name = "UNIVPLL2", "MFGPLL", "MFGSCPLL", "SENSONPLL", "MM2PLL", "MAIN2PLL", "ADSPPLL", "APLL1", "APLL2"; }; }; power-gs-list { }; }; dispsys_config: dispsys-config@14000000 { compatible = "mediatek,mt6985-disp"; mediatek,mml = <&mmlsys_config>; dispsys_num = <2>; ovlsys_num = <2>; reg = <0 0x14000000 0 0x1000>, <0 0x14200000 0 0x1000>, <0 0x14400000 0 0x1000>, <0 0x14600000 0 0x1000>; #address-cells = <2>; #size-cells = <2>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL1_2L_RDMA1>; // mediatek,larb = <&smi_larb0>; // fake-engine = <&smi_larb0 M4U_PORT_L0_DISP_FAKE0>, // <&smi_larb1 M4U_PORT_L1_DISP_FAKE1>; #clock-cells = <1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS0_SHUTDOWN>; pd-others = <&disp_mutex0>, <&disp_ovl0_2l>, <&disp1_ovl0_2l>; pd-names = "side_dispsys", "ovlsys", "side_ovlsys"; clocks = <&dispsys_config_clk CLK_MM_CONFIG>, <&dispsys_config_clk CLK_MM_DISP_MUTEX0>, <&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC0>, <&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC1>, <&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC2>, <&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC3>, <&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC4>, <&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC5>, <&dispsys_config_clk CLK_MM_DISP_DLO_ASYNC0>, <&dispsys_config_clk CLK_MM_DISP_DLO_ASYNC1>, <&dispsys_config_clk CLK_MM_DISP_RELAY0>, <&dispsys_config_clk CLK_MM_26M_CLK>, <&dispsys1_config_clk CLK_MM1_CONFIG>, <&dispsys1_config_clk CLK_MM1_DISP_MUTEX0>, <&dispsys1_config_clk CLK_MM1_DISP_DLI_ASYNC0>, <&dispsys1_config_clk CLK_MM1_DISP_DLI_ASYNC1>, <&dispsys1_config_clk CLK_MM1_DISP_DLI_ASYNC2>, <&dispsys1_config_clk CLK_MM1_DISP_DLI_ASYNC3>, <&dispsys1_config_clk CLK_MM1_DISP_DLI_ASYNC4>, <&dispsys1_config_clk CLK_MM1_DISP_DLI_ASYNC5>, <&dispsys1_config_clk CLK_MM1_DISP_DLO_ASYNC0>, <&dispsys1_config_clk CLK_MM1_DISP_DLO_ASYNC1>, <&dispsys1_config_clk CLK_MM1_DISP_RELAY0>, <&dispsys1_config_clk CLK_MM1_26M_CLK>, <&ovlsys_config_clk CLK_OVL_CONFIG>, <&ovlsys_config_clk CLK_OVL_DISP_MUTEX0>, <&ovlsys_config_clk CLK_OVL_DISP_DLI_ASYNC0>, <&ovlsys_config_clk CLK_OVL_DISP_DLI_ASYNC1>, <&ovlsys_config_clk CLK_OVL_DISP_DLI_ASYNC2>, <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC0>, <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC1>, <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC2>, <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC3>, <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC4>, <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC5>, <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC6>, <&ovlsys1_config_clk CLK_OVL1_CONFIG>, <&ovlsys1_config_clk CLK_OVL1_DISP_MUTEX0>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLI_ASYNC0>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLI_ASYNC1>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLI_ASYNC2>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC0>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC1>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC2>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC3>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC4>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC5>, <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC6>; clock-num = <48>; condition-num = <2>; operating-points-v2 = <&opp_table_disp>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; lp-mmclk-freq = <218000000>; interconnects = <&mmqos SLAVE_LARB(38) &mmqos SLAVE_COMMON(0)>; interconnect-names = "disp_hrt_qos"; pre-define-bw = <0xffffffff>, <4200>, <0>, <2700>; crtc-ovl-usage = <7>, <4>, <2>; /* define threads, see mt6873-gce.h */ mediatek,mailbox-gce = <&gce>; mboxes = <&gce 0 0 CMDQ_THR_PRIO_4>, <&gce 1 0 CMDQ_THR_PRIO_4>, <&gce 2 0 CMDQ_THR_PRIO_4>, <&gce 24 0 CMDQ_THR_PRIO_4>, <&gce 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>, <&gce 5 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>, <&gce 25 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>, <&gce 7 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>, <&gce 4 0 CMDQ_THR_PRIO_4>, <&gce 6 0 CMDQ_THR_PRIO_3>, <&gce 22 0 CMDQ_THR_PRIO_1>; // <&gce_sec 8 0 CMDQ_THR_PRIO_3>, // <&gce_sec 9 0 CMDQ_THR_PRIO_3>, // <&gce_sec 9 0 CMDQ_THR_PRIO_3>; gce-client-names = "CLIENT_CFG0", "CLIENT_CFG1", "CLIENT_CFG2", "CLIENT_CFG3", "CLIENT_TRIG_LOOP0", "CLIENT_TRIG_LOOP1", "CLIENT_TRIG_LOOP3", "CLIENT_EVENT_LOOP0", "CLIENT_SUB_CFG0", "CLIENT_DSI_CFG0", "CLIENT_PQ0"; // "CLIENT_SEC_CFG0", // "CLIENT_SEC_CFG1", // "CLIENT_SEC_CFG2"; /* define subsys, see mt6985-gce.h */ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, <&gce 0x14010000 SUBSYS_1401XXXX>, <&gce 0x14020000 SUBSYS_1402XXXX>; /* define subsys, see mt6985-gce.h */ gce-event-names = "disp_mutex0_eof", "disp_mutex1_eof", "disp_token_stream_dirty0", "disp_token_stream_dirty1", "disp_token_stream_dirty3", "disp_wait_dsi0_te", "disp_wait_dsi1_te", "disp_token_stream_eof0", "disp_token_stream_eof1", "disp_token_stream_eof3", "disp_dsi0_eof", "disp_dsi1_eof", "disp_token_esd_eof0", "disp_token_esd_eof1", "disp_token_esd_eof3", "disp_rdma0_eof0", "disp_wdma0_eof0", "disp_token_stream_block0", "disp_token_stream_block1", "disp_token_stream_block3", "disp_token_cabc_eof0", "disp_token_cabc_eof1", "disp_token_cabc_eof3", "disp_wdma0_eof2", "disp_wait_dp_intf0_te", "disp_dp_intf0_eof", "disp_mutex2_eof", "disp_ovlsys_wdma2_eof2", "disp_dsi0_sof0", "disp_dsi1_sof0", "disp_token_vfp_period0", "disp_token_disp_va_start0", "disp_token_disp_va_end0", "disp_token_disp_va_start2", "disp_token_disp_va_end2", "disp_token_disp_te0", "disp_token_disp_prefetch_te0", "disp_gpio_te0", "disp_gpio_te1", "disp_dsi0_targetline0", "disp_ovlsys_wdma0_eof0", "disp_token_disp_v_idle_power_on0", "disp_token_disp_check_trigger_merge0", "disp_ovlsys_wdma1_eof0", "disp_mdp_rdma0_eof3", "disp_mdp_rdma1_eof3"; gce-events = <&gce CMDQ_EVENT_OVLSYS_STREAM_DONE_ENG_EVENT_0>, <&gce CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_FRAME_DONE>, <&gce CMDQ_SYNC_TOKEN_CONFIG_DIRTY>, <&gce CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1>, <&gce CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_TE_ENG_EVENT>, <&gce CMDQ_EVENT_DISPSYS1_DISP_DSI0_TE_ENG_EVENT>, <&gce CMDQ_SYNC_TOKEN_STREAM_EOF>, <&gce CMDQ_SYNC_TOKEN_STREAM_EOF_1>, <&gce CMDQ_SYNC_TOKEN_STREAM_EOF_3>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS1_DISP_DSI0_FRAME_DONE>, <&gce CMDQ_SYNC_TOKEN_ESD_EOF>, <&gce CMDQ_SYNC_TOKEN_ESD_EOF_1>, <&gce CMDQ_SYNC_TOKEN_ESD_EOF_3>, <&gce CMDQ_EVENT_DISPSYS_DISP_MDP_RDMA0_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS_DISP_WDMA1_FRAME_DONE>, <&gce CMDQ_SYNC_TOKEN_STREAM_BLOCK>, <&gce CMDQ_SYNC_TOKEN_STREAM_BLOCK_1>, <&gce CMDQ_SYNC_TOKEN_STREAM_BLOCK_3>, <&gce CMDQ_SYNC_TOKEN_CABC_EOF>, <&gce CMDQ_SYNC_TOKEN_CABC_EOF_1>, <&gce CMDQ_SYNC_TOKEN_CABC_EOF_3>, <&gce CMDQ_EVENT_DISPSYS_DISP_WDMA1_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS_DISP_DP_INTF0_SOF>, <&gce CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS1_DISP_DP_INTF0_FRAME_DONE>, <&gce CMDQ_EVENT_OVLSYS1_DISP_WDMA0_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_SOF>, <&gce CMDQ_EVENT_DISPSYS1_DISP_DSI0_SOF>, <&gce CMDQ_SYNC_TOKEN_VFP_PERIOD>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_START>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_END>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_START>, <&gce CMDQ_SYNC_TOKEN_DISP_VA_END>, <&gce CMDQ_SYNC_TOKEN_TE_0>, <&gce CMDQ_SYNC_TOKEN_PREFETCH_TE_0>, <&gce CMDQ_EVENT_GCE_EVENT_DSI0_TE_I>, <&gce CMDQ_EVENT_GCE_EVENT_DSI1_TE_I>, <&gce CMDQ_EVENT_DISPSYS_DISP_DSI0_TARGET_LINE_ENG_EVENT>, <&gce CMDQ_EVENT_OVLSYS_DISP_WDMA0_FRAME_DONE>, <&gce CMDQ_SYNC_TOKEN_VIDLE_POWER_ON>, <&gce CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE>, <&gce CMDQ_EVENT_OVLSYS_DISP_WDMA2_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS_DISP_MDP_RDMA0_FRAME_DONE>, <&gce CMDQ_EVENT_DISPSYS1_DISP_MDP_RDMA0_FRAME_DONE>; helper-name = "MTK_DRM_OPT_STAGE", "MTK_DRM_OPT_USE_CMDQ", "MTK_DRM_OPT_USE_M4U", "MTK_DRM_OPT_MMQOS_SUPPORT", "MTK_DRM_OPT_MMDVFS_SUPPORT", "MTK_DRM_OPT_SODI_SUPPORT", "MTK_DRM_OPT_IDLE_MGR", "MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE", "MTK_DRM_OPT_IDLEMGR_BY_REPAINT", "MTK_DRM_OPT_IDLEMGR_ENTER_ULPS", "MTK_DRM_OPT_IDLEMGR_KEEP_LP11", "MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING", "MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ", "MTK_DRM_OPT_MET_LOG", "MTK_DRM_OPT_USE_PQ", "MTK_DRM_OPT_ESD_CHECK_RECOVERY", "MTK_DRM_OPT_ESD_CHECK_SWITCH", "MTK_DRM_OPT_PRESENT_FENCE", "MTK_DRM_OPT_RDMA_UNDERFLOW_AEE", "MTK_DRM_OPT_DSI_UNDERRUN_AEE", "MTK_DRM_OPT_ODDMR_OD_AEE", "MTK_DRM_OPT_ODDMR_DMR_AEE", "MTK_DRM_OPT_HRT", "MTK_DRM_OPT_HRT_MODE", "MTK_DRM_OPT_DELAYED_TRIGGER", "MTK_DRM_OPT_OVL_EXT_LAYER", "MTK_DRM_OPT_AOD", "MTK_DRM_OPT_RPO", "MTK_DRM_OPT_DUAL_PIPE", "MTK_DRM_OPT_DC_BY_HRT", "MTK_DRM_OPT_OVL_WCG", "MTK_DRM_OPT_OVL_SBCH", "MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK", "MTK_DRM_OPT_MET", "MTK_DRM_OPT_REG_PARSER_RAW_DUMP", "MTK_DRM_OPT_VP_PQ", "MTK_DRM_OPT_GAME_PQ", "MTK_DRM_OPT_MMPATH", "MTK_DRM_OPT_HBM", "MTK_DRM_OPT_VDS_PATH_SWITCH", "MTK_DRM_OPT_LAYER_REC", "MTK_DRM_OPT_CLEAR_LAYER", "MTK_DRM_OPT_LFR", "MTK_DRM_OPT_SF_PF", "MTK_DRM_OPT_DYN_MIPI_CHANGE", "MTK_DRM_OPT_PRIM_DUAL_PIPE", "MTK_DRM_OPT_MSYNC2_0", "MTK_DRM_OPT_MML_PRIMARY", "MTK_DRM_OPT_MML_SUPPORT_CMD_MODE", "MTK_DRM_OPT_MML_PQ", "MTK_DRM_OPT_MML_IR", "MTK_DRM_OPT_DUAL_TE", "MTK_DRM_OPT_RES_SWITCH", "MTK_DRM_OPT_RES_SWITCH_ON_AP", "MTK_DRM_OPT_PREFETCH_TE", "MTK_DRM_OPT_VIDLE_APSRC_OFF", "MTK_DRM_OPT_VIDLE_DSI_PLL_OFF", "MTK_DRM_OPT_CHECK_TRIGGER_MERGE", "MTK_DRM_OPT_VIRTUAL_DISP", "MTK_DRM_OPT_OVL_BW_MONITOR", "MTK_DRM_OPT_GPU_CACHE", "MTK_DRM_OPT_SPHRT", "MTK_DRM_OPT_SDPA_OVL_SWITCH", "MTK_DRM_OPT_TILE_OVERHEAD"; helper-value = <0>, /*MTK_DRM_OPT_STAGE*/ <1>, /*MTK_DRM_OPT_USE_CMDQ*/ <1>, /*MTK_DRM_OPT_USE_M4U*/ <1>, /*MTK_DRM_OPT_MMQOS_SUPPORT*/ <1>, /*MTK_DRM_OPT_MMDVFS_SUPPORT*/ <0>, /*MTK_DRM_OPT_SODI_SUPPORT*/ <1>, /*MTK_DRM_OPT_IDLE_MGR*/ <0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/ <1>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/ <0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/ <0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/ <0>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/ <1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/ <0>, /*MTK_DRM_OPT_MET_LOG*/ <1>, /*MTK_DRM_OPT_USE_PQ*/ <1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/ <1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/ <1>, /*MTK_DRM_OPT_PRESENT_FENCE*/ <0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/ <0>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/ <0>, /*MTK_DRM_OPT_ODDMR_OD_AEE*/ <0>, /*MTK_DRM_OPT_ODDMR_DMR_AEE*/ <1>, /*MTK_DRM_OPT_HRT*/ <1>, /*MTK_DRM_OPT_HRT_MODE*/ <0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/ <1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/ <0>, /*MTK_DRM_OPT_AOD*/ <1>, /*MTK_DRM_OPT_RPO*/ <0>, /*MTK_DRM_OPT_DUAL_PIPE*/ <0>, /*MTK_DRM_OPT_DC_BY_HRT*/ <0>, /*MTK_DRM_OPT_OVL_WCG*/ <0>, /*MTK_DRM_OPT_OVL_SBCH*/ <1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/ <0>, /*MTK_DRM_OPT_MET*/ <0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/ <0>, /*MTK_DRM_OPT_VP_PQ*/ <0>, /*MTK_DRM_OPT_GAME_PQ*/ <0>, /*MTK_DRM_OPT_MMPATH*/ <0>, /*MTK_DRM_OPT_HBM*/ <0>, /*MTK_DRM_OPT_VDS_PATH_SWITCH*/ <0>, /*MTK_DRM_OPT_LAYER_REC*/ <1>, /*MTK_DRM_OPT_CLEAR_LAYER*/ <0>, /*MTK_DRM_OPT_LFR*/ <0>, /*MTK_DRM_OPT_SF_PF*/ <1>, /*MTK_DRM_OPT_DYN_MIPI_CHANGE*/ <1>, /*MTK_DRM_OPT_PRIM_DUAL_PIPE*/ <1>, /*MTK_DRM_OPT_MSYNC2_0*/ <1>, /*MTK_DRM_OPT_MML_PRIMARY*/ <1>, /*MTK_DRM_OPT_MML_SUPPORT_CMD_MODE*/ <1>, /*MTK_DRM_OPT_MML_PQ*/ <1>, /*MTK_DRM_OPT_MML_IR*/ <0>, /*MTK_DRM_OPT_DUAL_TE*/ <1>, /*MTK_DRM_OPT_RES_SWITCH*/ <1>, /*MTK_DRM_OPT_RES_SWITCH_ON_AP*/ <0>, /*MTK_DRM_OPT_PREFETCH_TE*/ <0>, /*MTK_DRM_OPT_VIDLE_APSRC_OFF*/ <0>, /*MTK_DRM_OPT_VIDLE_DSI_PLL_OFF*/ <1>, /*MTK_DRM_OPT_CHECK_TRIGGER_MERGE*/ <1>, /*MTK_DRM_OPT_VIRTUAL_DISP*/ <0>, /*MTK_DRM_OPT_OVL_BW_MONITOR*/ <0>, /*MTK_DRM_OPT_GPU_CACHE*/ <1>, /*MTK_DRM_OPT_SPHRT*/ <1>, /*MTK_DRM_OPT_SDPA_OVL_SWITCH*/ <1>; /*MTK_DRM_OPT_TILE_OVERHEAD*/ }; disp_ssc0_smi_2x1_sub_comm: disp-ssc0-smi-2x1-sub-comm@1e809000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e809000 0 0x1000>; mediatek,common-id = <3>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; disp_ssc1_smi_2x1_sub_comm: disp-ssc1-smi-2x1-sub-comm@1e80a000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e80a000 0 0x1000>; mediatek,common-id = <4>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; mdp_ssc4_smi_2x1_sub_comm: mdp-ssc4-smi-2x1-sub-comm@1e817000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e817000 0 0x1000>; mediatek,common-id = <5>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; mdp_ssc5_smi_2x1_sub_comm: mdp-ssc5-smi-2x1-sub-comm@1e818000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e818000 0 0x1000>; mediatek,common-id = <6>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; mmsram_smi_2x1_sub_comm3: mmsram-smi-2x1-sub-comm3@1e80d000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e80d000 0 0x1000>; mediatek,common-id = <7>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; mmsram_smi_2x1_sub_comm4: mmsram-smi-2x1-sub-comm4@1e80e000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e80e000 0 0x1000>; mediatek,common-id = <8>; mediatek,dump-with-comm = <2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_disp_common: smi-disp-comm@1e801000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon"; reg = <0 0x1e801000 0 0x1000>; mediatek,smi = <&disp_ssc0_smi_2x1_sub_comm &disp_ssc1_smi_2x1_sub_comm>; mediatek,common-id = <0>; emimpu-check; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; operating-points-v2 = <&opp_table_mminfra>; smi-common; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_mdp_common: smi-mdp-comm@1e80f000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon"; reg = <0 0x1e80f000 0 0x1000>; mediatek,smi = <&mdp_ssc4_smi_2x1_sub_comm &mdp_ssc5_smi_2x1_sub_comm>; mediatek,common-id = <1>; emimpu-check; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; operating-points-v2 = <&opp_table_mminfra>; smi-common; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_sysram_common: smi-sysram-comm@1e80b000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon"; reg = <0 0x1e80b000 0 0x1000>; mediatek,smi = <&mmsram_smi_2x1_sub_comm3 &mmsram_smi_2x1_sub_comm4>; mediatek,common-id = <2>; emimpu-check; smi-common; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_mdp_2x1_subcommon: smi-mdp-2x1-subcommon@1e819000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1e819000 0 0x1000>; mediatek,smi = <&smi_mdp_common>; mediatek,common-id = <9>; mediatek,dump-with-comm = <1>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_dram_disp1_2x1_subcomm1: smi-dram-disp1-2x1-subcomm1@1421e000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1421e000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,common-id = <11>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS1_SHUTDOWN>; clocks = <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_sram_disp1_2x1_subcomm1: smi-sram-disp1-2x1-subcomm1@1421f000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1421f000 0 0x1000>; mediatek,smi = <&smi_sysram_common>; mediatek,common-id = <12>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS1_SHUTDOWN>; clocks = <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_dram_disp1_2x1_subcomm0: smi-dram-disp1-2x1-subcomm0@1401e000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1401e000 0 0x1000>; mediatek,smi = <&smi_mdp_common>; mediatek,common-id = <13>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS0_SHUTDOWN>; clocks = <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_sram_disp1_2x1_subcomm0: smi-sram-disp1-2x1-subcomm0@1401f000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1401f000 0 0x1000>; mediatek,smi = <&smi_sysram_common>; mediatek,common-id = <14>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS0_SHUTDOWN>; clocks = <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_sram_ovl_2x1_subcomm0: smi-sram-ovl-2x1-subcomm0@1440e000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1440e000 0 0x1000>; mediatek,smi = <&smi_sram_disp1_2x1_subcomm0>; mediatek,common-id = <22>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS_SHUTDOWN>; clocks = <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_sram_ovl_2x1_subcomm1: smi-sram-ovl-2x1-subcomm1@1460e000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1460e000 0 0x1000>; mediatek,smi = <&smi_sram_disp1_2x1_subcomm1>; mediatek,common-id = <23>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS1_SHUTDOWN>; clocks = <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_disp_img_4x1_subcomm0: smi-disp-img-4x1-subcomm0@15002000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x15002000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,common-id = <15>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; clocks = <&imgsys_main_clk CLK_IMG_DIP0>, <&imgsys_main_clk CLK_IMG_WPE1>, <&imgsys_main_clk CLK_IMG_WPE2>, <&imgsys_main_clk CLK_IMG_TRAW0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_mdp_img_5x1_subcomm1: smi-mdp-img-5x1-subcomm1@15003000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x15003000 0 0x1000>; mediatek,smi = <&smi_mdp_common>; mediatek,common-id = <18>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; clocks = <&imgsys_main_clk CLK_IMG_WPE0>, <&imgsys_main_clk CLK_IMG_IPE>, <&imgsys_main_clk CLK_IMG_DIP0>, <&imgsys_main_clk CLK_IMG_DIP0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_disp_cam_8x1_subcomm0: smi-disp-cam-8x1-subcomm0@1a005000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1a005000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,common-id = <16>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBA_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBB_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBC_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBC_CON_0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_mdp_cam_7x1_subcomm1: smi-mdp-cam-7x1-subcomm1@1a006000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1a006000 0 0x1000>; mediatek,smi = <&smi_mdp_common>; mediatek,common-id = <19>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_sram_cam_2x1_subcomm2: smi-sram-cam-2x1-subcomm2@1a007000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x1a007000 0 0x1000>; mediatek,smi = <&smi_sysram_common>; mediatek,common-id = <20>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_mdp_venc_2x1_subcomm0: smi-mdp-venc-2x1-subcomm0@17870000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x17870000 0 0x1000>; mediatek,common-id = <17>; emimpu-check; mediatek,smi = <&smi_mdp_common>; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN1>; clocks = <&venc_gcon_core1_clk CLK_VEN_C1_CKE0_LARB>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE0_LARB>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE1_VENC>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE1_VENC>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_sram_venc_2x1_subcomm1: smi-sram-venc-2x1-subcomm1@17880000 { compatible = "mediatek,mt6985-smi-common", "mediatek,smi-common", "syscon", "mediatek,smi-sub-common"; reg = <0 0x17880000 0 0x1000>; mediatek,smi = <&smi_sysram_common>; mediatek,common-id = <21>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN1>; clocks = <&venc_gcon_core1_clk CLK_VEN_C1_CKE0_LARB>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE0_LARB>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE1_VENC>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE1_VENC>; clock-names = "apb", "smi", "gals0", "gals1"; }; smi_pd_ovl0: smi-pd-ovl0 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common &smi_dram_disp1_2x1_subcomm0 &smi_sram_disp1_2x1_subcomm0>; mediatek,suspend-check-port = <0x1 0x1 0x2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS_SHUTDOWN>; init-power-on; suspend-check; }; smi_pd_ovl1: smi-pd-ovl1 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_common &smi_dram_disp1_2x1_subcomm1 &smi_sram_disp1_2x1_subcomm1>; mediatek,suspend-check-port = <0x2 0x1 0x2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS1_SHUTDOWN>; init-power-on; suspend-check; }; smi_pd_dis0: smi-pd-dis0 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_common &smi_sysram_common>; mediatek,suspend-check-port = <0x1 0x2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS0_SHUTDOWN>; init-power-on; suspend-check; }; smi_pd_dis1: smi-pd-dis1 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common &smi_sysram_common>; mediatek,suspend-check-port = <0x2 0x4>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS1_SHUTDOWN>; init-power-on; suspend-check; }; smi_pd_mdp0: smi-pd-mdp0 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common>; mediatek,suspend-check-port = <0x4>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MDP0_SHUTDOWN>; suspend-check; }; smi_pd_mdp1: smi-pd-mdp1 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_2x1_subcommon &smi_sysram_common>; mediatek,suspend-check-port = <0x1 0x10>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MDP1_SHUTDOWN>; suspend-check; }; smi_pd_venc0: smi-pd-venc0 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common &smi_sysram_common>; mediatek,suspend-check-port = <0x10 0x20>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN0>; suspend-check; }; smi_pd_venc1: smi-pd-venc1 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_common &smi_sysram_common>; mediatek,suspend-check-port = <0x10 0x40>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN1>; suspend-check; }; smi_pd_venc2: smi-pd-venc2 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_venc_2x1_subcomm0 &smi_sram_venc_2x1_subcomm1>; mediatek,suspend-check-port = <0x2 0x2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN2>; suspend-check; }; smi_pd_vdec0: smi-pd-vdec0 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common>; mediatek,suspend-check-port = <0x88>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE0>; suspend-check; }; smi_pd_vdec1: smi-pd-vdec1 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_common>; mediatek,suspend-check-port = <0x8>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE1>; suspend-check; }; smi_pd_isp_main: smi-pd-isp-main { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_common &smi_disp_common>; mediatek,suspend-check-port = <0x20 0x20>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; suspend-check; }; smi_pd_isp_dip1: smi-pd-isp-dip1 { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_mdp_img_5x1_subcomm1 &smi_disp_img_4x1_subcomm0>; mediatek,suspend-check-port = <0x6 0xf>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_DIP1>; suspend-check; }; smi_pd_cam_main: smi-pd-cam-main { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_common &smi_mdp_common &smi_sysram_common>; mediatek,suspend-check-port = <0x40 0x40 0x8>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; suspend-check; }; smi_pd_cam_suba: smi-pd-cam-suba { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_cam_8x1_subcomm0 &smi_mdp_cam_7x1_subcomm1>; mediatek,suspend-check-port = <0x21 0x4>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBA>; suspend-check; }; smi_pd_cam_subb: smi-pd-cam-subb { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_cam_8x1_subcomm0 &smi_mdp_cam_7x1_subcomm1>; mediatek,suspend-check-port = <0x4 0x2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBB>; suspend-check; }; smi_pd_cam_subc: smi-pd-cam-subc { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_cam_8x1_subcomm0 &smi_mdp_cam_7x1_subcomm1>; mediatek,suspend-check-port = <0x42 0x8>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBC>; suspend-check; }; smi_pd_cam_mraw: smi-pd-cam-mraw { compatible = "mediatek,smi-pd"; mediatek,suspend-check-dev = <&smi_disp_cam_8x1_subcomm0 &smi_mdp_cam_7x1_subcomm1 &smi_sram_cam_2x1_subcomm2>; mediatek,suspend-check-port = <0x18 0x10 0x2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; suspend-check; }; smi_larb0: smi-larb0@1440c000 { compatible = "mediatek,smi_larb0", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1440c000 0 0x1000>; mediatek,smi = <&smi_disp_common &smi_sram_ovl_2x1_subcomm0>; mediatek,larb-id = <0>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS_SHUTDOWN>; clocks = <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>; clock-names = "apb", "smi", "gals"; }; smi_larb1: smi-larb1@1440d000 { compatible = "mediatek,smi_larb1", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1440d000 0 0x1000>; mediatek,smi = <&smi_dram_disp1_2x1_subcomm0 &smi_sram_ovl_2x1_subcomm0>; mediatek,larb-id = <1>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS_SHUTDOWN>; clocks = <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>, <&ovlsys_config_clk CLK_OVL_SMI_SUB_COMMON0>; clock-names = "apb", "smi", "gals"; }; smi_larb20: smi-larb20@1460c000 { compatible = "mediatek,smi_larb20", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1460c000 0 0x1000>; mediatek,smi = <&smi_mdp_common &smi_sram_ovl_2x1_subcomm1>; mediatek,larb-id = <20>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS1_SHUTDOWN>; clocks = <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>; clock-names = "apb", "smi", "gals"; }; smi_larb21: smi-larb21@1460d000 { compatible = "mediatek,smi_larb21", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1460d000 0 0x1000>; mediatek,smi = <&smi_dram_disp1_2x1_subcomm1 &smi_sram_ovl_2x1_subcomm1>; mediatek,larb-id = <21>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS1_SHUTDOWN>; clocks = <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>, <&ovlsys1_config_clk CLK_OVL1_SMI_SUB_COMMON0>; clock-names = "apb", "smi", "gals"; }; smi_larb32: smi-larb32@1401d000 { compatible = "mediatek,smi_larb32", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1401d000 0 0x1000>; mediatek,smi = <&smi_dram_disp1_2x1_subcomm0 &smi_sram_disp1_2x1_subcomm0>; mediatek,larb-id = <32>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS0_SHUTDOWN>; clocks = <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>, <&dispsys_config_clk CLK_MM_SMI_SUB_COMM0>; clock-names = "apb", "smi", "gals"; }; smi_larb33: smi-larb33@1421d000 { compatible = "mediatek,smi_larb33", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1421d000 0 0x1000>; mediatek,smi = <&smi_dram_disp1_2x1_subcomm1 &smi_sram_disp1_2x1_subcomm1>; mediatek,larb-id = <33>; emimpu-check; init-power-on; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS1_SHUTDOWN>; clocks = <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>, <&dispsys1_config_clk CLK_MM1_SMI_SUB_COMM0>; clock-names = "apb", "smi", "gals"; }; smi-test { compatible = "mediatek,smi-testcase"; mediatek,larbs = <&smi_larb2>; }; smi_larb2: smi-larb2@1f002000 { compatible = "mediatek,smi_larb2", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1f002000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,larb-id = <2>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MDP0_SHUTDOWN>; clocks = <&mdpsys_config_clk CLK_MDP_SMI0>, <&mdpsys_config_clk CLK_MDP_SMI0>, <&mdpsys_config_clk CLK_MDP_SMI0>; clock-names = "apb", "smi", "gals"; }; smi_larb3: smi-larb3@1f802000 { compatible = "mediatek,smi_larb3", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1f802000 0 0x1000>; mediatek,smi = <&smi_mdp_2x1_subcommon &smi_sysram_common>; mediatek,larb-id = <3>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_MDP1_SHUTDOWN>; clocks = <&mdpsys1_config_clk CLK_MDP1_SMI0>, <&mdpsys1_config_clk CLK_MDP1_SMI0>, <&mdpsys1_config_clk CLK_MDP1_SMI0>; clock-names = "apb", "smi", "gals"; }; smi_larb4: smi-larb4@1602e000 { compatible = "mediatek,smi_larb4", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1602e000 0 0x1000>; mediatek,smi = <&smi_mdp_common>; mediatek,larb-id = <4>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE1>; clocks = <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>, <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>, <&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>; clock-names = "apb", "smi", "gals"; }; smi_larb5: smi-larb5@1600d000 { compatible = "mediatek,smi_larb5", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1600d000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,larb-id = <5>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE0>; clocks = <&vdec_soc_gcon_base_clk CLK_VDE1_LARB1_CKEN>, <&vdec_soc_gcon_base_clk CLK_VDE1_LARB1_CKEN>, <&vdec_soc_gcon_base_clk CLK_VDE1_LARB1_CKEN>; clock-names = "apb", "smi", "gals"; }; vdec_fmt: vdec-fmt@16005000 { compatible = "mediatek-vdec-fmt"; mediatek,fmtname = "vdec-fmt"; reg = <0 0x16005000 0 0x1000>, /* mini_mdp0_rdma */ <0 0x16006000 0 0x1000>, /* mini_mdp0_wdma */ <0 0x16007000 0 0x1000>, /* mini_mdp1_wdma */ <0 0x16008000 0 0x1000>, /* mini_mdp1_wdma */ <0 0x1600f000 0 0x10000>; /* VDEC_SOC_GCON */ clocks = <&vdec_soc_gcon_base_clk CLK_VDE1_VDEC_CKEN>, <&vdec_soc_gcon_base_clk CLK_VDE1_MINI_MDP_EN>, <&mmdvfs_clk CLK_MMDVFS_VFMT>; clock-names = "MT_CG_VDEC","MT_CG_MINI_MDP","mmdvfs_clk"; mediatek,fmt-gce-th-num = <2>; /* FMT GCE HW THREAD NUM */ mboxes = <&gce_m 6 0 CMDQ_THR_PRIO_1>, <&gce_m 7 0 CMDQ_THR_PRIO_1>; /* rdma0_sw_rst_done_eng_event */ rdma0-sw-rst-done-eng = /bits/ 16 ; /* rdma0_tile_done */ rdma0-tile-done = /bits/ 16 ; /* wdma0_sw_rst_done_eng_event */ wdma0-sw-rst-done-eng = /bits/ 16 ; /* wdma0_tile_done */ wdma0-tile-done = /bits/ 16 ; /* rdma1_sw_rst_done_eng_event */ rdma1-sw-rst-done-eng = /bits/ 16 ; /* rdma1_tile_done */ rdma1-tile-done = /bits/ 16 ; /* wdma1_sw_rst_done_eng_event */ wdma1-sw-rst-done-eng = /bits/ 16 ; /* wdma1_tile_done */ wdma1-tile-done = /bits/ 16 ; gce-gpr = ; iommus = <&disp_iommu M4U_PORT_L6_HW_MINI_MDP_R0_EXT>, <&disp_iommu M4U_PORT_L6_HW_MINI_MDP_W0_EXT>, <&disp_iommu M4U_PORT_L6_HW_MINI_MDP_R1_EXT>, <&disp_iommu M4U_PORT_L6_HW_MINI_MDP_W1_EXT>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE0>; mediatek,larbs = <&smi_larb6>; operating-points-v2 = <&opp_table_vdec>; dvfsrc-vcore-supply = <&dvfsrc_vcore>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_R0_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_W0_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_R1_EXT) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L6_HW_MINI_MDP_W1_EXT) &mmqos SLAVE_COMMON(0)>; interconnect-names = "path_mini_mdp_r0", "path_mini_mdp_w0", "path_mini_mdp_r1", "path_mini_mdp_w1"; m4u-ports = , , , ; }; smi_larb6: smi-larb6@16009000 { compatible = "mediatek,smi_larb6", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x16009000 0 0x1000>; mediatek,smi = <&smi_disp_common>; mediatek,larb-id = <6>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE0>; clocks = <&vdec_soc_gcon_base_clk CLK_VDE1_LARB1_CKEN>, <&vdec_soc_gcon_base_clk CLK_VDE1_LARB1_CKEN>, <&vdec_soc_gcon_base_clk CLK_VDE1_LARB1_CKEN>; clock-names = "apb", "smi", "gals"; }; smi_larb7: smi-larb7@17010000 { compatible = "mediatek,smi_larb7", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x17010000 0 0x1000>; mediatek,smi = <&smi_disp_common &smi_sysram_common>; mediatek,larb-id = <7>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN0>; clocks = <&venc_gcon_clk CLK_VEN_CKE0_LARB>, <&venc_gcon_clk CLK_VEN_CKE0_LARB>, <&venc_gcon_clk CLK_VEN_CKE1_VENC>; clock-names = "apb", "smi", "gals"; }; smi_larb8: smi-larb8@17810000 { compatible = "mediatek,smi_larb8", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x17810000 0 0x1000>; mediatek,smi = <&smi_mdp_venc_2x1_subcomm0 &smi_sram_venc_2x1_subcomm1>; mediatek,larb-id = <8>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN1>; clocks = <&venc_gcon_core1_clk CLK_VEN_C1_CKE0_LARB>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE0_LARB>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE1_VENC>; clock-names = "apb", "smi", "gals"; }; smi_larb37: smi-larb37@17c10000 { compatible = "mediatek,smi_larb37", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x17c10000 0 0x1000>; mediatek,smi = <&smi_mdp_venc_2x1_subcomm0 &smi_sram_venc_2x1_subcomm1>; mediatek,larb-id = <37>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN2>; clocks = <&venc_gcon_core2_clk CLK_VEN_C2_CKE0_LARB>, <&venc_gcon_core2_clk CLK_VEN_C2_CKE0_LARB>, <&venc_gcon_core2_clk CLK_VEN_C2_CKE1_VENC>; clock-names = "apb", "smi", "gals"; }; smi_larb9: smi-larb9@15001000 { compatible = "mediatek,smi_larb9", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15001000 0 0x1000>; mediatek,smi = <&smi_mdp_img_5x1_subcomm1>; mediatek,larb-id = <9>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; clocks = <&imgsys_main_clk CLK_IMG_LARB9>, <&imgsys_main_clk CLK_IMG_LARB9>, <&imgsys_main_clk CLK_IMG_LARB9>; clock-names = "apb", "smi", "gals"; }; smi_larb10: smi-larb10@15120000 { compatible = "mediatek,smi_larb10", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15120000 0 0x1000>; mediatek,smi = <&smi_disp_img_4x1_subcomm0>; mediatek,larb-id = <10>; emimpu-check; mediatek,comm-port-id = <1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_DIP1>; clocks = <&dip_top_dip1_clk CLK_DIP_TOP_DIP1_DIP_TOP>, <&dip_top_dip1_clk CLK_DIP_TOP_DIP1_LARB10>, <&dip_top_dip1_clk CLK_DIP_TOP_DIP1_LARB10>; clock-names = "apb", "smi", "gals"; }; smi_larb11: smi-larb11@15230000 { compatible = "mediatek,smi_larb11", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15230000 0 0x1000>; mediatek,smi = <&smi_mdp_img_5x1_subcomm1>; mediatek,larb-id = <11>; emimpu-check; mediatek,comm-port-id = <2>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_DIP1>; clocks = <&wpe1_dip1_clk CLK_WPE1_DIP1_WPE>, <&wpe1_dip1_clk CLK_WPE1_DIP1_LARB11>, <&wpe1_dip1_clk CLK_WPE1_DIP1_LARB11>; clock-names = "apb", "smi", "gals"; }; smi_larb12: smi-larb12@15340000 { compatible = "mediatek,smi_larb12", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15340000 0 0x1000>; mediatek,smi = <&smi_mdp_img_5x1_subcomm1>; mediatek,larb-id = <12>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; clocks = <&imgsys_main_clk CLK_IMG_LARB12>, <&imgsys_main_clk CLK_IMG_LARB12>, <&imgsys_main_clk CLK_IMG_LARB12>; clock-names = "apb", "smi", "gals"; }; smi_larb15: smi-larb15@15140000 { compatible = "mediatek,smi_larb15", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15140000 0 0x1000>; mediatek,smi = <&smi_mdp_img_5x1_subcomm1>; mediatek,larb-id = <15>; emimpu-check; mediatek,comm-port-id = <1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_DIP1>; clocks = <&dip_nr1_dip1_clk CLK_DIP_NR1_DIP1_DIP_NR1>, <&dip_nr2_dip1_clk CLK_DIP_NR2_DIP1_DIP_NR>, <&dip_nr2_dip1_clk CLK_DIP_NR2_DIP1_LARB15>; clock-names = "apb", "smi", "gals"; }; smi_larb18: smi-larb18@15006000 { compatible = "mediatek,smi_larb18", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15006000 0 0x1000>; mediatek,smi = <&smi_mdp_img_5x1_subcomm1>; mediatek,larb-id = <18>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_MAIN>; clocks = <&imgsys_main_clk CLK_IMG_SMI_ADL_LARB0>, <&imgsys_main_clk CLK_IMG_SMI_ADL_LARB0>, <&imgsys_main_clk CLK_IMG_SMI_ADL_LARB0>; clock-names = "apb", "smi", "gals"; }; smi_larb22: smi-larb22@15530000 { compatible = "mediatek,smi_larb22", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15530000 0 0x1000>; mediatek,smi = <&smi_disp_img_4x1_subcomm0>; mediatek,larb-id = <22>; emimpu-check; mediatek,comm-port-id = <2>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_DIP1>; clocks = <&wpe2_dip1_clk CLK_WPE2_DIP1_WPE>, <&wpe2_dip1_clk CLK_WPE2_DIP1_LARB11>, <&wpe2_dip1_clk CLK_WPE2_DIP1_LARB11>; clock-names = "apb", "smi", "gals"; }; smi_larb23: smi-larb23@15630000 { compatible = "mediatek,smi_larb23", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15630000 0 0x1000>; mediatek,smi = <&smi_disp_img_4x1_subcomm0>; mediatek,larb-id = <23>; emimpu-check; mediatek,comm-port-id = <3>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_DIP1>; clocks = <&wpe3_dip1_clk CLK_WPE3_DIP1_WPE>, <&wpe3_dip1_clk CLK_WPE3_DIP1_LARB11>, <&wpe3_dip1_clk CLK_WPE3_DIP1_LARB11>; clock-names = "apb", "smi", "gals"; }; smi_larb28: smi-larb28@15720000 { compatible = "mediatek,smi_larb28", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x15720000 0 0x1000>; mediatek,smi = <&smi_disp_img_4x1_subcomm0>; mediatek,larb-id = <28>; emimpu-check; mediatek,comm-port-id = <0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_ISP_DIP1>; clocks = <&traw_dip1_clk CLK_TRAW_DIP1_TRAW>, <&traw_dip1_clk CLK_TRAW_DIP1_LARB28>, <&traw_dip1_clk CLK_TRAW_DIP1_LARB28>; clock-names = "apb", "smi", "gals"; }; smi_larb13: smi-larb13@1a001000 { compatible = "mediatek,smi_larb13", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a001000 0 0x1000>; mediatek,smi = <&smi_mdp_cam_7x1_subcomm1>; mediatek,larb-id = <13>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>; clock-names = "apb", "smi", "gals"; }; smi_larb14: smi-larb14@1a002000 { compatible = "mediatek,smi_larb14", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a002000 0 0x1000>; mediatek,smi = <&smi_mdp_common>; mediatek,larb-id = <14>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>; clock-names = "apb", "smi", "gals"; }; smi_larb16: smi-larb16@1a026000 { compatible = "mediatek,smi_larb16", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a026000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0>; mediatek,larb-id = <16>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBA>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBA_CON_0>, <&camsys_rawa_clk CLK_CAM_RA_LARBX>, <&camsys_rawa_clk CLK_CAM_RA_LARBX>; clock-names = "apb", "smi", "gals"; }; smi_larb17: smi-larb17@1a027000 { compatible = "mediatek,smi_larb17", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a027000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0 &smi_mdp_cam_7x1_subcomm1>; mediatek,larb-id = <17>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBA>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBA_CON_0>, <&camsys_yuva_clk CLK_CAM_YA_LARBX>, <&camsys_yuva_clk CLK_CAM_YA_LARBX>; clock-names = "apb", "smi", "gals"; }; smi_larb19: smi-larb19@1b201000 { compatible = "mediatek,smi_larb19", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1b201000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0 &smi_sram_cam_2x1_subcomm2>; mediatek,larb-id = <19>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; clocks = <&ccu_main_clk CLK_CCU_LARB19>, <&ccu_main_clk CLK_CCU_LARB19>, <&ccu_main_clk CLK_CCU_LARB19>; clock-names = "apb", "smi", "gals"; }; smi_larb25: smi-larb25@1a02c000 { compatible = "mediatek,smi_larb25", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a02c000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0>; mediatek,larb-id = <25>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; clocks = <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>; clock-names = "apb", "smi", "gals"; }; smi_larb26: smi-larb26@1a02d000 { compatible = "mediatek,smi_larb26", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a02d000 0 0x1000>; mediatek,smi = <&smi_mdp_cam_7x1_subcomm1>; mediatek,larb-id = <26>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; clocks = <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>; clock-names = "apb", "smi", "gals"; }; smi_larb27: smi-larb27@1a003000 { compatible = "mediatek,smi_larb27", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a003000 0 0x1000>; mediatek,smi = <&smi_mdp_cam_7x1_subcomm1 &smi_sram_cam_2x1_subcomm2>; mediatek,larb-id = <27>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB27_CON_0>; clock-names = "apb", "smi", "gals"; }; smi_larb29: smi-larb29@1a004000 { compatible = "mediatek,smi_larb29", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a004000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0>; mediatek,larb-id = <29>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>; clock-names = "apb", "smi", "gals"; }; smi_larb30: smi-larb30@1a028000 { compatible = "mediatek,smi_larb30", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a028000 0 0x1000>; mediatek,smi = <&smi_mdp_cam_7x1_subcomm1>; mediatek,larb-id = <30>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBB>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBB_CON_0>, <&camsys_rawb_clk CLK_CAM_RB_LARBX>, <&camsys_rawb_clk CLK_CAM_RB_LARBX>; clock-names = "apb", "smi", "gals"; }; smi_larb31: smi-larb31@1a02a000 { compatible = "mediatek,smi_larb31", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a02a000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0>; mediatek,larb-id = <31>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBC>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBC_CON_0>, <&camsys_rawc_clk CLK_CAM_RC_CAMTG>, <&camsys_rawc_clk CLK_CAM_RC_LARBX>; clock-names = "apb", "smi", "gals"; }; smi_larb34: smi-larb34@1a029000 { compatible = "mediatek,smi_larb34", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a029000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0>; mediatek,larb-id = <34>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBB>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBB_CON_0>, <&camsys_yuvb_clk CLK_CAM_YB_LARBX>, <&camsys_yuvb_clk CLK_CAM_YB_LARBX>; clock-names = "apb", "smi", "gals"; }; smi_larb35: smi-larb35@1a02b000 { compatible = "mediatek,smi_larb35", "mediatek,mt6985-smi-larb", "mediatek,smi-larb"; reg = <0 0x1a02b000 0 0x1000>; mediatek,smi = <&smi_disp_cam_8x1_subcomm0 &smi_mdp_cam_7x1_subcomm1>; mediatek,larb-id = <35>; emimpu-check; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_SUBC>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_SUBC_CON_0>, <&camsys_rawc_clk CLK_CAM_RC_CAMTG>, <&camsys_yuvc_clk CLK_CAM_YC_LARBX>; clock-names = "apb", "smi", "gals"; }; mm_m0_rsi_regs: smi-mm-m0-rsi-regs@1e807000 { compatible = "mediatek,smi-rsi"; reg = <0 0x1e807000 0 0x1000>; mediatek,rsi-id = <0>; mediatek,dump-with-comm = <0>; }; mm_m1_rsi_regs: smi-mm-m1-rsi-regs@1e808000 { compatible = "mediatek,smi-rsi"; reg = <0 0x1e808000 0 0x1000>; mediatek,rsi-id = <1>; mediatek,dump-with-comm = <0>; }; mdp_m0_rsi_regs: smi-mdp-m0-rsi-regs@1e815000 { compatible = "mediatek,smi-rsi"; reg = <0 0x1e815000 0 0x1000>; mediatek,rsi-id = <2>; mediatek,dump-with-comm = <1>; }; mdp_m1_rsi_regs: smi-mdp-m1-rsi-regs@1e816000 { compatible = "mediatek,smi-rsi"; reg = <0 0x1e816000 0 0x1000>; mediatek,rsi-id = <3>; mediatek,dump-with-comm = <1>; }; mmqos-wrapper { compatible = "mediatek,mt6985-mmqos-wrapper"; }; mmqos: interconnect { compatible = "mediatek,mt6985-mmqos"; #mtk-interconnect-cells = <1>; mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2 &smi_larb3 &smi_larb4 &smi_larb5 &smi_larb6 &smi_larb7 &smi_larb8 &smi_larb9 &smi_larb10 &smi_larb11 &smi_larb12 &smi_larb13 &smi_larb14 &smi_larb15 &smi_larb16 &smi_larb17 &smi_larb18 &smi_larb19 &smi_larb20 &smi_larb21 &smi_larb22 &smi_larb23 &smi_larb25 &smi_larb26 &smi_larb27 &smi_larb28 &smi_larb29 &smi_larb30 &smi_larb31 &smi_larb32 &smi_larb33 &smi_larb34 &smi_larb35 &smi_larb37>; mediatek,commons = <&smi_disp_common>, <&smi_mdp_common>; clocks = <&topckgen_clk CLK_TOP_MMINFRA_SEL>, <&topckgen_clk CLK_TOP_MMINFRA_SEL>; clock-names = "mm", "mdp"; interconnects = <&dvfsrc MT6873_MASTER_MMSYS &dvfsrc MT6873_SLAVE_DDR_EMI>, <&dvfsrc MT6873_MASTER_HRT_MMSYS &dvfsrc MT6873_SLAVE_HRT_DDR_EMI>; interconnect-names = "icc-bw", "icc-hrt-bw"; }; mminfra-debug@0x1e827000 { compatible = "mediatek,mminfra-debug"; reg = <0 0x1e827000 0 0x90>; power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_INFRA>; interrupts = ; mminfra-bkrs = <0>; bkrs-reg = <0x1e800250>; init-clk-on; clocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>, <&mminfra_config_clk CLK_MMINFRA_GCE_M>, <&mminfra_config_clk CLK_MMINFRA_SMI>, <&mminfra_config_clk CLK_MMINFRA_GCE_26M>; clock-names = "clk0", "clk1", "clk2", "clk3"; }; disp_pwm: disp-pwm0@1100e000 { compatible = "mediatek,disp_pwm0", "mediatek,mt6985-disp-pwm0"; reg = <0 0x1100e000 0 0x1000>; interrupts = ; #pwm-cells = <2>; clocks = <&pericfg_ao_clk CLK_PERAO_DISP_PWM0>, <&topckgen_clk CLK_TOP_DISP_PWM_SEL>, <&topckgen_clk CLK_TOP_OSC_D4>; clock-names = "main", "mm", "pwm_src"; }; disp_ovl0_2l: disp-ovl0@14402000 { compatible = "mediatek,disp_ovl0", "mediatek,mt6985-disp-ovl"; reg = <0 0x14402000 0 0x1000>; interrupts = ; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS_SHUTDOWN>; clocks = <&ovlsys_config_clk CLK_OVL_OVL0_2L>; mediatek,larb = <&smi_larb0 M4U_PORT_L0_DISP_OVL0_2L_RDMA0>, <&smi_larb1 M4U_PORT_L1_DISP_OVL0_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL0_2L_RDMA0>, <&disp_iommu M4U_PORT_L0_DISP_OVL0_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL0_2L_qos", "DDP_COMPONENT_OVL0_2L_fbdc_qos", "DDP_COMPONENT_OVL0_2L_hrt_qos"; }; disp_ovl1_2l: disp-ovl1@14403000 { compatible = "mediatek,disp_ovl1", "mediatek,mt6985-disp-ovl"; reg = <0 0x14403000 0 0x1000>; interrupts = ; clocks = <&ovlsys_config_clk CLK_OVL_OVL1_2L>; mediatek,larb = <&smi_larb1 M4U_PORT_L1_DISP_OVL1_2L_RDMA0>, <&smi_larb0 M4U_PORT_L0_DISP_OVL1_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L1_DISP_OVL1_2L_RDMA0>, <&disp_iommu M4U_PORT_L1_DISP_OVL1_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL1_2L_qos", "DDP_COMPONENT_OVL1_2L_fbdc_qos", "DDP_COMPONENT_OVL1_2L_hrt_qos"; }; disp_ovl2_2l: disp-ovl2@14404000 { compatible = "mediatek,disp_ovl2", "mediatek,mt6985-disp-ovl"; reg = <0 0x14404000 0 0x1000>; interrupts = ; clocks = <&ovlsys_config_clk CLK_OVL_OVL2_2L>; mediatek,larb = <&smi_larb0 M4U_PORT_L0_DISP_OVL2_2L_RDMA0>, <&smi_larb1 M4U_PORT_L1_DISP_OVL2_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L0_DISP_OVL2_2L_RDMA0>, <&disp_iommu M4U_PORT_L0_DISP_OVL2_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL2_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL2_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL2_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL2_2L_qos", "DDP_COMPONENT_OVL2_2L_fbdc_qos", "DDP_COMPONENT_OVL2_2L_hrt_qos"; }; disp_ovl3_2l: disp-ovl3@14405000 { compatible = "mediatek,disp_ovl3", "mediatek,mt6985-disp-ovl"; reg = <0 0x14405000 0 0x1000>; interrupts = ; clocks = <&ovlsys_config_clk CLK_OVL_OVL3_2L>; mediatek,larb = <&smi_larb1 M4U_PORT_L1_DISP_OVL3_2L_RDMA0>, <&smi_larb0 M4U_PORT_L0_DISP_OVL3_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L1_DISP_OVL3_2L_RDMA0>, <&disp_iommu M4U_PORT_L1_DISP_OVL3_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL3_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL3_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL3_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL3_2L_qos", "DDP_COMPONENT_OVL3_2L_fbdc_qos", "DDP_COMPONENT_OVL3_2L_hrt_qos"; }; disp1_ovl0_2l: disp1-ovl0@14602000 { compatible = "mediatek,disp1_ovl0", "mediatek,mt6985-disp-ovl"; reg = <0 0x14602000 0 0x1000>; interrupts = ; power-domains = <&scpsys MT6985_POWER_DOMAIN_OVLSYS1_SHUTDOWN>; clocks = <&ovlsys1_config_clk CLK_OVL1_OVL0_2L>; mediatek,larb = <&smi_larb20 M4U_PORT_L20_DISP_OVL0_2L_RDMA0>, <&smi_larb21 M4U_PORT_L21_DISP_OVL0_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L20_DISP_OVL0_2L_RDMA0>, <&disp_iommu M4U_PORT_L20_DISP_OVL0_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL4_2L_qos", "DDP_COMPONENT_OVL4_2L_fbdc_qos", "DDP_COMPONENT_OVL4_2L_hrt_qos"; }; disp1_ovl1_2l: disp1-ovl1@14603000 { compatible = "mediatek,disp1_ovl1", "mediatek,mt6985-disp-ovl"; reg = <0 0x14603000 0 0x1000>; interrupts = ; clocks = <&ovlsys1_config_clk CLK_OVL1_OVL1_2L>; mediatek,larb = <&smi_larb21 M4U_PORT_L21_DISP_OVL1_2L_RDMA0>, <&smi_larb20 M4U_PORT_L20_DISP_OVL1_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L21_DISP_OVL1_2L_RDMA0>, <&disp_iommu M4U_PORT_L21_DISP_OVL1_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL1_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL1_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL1_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL5_2L_qos", "DDP_COMPONENT_OVL5_2L_fbdc_qos", "DDP_COMPONENT_OVL5_2L_hrt_qos"; }; disp1_ovl2_2l: disp1-ovl2@14604000 { compatible = "mediatek,disp1_ovl2", "mediatek,mt6985-disp-ovl"; reg = <0 0x14604000 0 0x1000>; interrupts = ; clocks = <&ovlsys1_config_clk CLK_OVL1_OVL2_2L>; mediatek,larb = <&smi_larb20 M4U_PORT_L20_DISP_OVL2_2L_RDMA0>, <&smi_larb21 M4U_PORT_L21_DISP_OVL2_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L20_DISP_OVL2_2L_RDMA0>, <&disp_iommu M4U_PORT_L20_DISP_OVL2_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL2_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL2_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL2_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL6_2L_qos", "DDP_COMPONENT_OVL6_2L_fbdc_qos", "DDP_COMPONENT_OVL6_2L_hrt_qos"; }; disp1_ovl3_2l: disp1-ovl3@14605000 { compatible = "mediatek,disp1_ovl3", "mediatek,mt6985-disp-ovl"; reg = <0 0x14605000 0 0x1000>; interrupts = ; clocks = <&ovlsys1_config_clk CLK_OVL1_OVL3_2L>; mediatek,larb = <&smi_larb21 M4U_PORT_L21_DISP_OVL3_2L_RDMA0>, <&smi_larb20 M4U_PORT_L20_DISP_OVL3_2L_RDMA1>; iommus = <&disp_iommu M4U_PORT_L21_DISP_OVL3_2L_RDMA0>, <&disp_iommu M4U_PORT_L21_DISP_OVL3_2L_HDR>; iommus-ovl = ; /* for dujac workaround */ interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL3_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL3_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL3_2L_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_OVL7_2L_qos", "DDP_COMPONENT_OVL7_2L_fbdc_qos", "DDP_COMPONENT_OVL7_2L_hrt_qos"; }; disp_rsz0: disp-rsz0@14016000 { compatible = "mediatek,disp_rsz0", "mediatek,mt6985-disp-rsz"; reg = <0 0x14016000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_RSZ0>; }; disp1_rsz0: disp1-rsz0@14216000 { compatible = "mediatek,disp1_rsz0", "mediatek,mt6985-disp-rsz"; reg = <0 0x14216000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_RSZ0>; }; disp_rsz1: disp-rsz1@14406000 { compatible = "mediatek,disp_rsz1", "mediatek,mt6985-disp-rsz"; reg = <0 0x14406000 0 0x1000>; interrupts = ; clocks = <&ovlsys_config_clk CLK_OVL_DISP_RSZ1>; }; disp1_rsz1: disp1-rsz1@14606000 { compatible = "mediatek,disp1_rsz1", "mediatek,mt6985-disp-rsz"; reg = <0 0x14606000 0 0x1000>; interrupts = ; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_RSZ1>; }; mdp_rsz6: mdp-rsz6@14407000 { compatible = "mediatek,mdp_rsz", "mediatek,mt6985-disp-mdp-rsz"; reg = <0 0x14407000 0 0x1000>; clocks = <&ovlsys_config_clk CLK_OVL_MDP_RSZ0>; }; mdp_rsz7: mdp-rsz7@14607000 { compatible = "mediatek,mdp_rsz", "mediatek,mt6985-disp-mdp-rsz"; reg = <0 0x14607000 0 0x1000>; clocks = <&ovlsys1_config_clk CLK_OVL1_MDP_RSZ0>; }; inlinerot0: inlinerot@1440b000 { compatible = "mediatek,inlinerot", "mediatek,mt6985-disp-inlinerotate"; clocks = <&ovlsys_config_clk CLK_OVL_INLINEROT>; reg = <0 0x1440b000 0 0x1000>; }; inlinerot1: inlinerot@1460b000 { compatible = "mediatek,inlinerot", "mediatek,mt6985-disp-inlinerotate"; clocks = <&ovlsys1_config_clk CLK_OVL1_INLINEROT>; reg = <0 0x1460b000 0 0x1000>; }; ovl_dli_async0: ovl-dli-async0@14400000 { compatible = "mediatek,ovl_dli_async0", "mediatek,mt6985-disp-dli-async"; reg = <0 0x14400000 0 0x1000>; clocks = <&ovlsys_config_clk CLK_OVL_DISP_DLI_ASYNC0>; }; ovl1_dli_async0: ovl1-dli-async0@14600000 { compatible = "mediatek,ovl1_dli_async0", "mediatek,mt6985-disp-dli-async"; reg = <0 0x14600000 0 0x1000>; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_DLI_ASYNC0>; }; ovl_dlo_async0: ovl-dlo-async0@14400000 { compatible = "mediatek,ovl_dlo_async0", "mediatek,mt6985-disp-dlo-async"; reg = <0 0x14400000 0 0x1000>; clocks = <&ovlsys_config_clk CLK_OVL_DISP_DLO_ASYNC0>; }; ovl1_dlo_async0: ovl1-dlo-async0@14600000 { compatible = "mediatek,ovl1_dlo_async0", "mediatek,mt6985-disp-dlo-async"; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_DLO_ASYNC0>; reg = <0 0x14600000 0 0x1000>; }; disp_y2r0: disp-y2r0@14000000 { compatible = "mediatek,disp_y2r0", "mediatek,mt6985-disp-y2r"; reg = <0 0x14000000 0 0x1000>; clocks = <&dispsys_config_clk CLK_MM_DISP_Y2R0>; }; disp1_y2r0: disp1-y2r0@14200000 { compatible = "mediatek,disp1_y2r0", "mediatek,mt6985-disp-y2r"; reg = <0 0x14200000 0 0x1000>; clocks = <&dispsys1_config_clk CLK_MM1_DISP_Y2R0>; }; ovl_y2r0: ovl-y2r0@14400000 { compatible = "mediatek,ovl_y2r0", "mediatek,mt6985-disp-y2r"; reg = <0 0x14400000 0 0x1000>; clocks = <&ovlsys_config_clk CLK_OVL_DISP_Y2R0>; }; ovl_y2r1: ovl-y2r1@14400000 { compatible = "mediatek,ovl_y2r1", "mediatek,mt6985-disp-y2r"; reg = <0 0x14400000 0 0x1000>; clocks = <&ovlsys_config_clk CLK_OVL_DISP_Y2R1>; }; ovl1_y2r0: ovl1-y2r0@14600000 { compatible = "mediatek,ovl1_y2r0", "mediatek,mt6985-disp-y2r"; reg = <0 0x14600000 0 0x1000>; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_Y2R0>; }; ovl1_y2r1: ovl1-y2r1@14600000 { compatible = "mediatek,ovl1_y2r1", "mediatek,mt6985-disp-y2r"; reg = <0 0x14600000 0 0x1000>; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_Y2R1>; }; disp_wdma0: disp-wdma0@14408000 { compatible = "mediatek,disp_wdma0", "mediatek,mt6985-disp-wdma"; reg = <0 0x14408000 0 0x1000>; interrupts = ; clocks = <&ovlsys_config_clk CLK_OVL_DISP_WDMA0>; fifo-size-1plane = <679>; fifo-size-2plane = <448>; fifo-size-uv-2plane = <224>; fifo-size-3plane = <445>; fifo-size-uv-3plane = <110>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_WDMA0>; }; disp_wdma1: disp-wdma1@1401c000 { compatible = "mediatek,disp_wdma1", "mediatek,mt6985-disp-wdma"; reg = <0 0x1401c000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_WDMA1>; fifo-size-1plane = <906>; fifo-size-2plane = <599>; fifo-size-uv-2plane = <229>; fifo-size-3plane = <596>; fifo-size-uv-3plane = <148>; mediatek,larb = <&smi_larb32>; mediatek,smi-id = <32>; iommus = <&disp_iommu M4U_PORT_L32_DISP_WDMA1>; }; disp_wdma2: disp-wdma2@1440a000 { compatible = "mediatek,disp_wdma2", "mediatek,mt6985-disp-wdma"; reg = <0 0x1440a000 0 0x1000>; interrupts = ; clocks = <&ovlsys_config_clk CLK_OVL_DISP_WDMA2>; fifo-size-1plane = <109>; fifo-size-2plane = <0>; fifo-size-uv-2plane = <0>; fifo-size-3plane = <0>; fifo-size-uv-3plane = <0>; mediatek,larb = <&smi_larb1>; mediatek,smi-id = <1>; iommus = <&disp_iommu M4U_PORT_L1_DISP_WDMA2>; }; disp1_wdma0: disp1-wdma0@14608000 { compatible = "mediatek,disp1_wdma0", "mediatek,mt6985-disp-wdma"; reg = <0 0x14608000 0 0x1000>; interrupts = ; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_WDMA0>; fifo-size-1plane = <679>; fifo-size-2plane = <448>; fifo-size-uv-2plane = <224>; fifo-size-3plane = <445>; fifo-size-uv-3plane = <110>; mediatek,larb = <&smi_larb20>; mediatek,smi-id = <20>; iommus = <&disp_iommu M4U_PORT_L20_DISP_WDMA0>; }; disp1_wdma1: disp1-wdma1@1421c000 { compatible = "mediatek,disp1_wdma1", "mediatek,mt6985-disp-wdma"; reg = <0 0x1421c000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_WDMA1>; fifo-size-1plane = <906>; fifo-size-2plane = <599>; fifo-size-uv-2plane = <229>; fifo-size-3plane = <596>; fifo-size-uv-3plane = <148>; mediatek,larb = <&smi_larb33>; mediatek,smi-id = <33>; iommus = <&disp_iommu M4U_PORT_L33_DISP_WDMA1>; }; disp1_wdma2: disp1-wdma2@1460a000 { compatible = "mediatek,disp1_wdma2", "mediatek,mt6985-disp-wdma"; reg = <0 0x1460a000 0 0x1000>; interrupts = ; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_WDMA2>; fifo-size-1plane = <109>; fifo-size-2plane = <0>; fifo-size-uv-2plane = <0>; fifo-size-3plane = <0>; fifo-size-uv-3plane = <0>; mediatek,larb = <&smi_larb21>; mediatek,smi-id = <21>; iommus = <&disp_iommu M4U_PORT_L21_DISP_WDMA2>; }; disp_ufbc_wdma0: disp-ufbc-wdma0@1401a000 { status = "disabled"; compatible = "mediatek,disp_ufbc_wdma0", "mediatek,mt6985-disp-wdma"; reg = <0 0x1401a000 0 0x1000>; interrupts = ; clocks = <&ovlsys_config_clk CLK_OVL_DISP_UFBC_WDMA0>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; iommus = <&disp_iommu M4U_PORT_L0_DISP_UFBC_WDMA0>; }; disp_ufbc_wdma1: disp-ufbc-wdma1@14409000 { status = "disabled"; compatible = "mediatek,disp_ufbc_wdma1", "mediatek,mt6985-disp-wdma"; reg = <0 0x14409000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_UFBC_WDMA1>; mediatek,larb = <&smi_larb32>; mediatek,smi-id = <32>; iommus = <&disp_iommu M4U_PORT_L32_DISP_WDMA1>; }; disp1_ufbc_wdma0: disp1-ufbc-wdma0@1421a000 { status = "disabled"; compatible = "mediatek,disp1_ufbc_wdma0", "mediatek,mt6985-disp-wdma"; reg = <0 0x1421a000 0 0x1000>; interrupts = ; clocks = <&ovlsys1_config_clk CLK_OVL1_DISP_UFBC_WDMA0>; mediatek,larb = <&smi_larb20>; mediatek,smi-id = <20>; iommus = <&disp_iommu M4U_PORT_L20_DISP_WDMA0>; }; disp1_ufbc_wdma1: disp1-ufbc-wdma1@14609000 { status = "disabled"; compatible = "mediatek,disp1_ufbc_wdma1", "mediatek,mt6985-disp-wdma"; reg = <0 0x14609000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_UFBC_WDMA1>; mediatek,larb = <&smi_larb33>; mediatek,smi-id = <33>; iommus = <&disp_iommu M4U_PORT_L33_DISP_WDMA1>; }; disp_mdp_rdma0: disp-mdp-rdma0@14010000 { compatible = "mediatek,disp_mdp_rdma0", "mediatek,mt6985-disp-mdp-rdma"; reg = <0 0x14010000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_MDP_RDMA0>; mediatek,larb = <&smi_larb32 M4U_PORT_L32_DISP_MDP_RDMA0>; iommus = <&disp_iommu M4U_PORT_L32_DISP_MDP_RDMA0>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L32_DISP_MDP_RDMA0) &mmqos SLAVE_COMMON(1)>; interconnect-names = "DDP_COMPONENT_MDP_RDMA0_hrt_qos"; }; disp1_mdp_rdma0: disp1-mdp-rdma0@14210000 { compatible = "mediatek,disp1_mdp_rdma0", "mediatek,mt6985-disp-mdp-rdma"; reg = <0 0x14210000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_MDP_RDMA0>; mediatek,larb = <&smi_larb33 M4U_PORT_L33_DISP_MDP_RDMA0>; iommus = <&disp_iommu M4U_PORT_L33_DISP_MDP_RDMA0>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L33_DISP_MDP_RDMA0) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_MDP_RDMA1_hrt_qos"; }; disp_tdshp0_0: disp_tdshp@14018000 { compatible = "mediatek,disp_tdshp0", "mediatek,mt6985-disp-tdshp"; reg = <0 0x14018000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_TDSHP0>; mtk-tdshp-clarity-support = <1>; }; disp_tdshp0_1: disp_tdshp@14019000 { compatible = "mediatek,disp_tdshp1", "mediatek,mt6985-disp-tdshp"; reg = <0 0x14019000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_TDSHP1>; }; disp_tdshp1_0: disp_tdshp@14218000 { compatible = "mediatek,disp_tdshp2", "mediatek,mt6985-disp-tdshp"; reg = <0 0x14218000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_TDSHP0>; }; disp_tdshp1_1: disp_tdshp@14219000 { compatible = "mediatek,disp_tdshp3", "mediatek,mt6985-disp-tdshp"; reg = <0 0x14219000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_TDSHP1>; }; disp_color0: disp_color@14008000 { compatible = "mediatek,disp_color0", "mediatek,mt6985-disp-color"; reg = <0 0x14008000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_COLOR0>; }; disp_color1: disp_color@14208000 { compatible = "mediatek,disp_color1", "mediatek,mt6985-disp-color"; reg = <0 0x14208000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_COLOR0>; }; disp_ccorr0_0: disp_ccorr@14004000 { compatible = "mediatek,disp_ccorr0", "mediatek,mt6985-disp-ccorr"; reg = <0 0x14004000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_CCORR0>; ccorr_bit = <13>; ccorr_num_per_pipe = <2>; ccorr_linear_per_pipe = <0x10>; }; disp_ccorr0_1: disp_ccorr@14005000 { compatible = "mediatek,disp_ccorr1", "mediatek,mt6985-disp-ccorr"; reg = <0 0x14005000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_CCORR1>; }; disp_c3d0: disp_c3d@14003000 { compatible = "mediatek,disp_c3d0", "mediatek,mt6985-disp-c3d"; reg = <0 0x14003000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_C3D0>; }; disp_c3d1: disp_c3d@14203000 { compatible = "mediatek,disp_c3d1", "mediatek,mt6985-disp-c3d"; reg = <0 0x14203000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_C3D0>; }; disp_ccorr1_0: disp_ccorr@14204000 { compatible = "mediatek,disp_ccorr2", "mediatek,mt6985-disp-ccorr"; reg = <0 0x14204000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_CCORR0>; }; disp_ccorr1_1: disp_ccorr@14205000 { compatible = "mediatek,disp_ccorr3", "mediatek,mt6985-disp-ccorr"; reg = <0 0x14205000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_CCORR1>; }; disp_mdp_aal0: disp_mdp_aal@1400f000 { compatible = "mediatek,disp_mdp_aal0", "mediatek,mt6985-dmdp-aal"; reg = <0 0x1400f000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_MDP_AAL0>; clock-names = "DRE3_AAL0"; }; disp_mdp_aal1: disp_mdp_aal@1420f000 { compatible = "mediatek,disp_mdp_aal1", "mediatek,mt6985-dmdp-aal"; reg = <0 0x1420f000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_MDP_AAL0>; clock-names = "DRE3_AAL1"; }; disp_aal0: disp_aal@14002000 { compatible = "mediatek,disp_aal0", "mediatek,mt6985-disp-aal"; reg = <0 0x14002000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_AAL0>; aal_dre3 = <&disp_mdp_aal0>; mtk_aal_support = <1>; mtk_dre30_support = <1>; mtk-aal-clarity-support = <1>; }; disp_aal1: disp_aal@14202000 { compatible = "mediatek,disp_aal1", "mediatek,mt6985-disp-aal"; reg = <0 0x14202000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_AAL0>; aal_dre3 = <&disp_mdp_aal1>; }; disp_gamma0: disp_gamma@1400e000 { compatible = "mediatek,disp_gamma0", "mediatek,mt6985-disp-gamma"; reg = <0 0x1400e000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_GAMMA0>; gamma_data_mode = <2>; color_protect_red = <0>; color_protect_green = <0>; color_protect_blue = <0>; color_protect_white = <0>; color_protect_black = <0>; color_protect_lsb = <0>; }; disp_gamma1: disp_gamma@1420e000 { compatible = "mediatek,disp_gamma1", "mediatek,mt6985-disp-gamma"; reg = <0 0x1420e000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_GAMMA0>; }; disp_dither0_0: disp_dither@14009000 { compatible = "mediatek,disp_dither0", "mediatek,mt6985-disp-dither"; reg = <0 0x14009000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_DITHER0>; pure_clr_det = <0>; pure_clr_num = <7>; pure_clr_rgb = <255 0 0 0 255 0 0 0 255 255 255 0 255 0 255 0 255 255 255 255 255>; }; disp_dither0_1: disp_dither@1400a000 { compatible = "mediatek,disp_dither1", "mediatek,mt6985-disp-dither"; reg = <0 0x1400a000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_DITHER1>; }; disp_dither1_0: disp_dither@14209000 { compatible = "mediatek,disp_dither2", "mediatek,mt6985-disp-dither"; reg = <0 0x14209000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_DITHER0>; }; disp_dither1_1: disp_dither@1420a000 { compatible = "mediatek,disp_dither3", "mediatek,mt6985-disp-dither"; reg = <0 0x1420a000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_DITHER1>; }; disp_spr0: disp_spr@14017000 { compatible = "mediatek,disp_spr0", "mediatek,mt6985-disp-spr"; reg = <0 0x14017000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_SPR0>; }; disp1_spr0: disp1_spr0@14217000 { compatible = "mediatek,disp1_spr0", "mediatek,mt6985-disp-spr"; reg = <0 0x14217000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_SPR0>; }; disp_postalign0: disp_postalign0 { compatible = "mediatek,disp_postalign0", "mediatek,mt6985-disp-postalign"; clocks = <&dispsys_config_clk CLK_MM_DISP_POSTALIGN0>; }; disp1_postalign0: disp1_postalign0 { compatible = "mediatek,disp1_postalign0", "mediatek,mt6985-disp-postalign"; clocks = <&dispsys1_config_clk CLK_MM1_DISP_POSTALIGN0>; }; disp_postmask0: disp-postmask0@14015000 { compatible = "mediatek,disp_postmask0", "mediatek,mt6985-disp-postmask"; reg = <0 0x14015000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_POSTMASK0>; mediatek,larb = <&smi_larb32>; mediatek,smi-id = <32>; iommus = <&disp_iommu M4U_PORT_L32_DISP_POSTMASK0>; }; disp1_postmask0: disp1-postmask0@14215000 { compatible = "mediatek,disp1_postmask0", "mediatek,mt6985-disp-postmask"; reg = <0 0x14215000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_POSTMASK0>; mediatek,larb = <&smi_larb33>; mediatek,smi-id = <33>; iommus = <&disp_iommu M4U_PORT_L33_DISP_POSTMASK0>; }; disp_chist0: disp_chist0@14006000 { compatible = "mediatek,disp_chist0", "mediatek,mt6985-disp-chist"; reg = <0 0x14006000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_CHIST0>; }; disp_chist1: disp_chist1@14007000 { compatible = "mediatek,disp_chist1", "mediatek,mt6985-disp-chist"; reg = <0 0x14007000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_CHIST1>; }; disp1_chist0: disp1_chist0@14206000 { compatible = "mediatek,disp1_chist0", "mediatek,mt6985-disp-chist"; reg = <0 0x14206000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_CHIST0>; }; disp1_chist1: disp1_chist1@14207000 { compatible = "mediatek,disp1_chist1", "mediatek,mt6985-disp-chist"; reg = <0 0x14207000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_CHIST1>; }; disp_dsc_wrap0: disp-dsc-wrap0@1400c000 { compatible = "mediatek,disp_dsc_wrap0", "mediatek,mt6985-disp-dsc"; reg = <0 0x1400c000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_DSC_WRAP0>; }; disp1_dsc_wrap0: disp1-dsc-wrap0@1420c000 { compatible = "mediatek,disp1_dsc_wrap0", "mediatek,mt6985-disp-dsc"; reg = <0 0x1420c000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_DSC_WRAP0>; }; disp_oddmr0: disp-oddmr0@14013000 { compatible = "mediatek,disp_oddmr0", "mediatek,mt6985-disp-oddmr"; reg = <0 0x14013000 0 0x2000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_ODDMR0>; mediatek,larb = <&smi_larb32>; mediatek,smi-id = <32>; iommus = <&disp_iommu M4U_PORT_L32_DISP_ODDMR0_DMRR>, <&disp_iommu M4U_PORT_L32_DISP_ODDMR0_ODR>, <&disp_iommu M4U_PORT_L32_DISP_ODDMR0_ODW>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_DMRR) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_ODR) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_ODW) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_DMRR) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_ODR) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L32_DISP_ODDMR0_ODW) &mmqos SLAVE_COMMON(1)>; interconnect-names = "DDP_COMPONENT_ODDMR0_DMRR", "DDP_COMPONENT_ODDMR0_ODR", "DDP_COMPONENT_ODDMR0_ODW", "DDP_COMPONENT_ODDMR0_DMRR_HRT", "DDP_COMPONENT_ODDMR0_ODR_HRT", "DDP_COMPONENT_ODDMR0_ODW_HRT"; }; disp1_oddmr0: disp1-oddmr0@14213000 { compatible = "mediatek,disp1_oddmr0", "mediatek,mt6985-disp-oddmr"; reg = <0 0x14213000 0 0x2000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_ODDMR0>; mediatek,larb = <&smi_larb33>; mediatek,smi-id = <33>; iommus = <&disp_iommu M4U_PORT_L33_DISP_ODDMR0_DMRR>, <&disp_iommu M4U_PORT_L33_DISP_ODDMR0_ODR>, <&disp_iommu M4U_PORT_L33_DISP_ODDMR0_ODW>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_DMRR) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_ODR) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_ODW) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_DMRR) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_ODR) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L33_DISP_ODDMR0_ODW) &mmqos SLAVE_COMMON(0)>; interconnect-names = "DDP_COMPONENT_ODDMR1_DMRR", "DDP_COMPONENT_ODDMR1_ODR", "DDP_COMPONENT_ODDMR1_ODW", "DDP_COMPONENT_ODDMR1_DMRR_HRT", "DDP_COMPONENT_ODDMR1_ODR_HRT", "DDP_COMPONENT_ODDMR1_ODW_HRT"; }; disp_vdcm0: disp-vdcm0@1401b000 { compatible = "mediatek,disp_vdcm0", "mediatek,mt6985-disp-vdcm"; reg = <0 0x1401b000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_VDCM0>; }; disp1_vdcm0: disp1-vdcm0@1421b000 { compatible = "mediatek,disp1_vdcm0", "mediatek,mt6985-disp-vdcm"; reg = <0 0x1421b000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_VDCM0>; }; disp_merge0: disp-merge0@14011000 { compatible = "mediatek,disp_merge0", "mediatek,mt6985-disp-merge"; reg = <0 0x14011000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_MERGE0>; }; disp_merge1: disp-merge1@14012000 { compatible = "mediatek,disp_merge1", "mediatek,mt6985-disp-merge"; reg = <0 0x14012000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_MERGE1>; }; disp1_merge0: disp1-merge0@14211000 { compatible = "mediatek,disp1_merge0", "mediatek,mt6985-disp-merge"; reg = <0 0x14211000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_MERGE0>; }; disp1_merge1: disp1-merge1@14212000 { compatible = "mediatek,disp1_merge1", "mediatek,mt6985-disp-merge"; reg = <0 0x14212000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_MERGE1>; }; mipi_tx_config0: mipi-tx-config@11e50000 { compatible = "mediatek,mipi_tx_config0", "mediatek,mt6985-mipi-tx"; reg = <0 0x11e50000 0 0x1000>; clocks = <&clk26m>; #clock-cells = <0>; #phy-cells = <0>; clock-output-names = "mipi_tx0_pll"; }; mipi_tx_config1: mipi-tx-config@11e60000 { status = "disabled"; compatible = "mediatek,mipi_tx_config1", "mediatek,mt6985-mipi-tx"; reg = <0 0x11e60000 0 0x1000>; clocks = <&clk26m>; #clock-cells = <0>; #phy-cells = <0>; clock-output-names = "mipi_tx1_pll"; }; touch_panel0: touch_panel@0 { compatible = "mediatek,touch-panel"; }; gateic0: gateic@0 { compatible = "mediatek,mtk-drm-gateic-drv"; }; dsi0: dsi0@1400d000 { compatible = "mediatek,dsi0", "mediatek,mt6985-dsi"; reg = <0 0x1400d000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_DSI0>, <&dispsys_config_clk CLK_MM_DSI_CLK>, <&mipi_tx_config0>; clock-names = "engine", "digital", "hs"; phys = <&mipi_tx_config0>; phy-names = "dphy"; }; dsi1: dsi1@1420d000 { status = "disabled"; compatible = "mediatek,dsi1", "mediatek,mt6985-dsi"; reg = <0 0x1420d000 0 0x1000>; interrupts = ; clocks = <&dispsys1_config_clk CLK_MM1_DISP_DSI0>, <&dispsys1_config_clk CLK_MM1_DSI_CLK>, <&mipi_tx_config1>; clock-names = "engine", "digital", "hs"; phys = <&mipi_tx_config1>; phy-names = "dphy"; }; dp_intf: disp-dp-intf0@1400b000 { compatible = "mediatek,dp_intf", "mediatek,mt6985-dp-intf"; reg = <0 0x1400b000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk CLK_MM_DISP_DP_INTF0>, <&dispsys_config_clk CLK_MM_DP_CLK>, <&topckgen_clk CLK_TOP_DP_SEL>, <&topckgen_clk CLK_TOP_TVDPLL_D2>, <&topckgen_clk CLK_TOP_TVDPLL_D4>, <&topckgen_clk CLK_TOP_TVDPLL_D8>, <&topckgen_clk CLK_TOP_TVDPLL_D16>, <&topckgen_clk CLK_TOP_TVDPLL>; clock-names = "hf_fmm_ck", "hf_fdp_ck", "MUX_DP", "TVDPLL_D2", "TVDPLL_D4", "TVDPLL_D8", "TVDPLL_D16", "DPI_CK"; phys = <&dp_tx>; phy-names = "dp_tx"; }; dp_tx: dp-tx@14800000 { compatible = "mediatek,mt6985-dp_tx", "mediatek,dp_tx"; reg = <0 0x14800000 0 0x5000>; mediatek,vs-voter = <&pmic 0x149a 0x20 1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_DP_TX>; interrupts = ; #phy-cells = <0>; dptx,phy_params = <0x221c1814 0x24241e18 0x0000302a 0x0e080400 0x000c0600 0x00000006>; }; disp_mutex0: disp-mutex0@14001000 { compatible = "mediatek,disp_mutex0", "mediatek,mt6985-disp-mutex"; power-domains = <&scpsys MT6985_POWER_DOMAIN_DIS1_SHUTDOWN>; mediatek,mml = <&mmlsys_config>; dispsys_num = <2>; ovlsys_num = <2>; reg = <0 0x14001000 0 0x1000>, <0 0x14201000 0 0x1000>, <0 0x14401000 0 0x1000>, <0 0x14601000 0 0x1000>; interrupts = , ; clocks = <&dispsys_config_clk CLK_MM_DISP_MUTEX0>, <&dispsys1_config_clk CLK_MM1_DISP_MUTEX0>, <&dispsys_config_clk CLK_OVL_DISP_MUTEX0>, <&dispsys1_config_clk CLK_OVL1_DISP_MUTEX0>; }; opp_table_disp: opp-table-disp { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <229000000>; opp-microvolt = <575000>; }; opp-1 { opp-hz = /bits/ 64 <364000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <458000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <725000>; }; opp-4 { opp-hz = /bits/ 64 <728000000>; opp-microvolt = <825000>; }; }; opp_table_mdp: opp-table-mdp { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <250000000>; opp-microvolt = <575000>; }; opp-1 { opp-hz = /bits/ 64 <364000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <458000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <725000>; }; opp-4 { opp-hz = /bits/ 64 <728000000>; opp-microvolt = <825000>; }; }; opp_table_mminfra: opp-table-mminfra { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <218000000>; opp-microvolt = <575000>; }; opp-1 { opp-hz = /bits/ 64 <343000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <458000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <725000>; }; opp-4 { opp-hz = /bits/ 64 <728000000>; opp-microvolt = <825000>; }; }; opp_table_venc: opp-table-venc { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <250000000>; opp-microvolt = <575000>; }; opp-1 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <600000>; }; opp-2 { opp-hz = /bits/ 64 <458000000>; opp-microvolt = <650000>; }; opp-3 { opp-hz = /bits/ 64 <624000000>; opp-microvolt = <725000>; }; opp-4 { opp-hz = /bits/ 64 <688000000>; opp-microvolt = <825000>; }; }; opp_table_vdec: opp-table-vdec { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <000000000>; opp-microvolt = <000000>; }; opp-1 { opp-hz = /bits/ 64 <182000000>; opp-microvolt = <550000>; }; opp-2 { opp-hz = /bits/ 64 <218000000>; opp-microvolt = <575000>; }; opp-3 { opp-hz = /bits/ 64 <249000000>; opp-microvolt = <600000>; }; opp-4 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <650000>; }; opp-5 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <700000>; }; opp-6 { opp-hz = /bits/ 64 <880000000>; opp-microvolt = <850000>; }; }; opp_table_cam: opp-table-cam { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <000000000>; opp-microvolt = <000000>; }; opp-1 { opp-hz = /bits/ 64 <273000000>; opp-microvolt = <550000>; }; opp-2 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <575000>; }; opp-3 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <600000>; }; opp-4 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <650000>; }; opp-5 { opp-hz = /bits/ 64 <688000000>; opp-microvolt = <700000>; }; opp-6 { opp-hz = /bits/ 64 <688000001>; opp-microvolt = <850000>; }; }; opp_table_img: opp-table-img { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <000000000>; opp-microvolt = <000000>; }; opp-1 { opp-hz = /bits/ 64 <264000000>; opp-microvolt = <550000>; }; opp-2 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <575000>; }; opp-3 { opp-hz = /bits/ 64 <416000000>; opp-microvolt = <600000>; }; opp-4 { opp-hz = /bits/ 64 <546000000>; opp-microvolt = <650000>; }; opp-5 { opp-hz = /bits/ 64 <660000000>; opp-microvolt = <700000>; }; opp-6 { opp-hz = /bits/ 64 <660000001>; opp-microvolt = <850000>; }; }; opp_table_vote: opp-table-vote { compatible = "operating-points-v2"; opp-0 { opp-hz = /bits/ 64 <1>; opp-microvolt = <1>; }; opp-1 { opp-hz = /bits/ 64 <2>; opp-microvolt = <2>; }; opp-2 { opp-hz = /bits/ 64 <3>; opp-microvolt = <3>; }; opp-3 { opp-hz = /bits/ 64 <4>; opp-microvolt = <4>; }; opp-4 { opp-hz = /bits/ 64 <5>; opp-microvolt = <5>; }; opp-5 { opp-hz = /bits/ 64 <6>; opp-microvolt = <6>; }; opp-6 { opp-hz = /bits/ 64 <7>; opp-microvolt = <7>; }; }; disp-sec { compatible = "mediatek,disp-sec"; sw-sync-token-tzmp-disp-wait = ; sw-sync-token-tzmp-disp-set = ; mboxes = <&gce_sec 8 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_4>; }; mmdvfs_clk: mmdvfs-clk { compatible = "mediatek,mtk-mmdvfs-v3"; mmdvfs-free-run; #mmdvfs,clock-cells = <6>; mediatek,mmdvfs-clocks = <&mmdvfs_clk CLK_MMDVFS_DISP PWR_MMDVFS_VCORE 1 IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_disp>, <&mmdvfs_clk CLK_MMDVFS_MDP PWR_MMDVFS_VCORE 2 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_mdp>, <&mmdvfs_clk CLK_MMDVFS_MML PWR_MMDVFS_VCORE 3 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_mdp>, <&mmdvfs_clk CLK_MMDVFS_SMI_COMMON0 PWR_MMDVFS_VCORE 4 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_mminfra>, <&mmdvfs_clk CLK_MMDVFS_SMI_COMMON1 PWR_MMDVFS_VCORE 4 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_mminfra>, <&mmdvfs_clk CLK_MMDVFS_VENC PWR_MMDVFS_VCORE 5 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_venc>, <&mmdvfs_clk CLK_MMDVFS_JPEGENC PWR_MMDVFS_VCORE 6 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_venc>, <&mmdvfs_clk CLK_MMDVFS_VDEC PWR_MMDVFS_VMM 7 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_vdec>, <&mmdvfs_clk CLK_MMDVFS_VFMT PWR_MMDVFS_VMM 8 IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_vdec>, <&mmdvfs_clk CLK_MMDVFS_JPEGDEC PWR_MMDVFS_VMM 6 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_venc>, <&mmdvfs_clk CLK_MMDVFS_IMG PWR_MMDVFS_VMM 9 IPI_MMDVFS_CCU SPEC_MMDVFS_NORMAL &opp_table_img>, <&mmdvfs_clk CLK_MMDVFS_IPE PWR_MMDVFS_VMM 9 IPI_MMDVFS_CCU SPEC_MMDVFS_NORMAL &opp_table_img>, <&mmdvfs_clk CLK_MMDVFS_CAM PWR_MMDVFS_VMM 10 IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_cam>, <&mmdvfs_clk CLK_MMDVFS_CCU PWR_MMDVFS_VMM 10 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_cam>, <&mmdvfs_clk CLK_MMDVFS_AOV PWR_MMDVFS_VMM 11 IPI_MMDVFS_VCP SPEC_MMDVFS_ALONE &opp_table_cam>, <&mmdvfs_clk CLK_MMDVFS_VCORE PWR_MMDVFS_VCORE 12 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_vote>, <&mmdvfs_clk CLK_MMDVFS_VMM PWR_MMDVFS_VMM 13 IPI_MMDVFS_VCP SPEC_MMDVFS_NORMAL &opp_table_vote>; mediatek,mmdvfs-clock-names = "disp", "mdp", "mml", "smi_common0", "smi_common1", "venc", "jpegenc", "vdec", "vfmt", "jpegdec", "img", "ipe", "cam", "ccu", "aov", "vcore", "vmm"; mediatek,ccu-rproc = <&ccu_rproc>; mediatek,larbs = <&smi_larb5>; mediatek,dpsw-thr = <1>; #clock-cells = <1>; clocks = <&mmdvfs_clk CLK_MMDVFS_VCORE>, <&mmdvfs_clk CLK_MMDVFS_VMM>, <&mmdvfs_clk CLK_MMDVFS_VFMT>, <&mmdvfs_clk CLK_MMDVFS_CAM>, <&mmdvfs_clk CLK_MMDVFS_IMG>; clock-names = "pwr_vcore", "pwr_vmm", "rst_vfmt", "rst_cam", "rst_img"; }; ktf-mmdvfs-test { compatible = "mediatek,ktf-mmdvfs-test"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_RDMA0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_2_WDMA) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L4_HW_VDEC_VLD_EXT) &mmqos SLAVE_COMMON(1)>; interconnect-names = "mmdvfs_interconnect1", "mmdvfs_interconnect2", "mmdvfs_interconnect3"; }; mmdvfs-debug { compatible = "mediatek,mmdvfs-debug"; dvfsrc-vcore-supply = <&dvfsrc_vcore>; disp-dev = <&dispsys_config>; force-step0 = <1>; /* 0:opp0, 1:opp1, ... */ release-step0 = <1>; /* 0:disable, 1:enable */ use-v3-pwr = <2>; /* OR operation of (1 << PWR_MMDVFS_XXX) */ vcore-supply = <&mt6363_vbuck6>; vmm-pmic-supply = <&mt6319_6_vbuck3>; fmeter-id = /bits/ 8 <5 6 7 8 9 10 11 58 57 58 69 70 71>; fmeter-type = /bits/ 8 <2 2 2 2 2 2 2 2 5 5 5 5 5>; }; mmdvfs-v3-start { compatible = "mediatek,mmdvfs-v3-start"; }; mmdvfs-ccu { compatible = "mediatek,mmdvfs-ccu"; }; mmdvfs { compatible = "mediatek,mmdvfs"; operating-points-v2 = <&opp_table_disp>; mediatek,support-mux = "disp0", "disp1", "disp2", "disp3", "mminfra", "mdp0", "mdp1", "venc"; mediatek,mux-disp0 = "TOP_MMPLL_D6_D2", "TOP_MAINPLL_D6", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4", "TOP_MAINPLL_D3"; mediatek,mux-disp1 = "TOP_MMPLL_D6_D2", "TOP_MAINPLL_D6", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4", "TOP_MAINPLL_D3"; mediatek,mux-disp2 = "TOP_MMPLL_D6_D2", "TOP_MAINPLL_D6", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4", "TOP_MAINPLL_D3"; mediatek,mux-disp3 = "TOP_MMPLL_D6_D2", "TOP_MAINPLL_D6", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4", "TOP_MAINPLL_D3"; mediatek,mux-mminfra = "TOP_MAINPLL_D5_D2", "TOP_MMPLL_D4_D2", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4", "TOP_MAINPLL_D3"; mediatek,mux-mdp0 = "TOP_MMPLL_D6_D2", "TOP_MAINPLL_D6", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4", "TOP_MAINPLL_D3"; mediatek,mux-mdp1 = "TOP_MMPLL_D6_D2", "TOP_MAINPLL_D6", "TOP_MMPLL_D6", "TOP_UNIVPLL_D4", "TOP_MAINPLL_D3"; mediatek,mux-venc = "TOP_UNIVPLL2_D5_D2", "TOP_UNIVPLL2_D4_D2", "TOP_MMPLL2_D6", "TOP_UNIVPLL2_D4", "TOP_MMPLL2_D4"; mediatek,mux-lp = "TOP_MAINPLL_D5_D2", "TOP_MAINPLL_D5_D2", "TOP_MAINPLL_D5_D2", "TOP_MAINPLL_D5_D2", "", "", "", ""; dvfsrc-vcore-supply = <&dvfsrc_vcore>; clocks = <&topckgen_clk CLK_TOP_DISP0_SEL>, /* 0 */ <&topckgen_clk CLK_TOP_DISP1_SEL>, /* 1 */ <&topckgen_clk CLK_TOP_OVL0_SEL>, /* 2 */ <&topckgen_clk CLK_TOP_OVL1_SEL>, /* 3 */ <&topckgen_clk CLK_TOP_MMINFRA_SEL>, /* 4 */ <&topckgen_clk CLK_TOP_MDP0_SEL>, /* 5 */ <&topckgen_clk CLK_TOP_MDP1_SEL>, /* 6 */ <&topckgen_clk CLK_TOP_VENC_SEL>, /* 7 */ <&topckgen_clk CLK_TOP_MMPLL_D6_D2>, /* 8 */ <&topckgen_clk CLK_TOP_MAINPLL_D6>, /* 9 */ <&topckgen_clk CLK_TOP_MMPLL_D6>, /* 10 */ <&topckgen_clk CLK_TOP_UNIVPLL_D4>, /* 11 */ <&topckgen_clk CLK_TOP_MAINPLL_D3>, /* 12 */ <&topckgen_clk CLK_TOP_MAINPLL_D5_D2>, /* 13 */ <&topckgen_clk CLK_TOP_MMPLL_D4_D2>, /* 14 */ <&topckgen_clk CLK_TOP_UNIVPLL_D5_D2>, /* 15 */ <&topckgen_clk CLK_TOP_UNIVPLL2_D5_D2>, /* 16 */ <&topckgen_clk CLK_TOP_UNIVPLL2_D4_D2>, /* 17 */ <&topckgen_clk CLK_TOP_MMPLL2_D6>, /* 18 */ <&topckgen_clk CLK_TOP_UNIVPLL2_D4>, /* 19 */ <&topckgen_clk CLK_TOP_MMPLL2_D4>, /* 20 */ <&topckgen_clk CLK_TOP_MMINFRA_SEL>, /* 21 */ <&topckgen_clk CLK_TOP_OSC_D4>, /* 22 */ <&topckgen_clk CLK_TOP_MAINPLL_D5_D2>; /* 23 */ clock-names = "disp0", /* 0 */ "disp1", /* 1 */ "disp2", /* 2 */ "disp3", /* 3 */ "mminfra", /* 4 */ "mdp0", /* 5 */ "mdp1", /* 6 */ "venc", /* 7 */ "TOP_MMPLL_D6_D2", /* 8 */ "TOP_MAINPLL_D6", /* 9 */ "TOP_MMPLL_D6", /* 10 */ "TOP_UNIVPLL_D4", /* 11 */ "TOP_MAINPLL_D3", /* 12 */ "TOP_MAINPLL_D5_D2", /* 13 */ "TOP_MMPLL_D4_D2", /* 14 */ "TOP_UNIVPLL_D5_D2", /* 15 */ "TOP_UNIVPLL2_D5_D2", /* 16 */ "TOP_UNIVPLL2_D4_D2", /* 17 */ "TOP_MMPLL2_D6", /* 18 */ "TOP_UNIVPLL2_D4", /* 19 */ "TOP_MMPLL2_D4", /* 20 */ "aov_mux", /* 21 */ "aov_lp_clk", /* 22 */ "aov_clk"; /* 23 */ }; vcu: vcu@16000000 { compatible = "mediatek-vcu"; mediatek,vcuid = <0>; mediatek,vcuname = "vcu"; mediatek,vcp-support = <3>; reg = <0 0x16000000 0 0x40000>, /* VDEC_BASE */ <0 0x17020000 0 0x10000>, /* VENC_BASE */ <0 0x17820000 0 0x10000>, /* VENC_C1_BASE */ <0 0x17c20000 0 0x10000>, /* VENC_C2_BASE */ <0 0x17000000 0 0x1000>, /* VENC_C0_GCON_BASE */ <0 0x17800000 0 0x1000>, /* VENC_C1_GCON_BASE */ <0 0x17c00000 0 0x1000>, /* VENC_C2_GCON_BASE */ <0 0x14006000 0 0x1000>, /* DISP_WDMA0_BASE */ <0 0x14106000 0 0x1000>; /* DISP_WDMA1_BASE */ iommus = <&disp_iommu M4U_PORT_L5_HW_VDEC_LAT0_VLD_EXT>, <&disp_iommu M4U_PORT_L5_HW_VDEC_LAT0_VLD2_EXT>, <&disp_iommu M4U_PORT_L5_HW_VDEC_LAT0_AVC_MV_EXT>, <&disp_iommu M4U_PORT_L5_HW_VDEC_LAT0_PRED_RD_EXT>, <&disp_iommu M4U_PORT_L5_HW_VDEC_LAT0_TILE_EXT>, <&disp_iommu M4U_PORT_L5_HW_VDEC_LAT0_WDMA_EXT>, <&disp_iommu M4U_PORT_L5_HW_VDEC_UFO_ENC_EXT>, <&disp_iommu M4U_PORT_L5_HW_VDEC_UFO_ENC_EXT_C>, <&disp_iommu M4U_PORT_L5_HW_VDEC_MC_EXT>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; }; vcu-iommu-venc { compatible = "mediatek,vcu-io-venc"; mediatek,vcuid = <0>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L7_VENC_RCPU>, <&disp_iommu M4U_PORT_L7_VENC_REC>, <&disp_iommu M4U_PORT_L7_VENC_BSDMA>, <&disp_iommu M4U_PORT_L7_VENC_SV_COMV>, <&disp_iommu M4U_PORT_L7_VENC_RD_COMV>, <&disp_iommu M4U_PORT_L7_VENC_NBM_RDMA>, <&disp_iommu M4U_PORT_L7_VENC_NBM_RDMA_LITE>, <&disp_iommu M4U_PORT_L7_VENC_NBM_WDMA>, <&disp_iommu M4U_PORT_L7_VENC_NBM_WDMA_LITE>, <&disp_iommu M4U_PORT_L7_VENC_CUR_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_CUR_CHROMA>, <&disp_iommu M4U_PORT_L7_VENC_REF_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_REF_CHROMA>, <&disp_iommu M4U_PORT_L7_VENC_SUB_R_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_SUB_W_LUMA>, <&disp_iommu M4U_PORT_L7_VENC_FCS_NBM_RDMA>, <&disp_iommu M4U_PORT_L7_VENC_FCS_NBM_WDMA>, <&disp_iommu M4U_PORT_L7_VENC_EC_WPP_BSDMA>, <&disp_iommu M4U_PORT_L7_VENC_EC_WPP_RDMA>, <&disp_iommu M4U_PORT_L7_VENC_DB_SYSRAM_WDMA>, <&disp_iommu M4U_PORT_L7_VENC_DB_SYSRAM_RDMA>; }; vdec@16000000 { compatible = "mediatek,mt6985-vcodec-dec"; mediatek,platform = "platform:mt6985"; mediatek,ipm = <2>; reg = <0 0x16000000 0 0x1000>, /* VDEC_BASE */ <0 0x1602f000 0 0x1000>, /* VDEC_SYS */ <0 0x16020000 0 0x1000>, /* VDEC_VLD */ <0 0x16021000 0 0x1000>, /* VDEC_MC */ <0 0x16023000 0 0x1000>, /* VDEC_MV */ <0 0x16025000 0 0x4000>, /* VDEC_MISC */ <0 0x16010000 0 0x1000>, /* VDEC_LAT_MISC */ <0 0x16011000 0 0x400>, /* VDEC_LAT_VLD */ <0 0x1600f000 0 0x1000>, /* VDEC_SOC_GCON */ <0 0x16004000 0 0x1000>, /* VDEC_RACING_CTRL */ <0 0x16012000 0 0x1000>, /* VDEC_LAT_AVC_VLD */ <0 0x16022000 0 0x1000>; /* VDEC_AVC_VLD */ reg-names = "VDEC_BASE", "VDEC_SYS", "VDEC_VLD", "VDEC_MC", "VDEC_MV", "VDEC_MISC", "VDEC_LAT_MISC", "VDEC_LAT_VLD", "VDEC_SOC_GCON", "VDEC_RACING_CTRL", "VDEC_LAT_AVC_VLD", "VDEC_AVC_VLD"; iommus = <&mdp_iommu M4U_PORT_L4_HW_VDEC_MC_C_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_UFO_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_PP_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_PRED_RD_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_PRED_WR_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_PPWRAP_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_TILE_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_VLD_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_VLD2_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_AVC_MV_EXT>, <&mdp_iommu M4U_PORT_L4_HW_VDEC_UFO_EXT_C>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; mediatek,larbs = <&smi_larb4 &smi_larb5>; interrupts = , ; power-domains = <&scpsys MT6985_POWER_DOMAIN_VDE0>, <&scpsys MT6985_POWER_DOMAIN_VDE1>; mediatek,vcu = <&vcu>; clocks = <&vdec_soc_gcon_base_clk CLK_VDE1_VDEC_CKEN>, <&vdec_soc_gcon_base_clk CLK_VDE1_LAT_CKEN>, <&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN>; clock-names = "SOC_MT_CG_SOC", "LAT_MT_CG_VDEC1", "CORE_MT_CG_VDEC0"; mediatek,clock-parents = <4 3>; operating-points-v2 = <&opp_table_vdec>; m4u-ports = , , , , , , , , , , , , , , , , , , , , , ; m4u-port-names = "M4U_PORT_VDEC_MC", "M4U_PORT_VDEC_UFO", "M4U_PORT_VDEC_PP", "M4U_PORT_VDEC_PRED_RD", "M4U_PORT_VDEC_PRED_WR", "M4U_PORT_VDEC_PPWRAP", "M4U_PORT_VDEC_TILE", "M4U_PORT_VDEC_VLD", "M4U_PORT_VDEC_VLD2", "M4U_PORT_VDEC_AVC_MV", "M4U_PORT_VDEC_UFO_ENC", "M4U_PORT_VDEC_LAT0_VLD", "M4U_PORT_VDEC_LAT0_VLD2", "M4U_PORT_VDEC_LAT0_AVC_MV", "M4U_PORT_VDEC_LAT0_PRED_RD", "M4U_PORT_VDEC_LAT0_TILE", "M4U_PORT_VDEC_LAT0_WDMA", "M4U_PORT_VDEC_LAT0_UFO_ENC", "M4U_PORT_VDEC_LAT0_UFO_ENC_C", "M4U_PORT_VDEC_LAT0_MC", "M4U_PORT_VDEC_VIDEO_UP_SEC", "M4U_PORT_VDEC_VIDEO_UP_NOR"; interconnects = <&mmqos SLAVE_LARB(4) &mmqos SLAVE_COMMON(1)>, <&mmqos SLAVE_LARB(5) &mmqos SLAVE_COMMON(0)>; interconnect-names = "path_larb4", "path_larb5"; interconnect-num = <2>; throughput-op-rate-thresh = <120>; throughput-min = <182000000>; throughput-normal-max = <880000000>; profile-duration = <60 2000>; profile-target = <15 25 30 50 60 90 120 150 180 240 480>; max-op-rate-table = <877088845 2073600 120 3686400 60 8847360 15 35389440 5>, /* MPEG4 */ <859189832 2073600 120 3686400 60 8847360 15 35389440 5>, /* H.263 */ <875967048 2073600 180 3686400 115 8847360 60 35389440 30>, /* H.264 */ <826496577 2073600 180 3686400 115 8847360 60 35389440 30>, /* H.264 */ <1129727304 2073600 180 3686400 115 8847360 60 35389440 30>, /* HEVC */ <892744264 2073600 180 3686400 115 8847360 60 35389440 30>, /* H.265 */ <1179206984 262144 550 2097152 550 8847360 60 35389440 30>, /* HEIF */ <809062486 2073600 180 3686400 120 8847360 60 35389440 30>, /* VP9 */ <808539713 2073600 180 3686400 120 8847360 60 35389440 30>; /* AV1 */ throughput-table = <877088845 0 417 417>, /* MPEG4 */ <859189832 0 417 417>, /* H.263 */ <875967048 0 185 185>, /* H.264 */ <826496577 0 185 185>, /* H.264 */ <1129727304 0 185 185>, /* HEVC */ <892744264 0 185 185>, /* H.265 */ <1179206984 0 185 185>, /* HEIF */ <809062486 0 185 185>, /* VP9 */ <808539713 0 185 185>; /* AV1 */ bandwidth-table = <4 0 0>, <5 1 2450>; /* read only */ }; venc@17020000 { compatible = "mediatek,mt6985-vcodec-enc"; mediatek,platform = "platform:mt6985"; mediatek,ipm = <2>; reg = <0 0x17020000 0 0x6000>, <0 0x17820000 0 0x6000>, <0 0x17c20000 0 0x6000>; reg-names = "VENC_SYS", "VENC_C1_SYS", "VENC_C2_SYS"; iommus = <&mdp_iommu M4U_PORT_L8_VENC_RCPU>, <&mdp_iommu M4U_PORT_L8_VENC_REC>, <&mdp_iommu M4U_PORT_L8_VENC_BSDMA>, <&mdp_iommu M4U_PORT_L8_VENC_SV_COMV>, <&mdp_iommu M4U_PORT_L8_VENC_RD_COMV>, <&mdp_iommu M4U_PORT_L8_VENC_NBM_RDMA>, <&mdp_iommu M4U_PORT_L8_VENC_NBM_RDMA_LITE>, <&mdp_iommu M4U_PORT_L8_VENC_NBM_WDMA>, <&mdp_iommu M4U_PORT_L8_VENC_NBM_WDMA_LITE>, <&mdp_iommu M4U_PORT_L8_VENC_CUR_LUMA>, <&mdp_iommu M4U_PORT_L8_VENC_CUR_CHROMA>, <&mdp_iommu M4U_PORT_L8_VENC_REF_LUMA>, <&mdp_iommu M4U_PORT_L8_VENC_REF_CHROMA>, <&mdp_iommu M4U_PORT_L8_VENC_SUB_R_LUMA>, <&mdp_iommu M4U_PORT_L8_VENC_SUB_W_LUMA>, <&mdp_iommu M4U_PORT_L8_VENC_FCS_NBM_RDMA>, <&mdp_iommu M4U_PORT_L8_VENC_FCS_NBM_WDMA>, <&mdp_iommu M4U_PORT_L8_VENC_EC_WPP_BSDMA>, <&mdp_iommu M4U_PORT_L8_VENC_EC_WPP_RDMA>, <&mdp_iommu M4U_PORT_L8_VENC_DB_SYSRAM_WDMA>, <&mdp_iommu M4U_PORT_L8_VENC_DB_SYSRAM_RDMA>; mediatek,larbs = <&smi_larb7 &smi_larb8 &smi_larb37>; interrupts = , , ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_VEN0>, <&scpsys MT6985_POWER_DOMAIN_VEN1>, <&scpsys MT6985_POWER_DOMAIN_VEN2>; mediatek,vcu = <&vcu>; clocks = <&venc_gcon_clk CLK_VEN_CKE1_VENC>, <&venc_gcon_core1_clk CLK_VEN_C1_CKE1_VENC>, <&venc_gcon_core2_clk CLK_VEN_C2_CKE1_VENC>, <&mmdvfs_clk CLK_MMDVFS_VENC>; clock-names = "MT_CG_VENC0", "MT_CG_VENC1", "MT_CG_VENC2", "mmdvfs_clk"; operating-points-v2 = <&opp_table_venc>; mmdvfs-dvfsrc-vcore-supply = <&dvfsrc_vcore>; port-arg-num = <3>; port-def = <0 M4U_PORT_L7_VENC_RCPU 0>, <0 M4U_PORT_L7_VENC_REC 0>, <0 M4U_PORT_L7_VENC_BSDMA 0>, <0 M4U_PORT_L7_VENC_SV_COMV 0>, <0 M4U_PORT_L7_VENC_RD_COMV 0>, <0 M4U_PORT_L7_VENC_NBM_RDMA 1>, <0 M4U_PORT_L7_VENC_NBM_RDMA_LITE 1>, <0 M4U_PORT_L7_JPGENC_Y_RDMA 0>, <0 M4U_PORT_L7_JPGENC_C_RDMA 0>, <0 M4U_PORT_L7_JPGENC_Q_TABLE 0>, <0 M4U_PORT_L7_VENC_SUB_W_LUMA 0>, <0 M4U_PORT_L7_VENC_FCS_NBM_RDMA 1>, <0 M4U_PORT_L7_VENC_EC_WPP_BSDMA 0>, <0 M4U_PORT_L7_VENC_EC_WPP_RDMA 0>, <0 M4U_PORT_L7_VENC_DB_SYSRAM_WDMA 1>, <0 M4U_PORT_L7_VENC_DB_SYSRAM_RDMA 1>, <0 M4U_PORT_L7_JPGENC_BSDMA 0>, <0 M4U_PORT_L7_JPGDEC_WDMA_0 0>, <0 M4U_PORT_L7_JPGDEC_BSDMA_0 0>, <0 M4U_PORT_L7_VENC_NBM_WDMA 1>, <0 M4U_PORT_L7_VENC_NBM_WDMA_LITE 1>, <0 M4U_PORT_L7_VENC_CUR_LUMA 0>, <0 M4U_PORT_L7_VENC_CUR_CHROMA 0>, <0 M4U_PORT_L7_VENC_REF_LUMA 0>, <0 M4U_PORT_L7_VENC_REF_CHROMA 0>, <0 M4U_PORT_L7_VENC_SUB_R_LUMA 0>, <0 M4U_PORT_L7_VENC_FCS_NBM_WDMA 1>, <0 M4U_PORT_L7_JPGDEC_WDMA_1 0>, <0 M4U_PORT_L7_JPGDEC_BSDMA_1 0>, <0 M4U_PORT_L7_JPGDEC_HUFF_OFFSET_1 0>, <0 M4U_PORT_L7_JPGDEC_HUFF_OFFSET_0 0>, <1 M4U_PORT_L8_VENC_RCPU 0>, <1 M4U_PORT_L8_VENC_REC 0>, <1 M4U_PORT_L8_VENC_BSDMA 0>, <1 M4U_PORT_L8_VENC_SV_COMV 0>, <1 M4U_PORT_L8_VENC_RD_COMV 0>, <1 M4U_PORT_L8_VENC_NBM_RDMA 1>, <1 M4U_PORT_L8_VENC_NBM_RDMA_LITE 1>, <1 M4U_PORT_L8_JPGENC_Y_RDMA 0>, <1 M4U_PORT_L8_JPGENC_C_RDMA 0>, <1 M4U_PORT_L8_JPGENC_Q_TABLE 0>, <1 M4U_PORT_L8_VENC_SUB_W_LUMA 0>, <1 M4U_PORT_L8_VENC_FCS_NBM_RDMA 1>, <1 M4U_PORT_L8_VENC_EC_WPP_BSDMA 0>, <1 M4U_PORT_L8_VENC_EC_WPP_RDMA 0>, <1 M4U_PORT_L8_VENC_DB_SYSRAM_WDMA 1>, <1 M4U_PORT_L8_VENC_DB_SYSRAM_RDMA 1>, <1 M4U_PORT_L8_JPGENC_BSDMA 0>, <1 M4U_PORT_L8_JPGDEC_WDMA_0 0>, <1 M4U_PORT_L8_JPGDEC_BSDMA_0 0>, <1 M4U_PORT_L8_VENC_NBM_WDMA 1>, <1 M4U_PORT_L8_VENC_NBM_WDMA_LITE 1>, <1 M4U_PORT_L8_VENC_CUR_LUMA 0>, <1 M4U_PORT_L8_VENC_CUR_CHROMA 0>, <1 M4U_PORT_L8_VENC_REF_LUMA 0>, <1 M4U_PORT_L8_VENC_REF_CHROMA 0>, <1 M4U_PORT_L8_VENC_SUB_R_LUMA 0>, <1 M4U_PORT_L8_VENC_FCS_NBM_WDMA 1>, <1 M4U_PORT_L8_JPGDEC_WDMA_1 0>, <1 M4U_PORT_L8_JPGDEC_BSDMA_1 0>, <1 M4U_PORT_L8_JPGDEC_HUFF_OFFSET_1 0>, <1 M4U_PORT_L8_JPGDEC_HUFF_OFFSET_0 0>, <2 M4U_PORT_L37_VENC_RCPU 0>, <2 M4U_PORT_L37_VENC_REC 0>, <2 M4U_PORT_L37_VENC_BSDMA 0>, <2 M4U_PORT_L37_VENC_SV_COMV 0>, <2 M4U_PORT_L37_VENC_RD_COMV 0>, <2 M4U_PORT_L37_VENC_NBM_RDMA 1>, <2 M4U_PORT_L37_VENC_NBM_RDMA_LITE 1>, <2 M4U_PORT_L37_JPGENC_Y_RDMA 0>, <2 M4U_PORT_L37_JPGENC_C_RDMA 0>, <2 M4U_PORT_L37_JPGENC_Q_TABLE 0>, <2 M4U_PORT_L37_VENC_SUB_W_LUMA 0>, <2 M4U_PORT_L37_VENC_FCS_NBM_RDMA 1>, <2 M4U_PORT_L37_VENC_EC_WPP_BSDMA 0>, <2 M4U_PORT_L37_VENC_EC_WPP_RDMA 0>, <2 M4U_PORT_L37_VENC_DB_SYSRAM_WDMA 1>, <2 M4U_PORT_L37_VENC_DB_SYSRAM_RDMA 1>, <2 M4U_PORT_L37_JPGENC_BSDMA 0>, <2 M4U_PORT_L37_JPGDEC_WDMA_0 0>, <2 M4U_PORT_L37_JPGDEC_BSDMA_0 0>, <2 M4U_PORT_L37_VENC_NBM_WDMA 1>, <2 M4U_PORT_L37_VENC_NBM_WDMA_LITE 1>, <2 M4U_PORT_L37_VENC_CUR_LUMA 0>, <2 M4U_PORT_L37_VENC_CUR_CHROMA 0>, <2 M4U_PORT_L37_VENC_REF_LUMA 0>, <2 M4U_PORT_L37_VENC_REF_CHROMA 0>, <2 M4U_PORT_L37_VENC_SUB_R_LUMA 0>, <2 M4U_PORT_L37_VENC_FCS_NBM_WDMA 1>, <2 M4U_PORT_L37_JPGDEC_WDMA_1 0>, <2 M4U_PORT_L37_JPGDEC_BSDMA_1 0>, <2 M4U_PORT_L37_JPGDEC_HUFF_OFFSET_1 0>, <2 M4U_PORT_L37_JPGDEC_HUFF_OFFSET_0 0>; interconnects = <&mmqos SLAVE_LARB(7) &mmqos SLAVE_COMMON(0)>, <&mmqos SLAVE_LARB(8) &mmqos SLAVE_COMMON(1)>, <&mmqos SLAVE_LARB(37) &mmqos SLAVE_COMMON(1)>; interconnect-names = "path_larb7", "path_larb8", "path_larb37"; interconnect-num = <3>; throughput-op-rate-thresh = <120>; throughput-min = <250000000>; throughput-normal-max = <624000000>; throughput-config-offset = <2>; throughput-table = /* H.264 */ <875967048 3 1394 2624 250000000 52>, /* 720p */ <875967048 4 996 1632 250000000 77>, /* 1080p30 */ <875967048 5 891 1492 250000000 86>, /* 1080p60 */ <875967048 12 476 595 250000000 161>, /* 4K30 */ <875967048 16 298 394 312000000 153>, /* 4K60 */ <875967048 17 300 397 624000000 300>, /* 8K30 */ /* HEVC */ <1129727304 1 1394 1491 250000000 100>, /* 720p */ <1129727304 2 996 1065 250000000 100>, /* 1080p30 */ <1129727304 4 891 1146 250000000 137>, /* 1080p60 */ <1129727304 9 476 810 250000000 211>, /* 4K30 */ <1129727304 10 298 525 312000000 188>, /* 4K60 */ <1129727304 11 220 388 458000000 314>, /* 8K30 */ /* H.265 */ <892744264 1 1394 1491 250000000 100>, /* 720p */ <892744264 2 996 1065 250000000 100>, /* 1080p30 */ <892744264 4 891 1146 250000000 137>, /* 1080p60 */ <892744264 9 476 810 250000000 211>, /* 4K30 */ <892744264 10 298 525 312000000 188>, /* 4K60 */ <892744264 11 220 388 458000000 314>, /* 8K30 */ /* HEIF */ <1179206984 1 1394 1491 250000000 100>, /* 720p */ <1179206984 2 996 1065 250000000 100>, /* 1080p30 */ <1179206984 4 891 1146 250000000 137>, /* 1080p60 */ <1179206984 9 476 810 250000000 211>, /* 4K30 */ <1179206984 10 298 525 312000000 188>, /* 4K60 */ <1179206984 11 220 388 458000000 314>; /* 8K30 */ config-table = <875967048 108000 3 3>, /* H.264 */ <875967048 244800 4 4>, <875967048 489600 5 5>, <875967048 1044480 12 12>, <875967048 1944000 16 16>, <875967048 4294967295 17 17>, <1129727304 108000 1 1>, /* HEVC */ <1129727304 244800 2 2>, <1129727304 489600 4 4>, <1129727304 1044480 9 9>, <1129727304 1944000 10 11>, <1129727304 4294967295 11 11>, <892744264 108000 1 1>, /* H.265 */ <892744264 244800 2 2>, <892744264 489600 4 4>, <892744264 1044480 9 9>, <892744264 1944000 10 10>, <892744264 4294967295 11 11>, <1179206984 108000 1 1>, /* HEIF */ <1179206984 244800 2 2>, <1179206984 489600 4 4>, <1179206984 1044480 9 9>, <1179206984 1944000 10 10>, <1179206984 4294967295 11 11>; bandwidth-table = <7 0 447>, <8 1 481>, <37 2 404>; }; vcp: vcp@1ec00000 { compatible = "mediatek,vcp"; vcp-support = <1>; status = "okay"; reg = <0 0x1ea00000 0 0x40000>, /* tcm */ <0 0x1ec24000 0 0x1000>, /* cfg */ <0 0x1ec30000 0 0x1000>, /* cfg core0 */ <0 0x1ec40000 0 0x1000>, /* cfg core1 */ <0 0x1ec52000 0 0x1000>, /* bus tracker dbg */ <0 0x1ec60000 0 0x40000>, /* llc dbg */ <0 0x1eca5000 0 0x4>, /* cfg_sec dbg */ <0 0x1e820000 0 0x4>, /* mmu dbg */ <0 0x1ecfb000 0 0x100>, /* mbox0 base */ <0 0x1ecfb100 0 0x4>, /* mbox0 set */ <0 0x1ecfb10c 0 0x4>, /* mbox0 clr */ <0 0x1eca5020 0 0x4>, /* mbox0 init */ <0 0x1ecfc000 0 0x100>, /* mbox1 base */ <0 0x1ecfc100 0 0x4>, /* mbox1 set */ <0 0x1ecfc10c 0 0x4>, /* mbox1 clr */ <0 0x1eca5024 0 0x4>, /* mbox1 init */ <0 0x1ecfd000 0 0x100>, /* mbox2 base */ <0 0x1ecfd100 0 0x4>, /* mbox2 set */ <0 0x1ecfd10c 0 0x4>, /* mbox2 clr */ <0 0x1eca5028 0 0x4>, /* mbox2 init */ <0 0x1ecfe000 0 0x100>, /* mbox3 base */ <0 0x1ecfe100 0 0x4>, /* mbox3 set */ <0 0x1ecfe10c 0 0x4>, /* mbox3 clr */ <0 0x1eca502c 0 0x4>, /* mbox3 init */ <0 0x1ecff000 0 0x100>, /* mbox4 base */ <0 0x1ecff100 0 0x4>, /* mbox4 set */ <0 0x1ecff10c 0 0x4>, /* mbox4 clr */ <0 0x1eca5030 0 0x4>, /* mbox4 init */ <0 0x1c001000 0 0x1000>; /* spm */ reg-names = "vcp_sram_base", "vcp_cfgreg", "vcp_cfgreg_core0", "vcp_cfgreg_core1", "vcp_bus_tracker", "vcp_l1creg", "vcp_cfgreg_sec", "vcp_cfgreg_mmu", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_init", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_init", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_init", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_init", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_init", "spm"; interrupts = , , , , , , ; interrupt-names = "wdt", "reserved", "mbox0", "mbox1", "mbox2", "mbox3", "mbox4"; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&mdp_iommu M4U_PORT_L39_VIDEO_UP1>; mediatek,smi = <&mmsram_smi_2x1_sub_comm4 &smi_mdp_2x1_subcommon>; core-0 = "enable"; vcp-sramSize = <0x00040000>; vcp-dramSize = <0x00800000>; core-nums = <1>; /* core number */ twohart = <1>; /* two hart arch */ femter-ck = <12>; /* clk table fmeter f_fmmup_ck */ mbox-count = <5>; vcp-ee-enable = <0>; /* id, mbox, send_size*/ send-table = < 0 0 18>,/* IPI_OUT_VDEC_1 */ < 2 1 2>,/* IPI_OUT_C_SLEEP_0 */ < 3 1 1>,/* IPI_OUT_TEST_0 */ < 9 1 2>,/* IPI_OUT_MMDVFS */ <11 1 4>,/* IPI_OUT_C_VCP_HWVOTER_DEBUG */ <12 2 18>,/* IPI_OUT_VENC_0 */ <14 2 4>,/* IPI_OUT_VCP_MPOOL_0 */ <16 3 2>,/* IPI_OUT_C_SLEEP_1 */ <17 3 1>,/* IPI_OUT_TEST_1 */ <18 3 6>,/* IPI_OUT_LOGGER_CTRL */ <19 3 2>,/* IPI_OUT_VCPCTL_1 */ <24 4 4>;/* IPI_OUT_VCP_MPOOL_1 */ /* id, mbox, recv_size, recv_opt */ recv-table = < 1 0 18 0>,/* IPI_IN_VDEC_1 */ < 2 1 1 1>,/* IPI_OUT_C_SLEEP_0 */ < 4 1 10 0>,/* IPI_IN_VCP_ERROR_INFO_0 */ < 5 1 1 0>,/* IPI_IN_VCP_READY_0 */ < 6 1 2 0>,/* IPI_IN_VCP_RAM_DUMP_0 */ <10 1 2 0>,/* IPI_IN_MMDVFS */ <11 1 4 1>,/* IPI_OUT_C_VCP_HWVOTER_DEBUG */ <13 2 18 0>,/* IPI_IN_VENC_0 */ <15 2 4 0>,/* IPI_IN_VCP_MPOOL_0 */ <16 3 1 1>,/* IPI_OUT_C_SLEEP_1 */ <20 3 10 0>,/* IPI_IN_VCP_ERROR_INFO_1 */ <21 3 6 0>,/* IPI_IN_LOGGER_CTRL */ <22 3 1 0>,/* IPI_IN_VCP_READY_1 */ <23 3 2 0>,/* IPI_IN_VCP_RAM_DUMP_1 */ <25 4 4 0>;/* IPI_IN_VCP_MPOOL_1 */ vcp-secure-dump = <1>; /* enable dump via secure world*/ vcp-secure-dump-size = <0x200000>; vcp-secure-dump-offset = <0x600000>; vcp-sec-dump-key = "mediatek,me_vcp_reserved"; memorydump = <0x40000>, /* l2tcm */ <0x020000>, /* l1c */ <0x003f00>, /* regdump */ <0x000400>, /* trace buffer */ <0x160000>; /* dram */ vcp-mem-tbl = <0 0x78000>, /* VDEC_MEM_ID 480KB */ <1 0x8000>, /* VENC_MEM_ID 32KB */ <2 0x180000>, /* LOGGER 1MB 512KB*/ <3 0x400>, /* VDEC_SET_PROP_MEM_ID 1KB */ <4 0x400>, /* VENC_SET_PROP_MEM_ID 1KB */ <5 0x400>, /* VDEC_VCP_LOG_INFO_ID 1KB */ <6 0x400>, /* VENC_VCP_LOG_INFO_ID 1KB */ <7 0x100000>, /* GCE_MEM_ID 256*4KB */ <8 0x1000>, /* MMDVFS_MEM_ID 4KB */ <9 0x0>; /* secure dump, its size is in secure_dump_size */ power-domains = <&scpsys MT6985_POWER_DOMAIN_MM_PROC_DORMANT>; clocks = <&topckgen_clk CLK_TOP_MMUP_SEL>, <&topckgen_clk CLK_TOP_MAINPLL_D3>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>; clock-names = "mmup-sel", "mmup-clk", "mmup-26m"; }; vcp_io2: vcp-iommu-vdec { compatible = "mediatek,vcp-io-vdec"; vcp-support = <2>; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&mdp_iommu M4U_PORT_L39_VIDEO_UP1>; }; vcp_io3: vcp-iommu-venc { compatible = "mediatek,vcp-io-venc"; vcp-support = <3>; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&mdp_iommu M4U_PORT_L39_VIDEO_UP1>; }; vcp_io4: vcp-iommu-work { compatible = "mediatek,vcp-io-work"; vcp-support = <4>; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&mdp_iommu M4U_PORT_L39_VIDEO_UP1>; }; vcp_io5: vcp-iommu-sec { #address-cells = <2>; #size-cells = <2>; compatible = "mediatek,vcp-io-sec"; vcp-support = <7>; dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>; iommus = <&mdp_iommu M4U_PORT_L39_VIDEO_UP0>; }; slbc: slbc@113e00 { compatible = "mediatek,mtk-slbc"; reg = <0 0x00113e00 0 0x200>; slbc-enable = <1>; apu = <2097152>; }; pmic-oc-debug { compatible = "mediatek,mt6983-oc-debug"; status = "okay"; }; extcon_usb: extcon-usb { compatible = "mediatek,extcon-usb"; vbus-supply = <&mt6375_otg_vbus>; vbus-voltage = <5000000>; vbus-current = <1800000>; charger = <&mt6375_chg>; tcpc = "type_c_port0"; mediatek,bypss-typec-sink = <1>; port { usb_role: endpoint { remote-endpoint = <&mtu3_drd_switch>; }; }; }; extcon_usb1: extcon-usb1 { compatible = "mediatek,extcon-usb"; port { usb_role1: endpoint { remote-endpoint = <&mtu3_drd_switch1>; }; }; }; usb_meta: usb-meta { compatible = "mediatek,usb-meta"; udc = <&ssusb>; }; usb_boost: usb-boost-manager { compatible = "mediatek,usb-boost", "mediatek,mt6985-usb-boost"; interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>; interconnect-names = "icc-bw"; required-opps = <&dvfsrc_freq_opp0>; usb-audio; small-core = <1250000>; }; smart_pa: smart_pa { }; afe: mt6985-afe-pcm@11050000 { compatible = "mediatek,mt6985-sound"; reg = <0 0x11050000 0 0x2000>; interrupts = ; topckgen = <&topckgen_clk>; apmixedsys = <&apmixedsys_clk>; infracfg = <&infracfg_ao_clk>; power-domains = <&scpsys MT6985_POWER_DOMAIN_AUDIO>; clocks = <&afe_clk CLK_AFE_AFE>, <&afe_clk CLK_AFE_DAC>, <&afe_clk CLK_AFE_DAC_PREDIS>, <&afe_clk CLK_AFE_ADC>, <&afe_clk CLK_AFE_ADDA6_ADC>, <&afe_clk CLK_AFE_22M>, <&afe_clk CLK_AFE_24M>, <&afe_clk CLK_AFE_APLL_TUNER>, <&afe_clk CLK_AFE_APLL2_TUNER>, <&afe_clk CLK_AFE_TDM>, <&afe_clk CLK_AFE_TML>, <&afe_clk CLK_AFE_NLE>, <&afe_clk CLK_AFE_DAC_HIRES>, <&afe_clk CLK_AFE_ADC_HIRES>, <&afe_clk CLK_AFE_ADC_HIRES_TML>, <&afe_clk CLK_AFE_ADDA6_ADC_HIRES>, <&afe_clk CLK_AFE_3RD_DAC>, <&afe_clk CLK_AFE_3RD_DAC_PREDIS>, <&afe_clk CLK_AFE_3RD_DAC_TML>, <&afe_clk CLK_AFE_3RD_DAC_HIRES>, <&topckgen_clk CLK_TOP_AUDIO_SEL>, <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>, <&topckgen_clk CLK_TOP_MAINPLL_D4_D4>, <&topckgen_clk CLK_TOP_AUD_1_SEL>, <&topckgen_clk CLK_TOP_APLL1>, <&topckgen_clk CLK_TOP_AUD_2_SEL>, <&topckgen_clk CLK_TOP_APLL2>, <&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>, <&topckgen_clk CLK_TOP_APLL1_D4>, <&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>, <&topckgen_clk CLK_TOP_APLL2_D4>, <&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S3_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S6_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S7_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S8_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL_I2S9_MCK_SEL>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV0>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV1>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV2>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV3>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV4>, <&topckgen_clk CLK_TOP_APLL12_CK_DIVB>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV5>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV6>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV7>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV8>, <&topckgen_clk CLK_TOP_APLL12_CK_DIV9>, <&topckgen_clk CLK_TOP_AUDIO_H_SEL>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>, <&pericfg_ao_clk CLK_PERAO_AUDIO_SLV>, <&pericfg_ao_clk CLK_PERAO_AUDIO_MST>, <&pericfg_ao_clk CLK_PERAO_AUDIO_INTBUS>; clock-names = "aud_afe_clk", "aud_dac_clk", "aud_dac_predis_clk", "aud_adc_clk", "aud_adda6_adc_clk", "aud_apll22m_clk", "aud_apll24m_clk", "aud_apll1_tuner_clk", "aud_apll2_tuner_clk", "aud_tdm_clk", "aud_tml_clk", "aud_nle", "aud_dac_hires_clk", "aud_adc_hires_clk", "aud_adc_hires_tml", "aud_adda6_adc_hires_clk", "aud_3rd_dac_clk", "aud_3rd_dac_predis_clk", "aud_3rd_dac_tml", "aud_3rd_dac_hires_clk", "top_mux_audio", "top_mux_audio_int", "top_mainpll_d4_d4", "top_mux_aud_1", "top_apll1_ck", "top_mux_aud_2", "top_apll2_ck", "top_mux_aud_eng1", "top_apll1_d4", "top_mux_aud_eng2", "top_apll2_d4", "top_i2s0_m_sel", "top_i2s1_m_sel", "top_i2s2_m_sel", "top_i2s3_m_sel", "top_i2s4_m_sel", "top_i2s5_m_sel", "top_i2s6_m_sel", "top_i2s7_m_sel", "top_i2s8_m_sel", "top_i2s9_m_sel", "top_apll12_div0", "top_apll12_div1", "top_apll12_div2", "top_apll12_div3", "top_apll12_div4", "top_apll12_divb", "top_apll12_div5", "top_apll12_div6", "top_apll12_div7", "top_apll12_div8", "top_apll12_div9", "top_mux_audio_h", "top_clk26m_clk", "aud_slv_ck_peri", "aud_mst_ck_peri", "aud_intbus_ck_peri"; pinctrl-names = "aud_clk_mosi_off", "aud_clk_mosi_on", "aud_dat_mosi_off", "aud_dat_mosi_on", "aud_dat_mosi_ch34_off", "aud_dat_mosi_ch34_on", "aud_dat_miso0_off", "aud_dat_miso0_on", "aud_dat_miso2_off", "aud_dat_miso2_on", "vow_dat_miso_off", "vow_dat_miso_on", "vow_clk_miso_off", "vow_clk_miso_on", "aud_gpio_i2s0_off", "aud_gpio_i2s0_on", "aud_gpio_i2s3_off", "aud_gpio_i2s3_on", "aud_gpio_i2s8_off", "aud_gpio_i2s8_on", "aud_gpio_i2s9_off", "aud_gpio_i2s9_on", "aud-gpio-etdmin-off", "aud-gpio-etdmin-on", "aud-gpio-etdmout-off", "aud-gpio-etdmout-on"; pinctrl-0 = <&aud_clk_mosi_off>; pinctrl-1 = <&aud_clk_mosi_on>; pinctrl-2 = <&aud_dat_mosi_off>; pinctrl-3 = <&aud_dat_mosi_on>; pinctrl-4 = <&aud_dat_mosi_ch34_off>; pinctrl-5 = <&aud_dat_mosi_ch34_on>; pinctrl-6 = <&aud_dat_miso0_off>; pinctrl-7 = <&aud_dat_miso0_on>; pinctrl-8 = <&aud_dat_miso2_off>; pinctrl-9 = <&aud_dat_miso2_on>; pinctrl-10 = <&vow_dat_miso_off>; pinctrl-11 = <&vow_dat_miso_on>; pinctrl-12 = <&vow_clk_miso_off>; pinctrl-13 = <&vow_clk_miso_on>; pinctrl-14 = <&aud_gpio_i2s0_off>; pinctrl-15 = <&aud_gpio_i2s0_on>; pinctrl-16 = <&aud_gpio_i2s3_off>; pinctrl-17 = <&aud_gpio_i2s3_on>; pinctrl-18 = <&aud_gpio_i2s8_off>; pinctrl-19 = <&aud_gpio_i2s8_on>; pinctrl-20 = <&aud_gpio_i2s9_off>; pinctrl-21 = <&aud_gpio_i2s9_on>; pinctrl-22 = <&aud_gpio_etdmin_off>; pinctrl-23 = <&aud_gpio_etdmin_on>; pinctrl-24 = <&aud_gpio_etdmout_off>; pinctrl-25 = <&aud_gpio_etdmout_on>; etdm-out-ch = <2>; etdm-in-ch = <2>; etdm-out-sync = <0>; /* 0: disable; 1: enable */ etdm-in-sync = <1>; /* 0: disable; 1: enable */ }; snd_scp_ultra: snd-scp-ultra { compatible = "mediatek,snd-scp-ultra"; scp-ultra-dl-memif-id = <0x7>; scp-ultra-ul-memif-id = <0x11>; }; audio_sram@11052000 { compatible = "mediatek,audio_sram"; reg = <0 0x11052000 0 0x18000>; prefer_mode = <0>; mode_size = <0x12000 0x18000>; block_size = <0x1000>; }; sound: sound { compatible = "mediatek,mt6985-mt6338-sound"; //mediatek,headset-codec = <&mt6338_accdet>; mediatek,platform = <&afe>; }; /* feature : $enable $dl_mem $ul_mem $ref_mem $size */ snd_audio_dsp: snd-audio-dsp { compatible = "mediatek,snd-audio-dsp"; mtk-dsp-voip = <0x1f 0xffffffff 0xffffffff 0xffffffff 0x30000>; mtk-dsp-primary = <0x5 0xffffffff 0xffffffff \ 0xffffffff 0x30000>; mtk-dsp-offload = <0x1d 0xffffffff 0xffffffff \ 0xffffffff 0x400000>; mtk-dsp-deep = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>; mtk-dsp-playback = <0x1 0xa 0xffffffff 0x1b 0x30000>; mtk-dsp-music = <0x1 0xffffffff 0xffffffff 0xffffffff 0x0>; mtk-dsp-capture1 = <0x1 0xffffffff 0xf 0x1a 0x20000>; mtk-dsp-a2dp = <0x1 0xffffffff 0xffffffff 0xffffffff 0x40000>; mtk-dsp-bledl = <0x1 0xffffffff 0xffffffff 0xffffffff 0x30000>; mtk-dsp-dataprovider = <0x0 0xffffffff 0x11 0xffffffff 0x30000>; mtk-dsp-call-final = <0x5 0xa 0x12 0x1b 0x18000>; mtk-dsp-fast = <0x5 0xffffffff 0xffffffff 0xffffffff 0x5000>; mtk-dsp-spatializer = <0x1f 0xffffffff 0xffffffff 0xffffffff 0x5000>; mtk-dsp-ktv = <0x1 0x8 0x14 0xffffffff 0x10000>; mtk-dsp-capture-raw = <0x1 0xffffffff 0xffffffff 0xffffffff 0x20000>; mtk-dsp-fm = <0x0 0xffffffff 0x12 0xffffffff 0x10000>; mtk-dsp-bleul = <0x0 0xffffffff 0xffffffff 0xffffffff 0x20000>; mtk-dsp-ulproc = <0x1 0xffffffff 0xffffffff 0xffffffff 0x20000>; mtk-dsp-echoref = <0x1 0xffffffff 0x1a 0xffffffff 0x20000>; mtk-dsp-echodl = <0x1 0x6 0xffffffff 0xffffffff 0x30000>; mtk-dsp-usbdl = <0x1 0xffffffff 0xffffffff 0xffffffff 0x30000>; mtk-dsp-usbul = <0x1 0xffffffff 0xffffffff 0xffffffff 0x30000>; mtk-dsp-a2dp-irq = <0x1>; mtk-dsp-ver = <0x1>; swdsp-smartpa-process-enable = <0x5>; mtk-dsp-mem-afe = <0x1 0x40000>; mtk-dsp-btdl = <0x1 0xb 0xffffffff 0xffffffff 0x30000>; mtk-dsp-btul = <0x1 0xffffffff 0x19 0x1a 0x20000>; }; mt_soc_offload_common { compatible = "mediatek,mt_soc_offload_common"; }; speech_usip_mem: speech-usip-mem { compatible = "mediatek,speech-usip-mem"; adsp-phone-call-enh-enable = <0x3>; adsp-ble-phone-call-enable = <0x0>; }; rt-pd-manager { compatible = "mediatek,rt-pd-manager"; /* wd0_enable : use it for enable wd0 function */ //wd0_enable; }; pd_adapter: pd_adapter { compatible = "mediatek,pd_adapter"; boot_mode = <&chosen>; adapter_name = "pd_adapter"; force_cv; phys = <&u2port0 PHY_TYPE_USB2>; phy-names = "usb2-phy"; }; flashlight_core: flashlight-core { compatible = "mediatek,flashlight_core"; }; mtk_composite_v4l2_1: mtk-composite-v4l2-1 { compatible = "mediatek,mtk_composite_v4l2_1"; }; mtk_composite_v4l2_2: mtk-composite-v4l2-2 { compatible = "mediatek,mtk_composite_v4l2_2"; }; mtk_ctd: mtk_ctd { compatible = "mediatek,mtk_ctd"; bc12 = <&mt6375_chg>; bc12_sel = <0>; }; low_battery_throttling { compatible = "mediatek,low_battery_throttling"; hv-thd-volt = <3500>; lv1-thd-volt = <3450>; lv2-thd-volt = <3300>; lvsys-thd-enable = <0>; vbat-thd-enable = <1>; }; pbm: pbm { compatible = "mediatek,pbm"; }; mdpm: mdpm { compatible = "mediatek,mt6985-mdpm"; }; cpu_power_throttling: cpu_power_throttling { compatible = "mediatek,cpu-power-throttling"; lbat_cpu_limit = <900000 900000 1300000>; oc_cpu_limit = <900000 900000 1300000>; }; ppc: ppc { compatible = "mediatek,mt6985-ppc"; nvmem-cells = <&efuse_segment>; nvmem-cell-names = "ppc_segment"; }; md_power_throttling: md_power_throttling { compatible = "mediatek,md-power-throttling"; lbat_md_reduce_tx = <6>; oc_md_reduce_tx = <6>; }; bp_thl: bp_thl { compatible = "mediatek,mtk-bp-thl"; soc_limit = <15>; soc_limit_ext = <20>; soc_limit_ext_release = <25>; }; lk_charger: lk_charger { compatible = "mediatek,lk_charger"; enable_anime; /* enable_pe_plus; */ enable_pd20_reset; power_path_support; max_charger_voltage = <6500000>; fast_charge_voltage = <3000000>; /* charging current */ usb_charger_current = <500000>; ac_charger_current = <2050000>; ac_charger_input_current = <3200000>; non_std_ac_charger_current = <500000>; charging_host_charger_current = <1500000>; ta_ac_charger_current = <3000000>; pd_charger_current = <500000>; /* battery temperature protection */ temp_t4_threshold = <50>; temp_t3_threshold = <45>; temp_t1_threshold = <0>; /* enable check vsys voltage */ enable_check_vsys; }; pe: pe { compatible = "mediatek,charger,pe"; gauge = <&mtk_gauge>; ta_12v_support; ta_9v_support; pe_ichg_level_threshold = <1000000>; /* uA */ ta_start_battery_soc = <0>; ta_stop_battery_soc = <85>; min_charger_voltage = <4600000>; ta_ac_12v_input_current = <3200000>; ta_ac_9v_input_current = <3200000>; ta_ac_7v_input_current = <3200000>; pe_charger_current = <3000000>; vbat_threshold = <4150>; }; pe2: pe2 { compatible = "mediatek,charger,pe2"; gauge = <&mtk_gauge>; /* PE 2.0 */ pe20_ichg_level_threshold = <1000000>; /* uA */ ta_start_battery_soc = <0>; ta_stop_battery_soc = <85>; min_charger_voltage = <4600000>; /* cable measurement impedance */ cable_imp_threshold = <699>; vbat_cable_imp_threshold = <3900000>; /* uV */ /* single charger */ sc_input_current = <3200000>; sc_charger_current = <3000000>; /* dual charger in series*/ dcs_input_current = <3200000>; dcs_chg1_charger_current = <1500000>; dcs_chg2_charger_current = <1500000>; dual_polling_ieoc = <450000>; slave_mivr_diff = <100000>; vbat_threshold = <4150>; }; pdc: pdc { compatible = "mediatek,charger,pd"; gauge = <&mtk_gauge>; min-charger-voltage = <4600000>; pd-vbus-low-bound = <5000000>; pd-vbus-upper-bound = <5000000>; vsys-watt = <5000000>; ibus-err = <14>; pd-stop-battery-soc = <80>; /* single charger */ sc-input-current = <3200000>; sc-charger-current = <3000000>; /* dual charger in series*/ dcs-input-current = <3200000>; dcs-chg1-charger-current = <1500000>; dcs-chg2-charger-current = <1500000>; /* dual charger */ dual-polling-ieoc = <450000>; slave-mivr-diff = <100000>; vbat-threshold = <4150>; /* rcable */ enable-inductor-protect = <1>; }; pe45: pe45 { compatible = "mediatek,charger,pe45"; gauge = <&mtk_gauge>; min-charger-voltage = <4600000>; pe45-stop-battery-soc = <80>; high-temp-to-leave-pe45 = <46>; high-temp-to-enter-pe45 = <39>; low-temp-to-leave-pe45 = <10>; low-temp-to-enter-pe45 = <16>; ibus-err = <14>; /* PE 4.5 cable impedance (mohm) */ pe45-r-cable-1a-lower = <500>; pe45-r-cable-2a-lower = <351>; pe45-r-cable-3a-lower = <240>; pe45-r-cable-level = <200 300 400 500 500>; pe45-r-cable-voltage = <5000 5500 6000 6500 7000>; pe45-r-cable-current-limit = <3000 3000 3000 2500 2200>; /* single charger */ sc-input-current = <3200000>; sc-charger-current = <3000000>; /* dual charger in series*/ dcs-input-current = <3200000>; dcs-chg1-charger-current = <1500000>; dcs-chg2-charger-current = <1500000>; dual-polling-ieoc = <450000>; slave-mivr-diff = <100000>; vbat-threshold = <4150>; }; pe5: pe5 { compatible = "mediatek,charger,pe5"; gauge = <&mtk_gauge>; polling_interval = <10000>; ta_cv_ss_repeat_tmin = <25>; vbat_cv = <4350>; start_soc_min = <0>; start_soc_max = <80>; start_vbat_max = <4300>; idvchg_term = <500>; idvchg_step = <50>; ita_level = <3000 2500 2000 1500>; rcable_level = <250 300 375 500>; ita_level_dual = <5000 3700 3400 3000>; rcable_level_dual = <230 350 450 550>; idvchg_ss_init = <1000>; idvchg_ss_step = <250>; idvchg_ss_step1 = <100>; idvchg_ss_step2 = <50>; idvchg_ss_step1_vbat = <4000>; idvchg_ss_step2_vbat = <4200>; ta_blanking = <400>; swchg_aicr = <0>; swchg_ichg = <1200>; swchg_aicr_ss_init = <400>; swchg_aicr_ss_step = <200>; swchg_off_vbat = <4250>; force_ta_cv_vbat = <4250>; chg_time_max = <5400>; tta_level_def = <0 0 0 0 25 50 60 70 80>; tta_curlmt = <0 0 0 0 0 300 600 900 (-1)>; tta_recovery_area = <3>; tbat_level_def = <0 0 0 5 25 40 43 46 50>; tbat_curlmt = <(-1) (-1) (-1) 300 0 600 900 1050 (-1)>; tbat_recovery_area = <3>; tdvchg_level_def = <0 0 0 5 25 55 60 65 70>; tdvchg_curlmt = <(-1) (-1) (-1) 300 0 300 600 900 (-1)>; tdvchg_recovery_area = <3>; tswchg_level_def = <0 0 0 5 25 65 70 75 80>; tswchg_curlmt = <(-1) (-1) (-1) 200 0 200 300 400 (-1)>; tswchg_recovery_area = <3>; ifod_threshold = <200>; rsw_min = <20>; ircmp_rbat = <40>; ircmp_vclamp = <0>; vta_cap_min = <6800>; vta_cap_max = <11000>; ita_cap_min = <1000>; support_ta = "pca_ta_pps", "pd_adapter"; allow_not_check_ta_status; vbat_threshold = <4150>; }; pe5p: pe5p { compatible = "mediatek,charger,pe5p"; gauge = <&mtk_gauge>; polling_interval = <10000>; ta_cv_ss_repeat_tmin = <25>; vbat_cv = <8900>; start_soc_min = <0>; start_soc_max = <80>; start_vbat_min = <7100>; start_vbat_max = <8750>; idvchg_term = <250>; idvchg_step = <50>; ita_level = <5000 4500 3750 3000>; rcable_level = <250 300 375 500>; ita_level_dual = <5000 4500 3750 3000>; rcable_level_dual = <230 350 450 550>; idvchg_ss_init = <500>; idvchg_ss_step = <250>; idvchg_ss_step1 = <100>; idvchg_ss_step2 = <50>; idvchg_ss_step1_vbat = <8000>; idvchg_ss_step2_vbat = <8100>; ta_blanking = <500>; swchg_aicr = <0>; swchg_ichg = <0>; swchg_aicr_ss_init = <400>; swchg_aicr_ss_step = <200>; swchg_off_vbat = <8200>; force_ta_cv_vbat = <8200>; chg_time_max = <5400>; tta_level_def = <0 0 0 0 25 40 50 60 70>; /* tta_curlmt = <0 0 0 0 0 300 600 900 (-1)>; */ tta_curlmt = <0 0 0 0 0 0 600 900 (-1)>; tta_recovery_area = <3>; tbat_level_def = <0 0 0 5 25 40 43 46 50>; tbat_curlmt = <(-1) (-1) (-1) 300 0 600 900 1050 (-1)>; tbat_recovery_area = <3>; tdvchg_level_def = <0 0 0 5 25 55 60 65 70>; tdvchg_curlmt = <(-1) (-1) (-1) 300 0 300 600 900 (-1)>; tdvchg_recovery_area = <3>; tswchg_level_def = <0 0 0 5 25 65 70 75 80>; tswchg_curlmt = <(-1) (-1) (-1) 200 0 200 300 400 (-1)>; tswchg_recovery_area = <3>; ifod_threshold = <200>; rsw_min = <20>; ircmp_rbat = <40>; ircmp_vclamp = <0>; vta_cap_min = <14000>; vta_cap_max = <20000>; ita_cap_min = <1000>; support_ta = "pca_ta_pps", "pd_adapter"; allow_not_check_ta_status; vbat_threshold = <8200>; }; hvbp: hvbp { compatible = "mediatek,charger,hvbp"; gauge = <&mtk_gauge>; polling_interval = <10000>; ta_cv_ss_repeat_tmin = <25>; vbat_cv = <8900>; start_soc_min = <1>; start_soc_max = <80>; start_vbat_min = <7100>; start_vbat_max = <8750>; idvchg_term = <500>; idvchg_step = <50>; ita_level = <2500 2300 2150 2000>; rcable_level = <250 300 375 500>; /* ita_level_dual = <5000 4500 3750 3000>; */ ita_level_dual = <3000 2500 1750 1000>; rcable_level_dual = <230 350 450 550>; idvchg_ss_init = <500>; idvchg_ss_step = <250>; idvchg_ss_step1 = <100>; idvchg_ss_step2 = <50>; idvchg_ss_step1_vbat = <8000>; idvchg_ss_step2_vbat = <8100>; ta_blanking = <500>; swchg_aicr = <0>; swchg_ichg = <0>; swchg_aicr_ss_init = <400>; swchg_aicr_ss_step = <200>; swchg_off_vbat = <8200>; force_ta_cv_vbat = <8200>; chg_time_max = <5400>; tta_level_def = <0 0 0 0 25 40 50 60 70>; /* tta_curlmt = <0 0 0 0 0 300 600 900 (-1)>; */ tta_curlmt = <0 0 0 0 0 0 600 900 (-1)>; tta_recovery_area = <3>; tbat_level_def = <0 0 0 5 25 40 43 46 50>; tbat_curlmt = <(-1) (-1) (-1) 300 0 600 900 1050 (-1)>; tbat_recovery_area = <3>; tdvchg_level_def = <0 0 0 5 25 55 60 65 70>; tdvchg_curlmt = <(-1) (-1) (-1) 300 0 300 600 900 (-1)>; tdvchg_recovery_area = <3>; tswchg_level_def = <0 0 0 5 25 65 70 75 80>; tswchg_curlmt = <(-1) (-1) (-1) 200 0 200 300 400 (-1)>; tswchg_recovery_area = <3>; ifod_threshold = <200>; rsw_min = <20>; ircmp_rbat = <40>; ircmp_vclamp = <0>; vta_cap_min = <50000>; vta_cap_max = <11000>; ita_cap_min = <1000>; support_ta = "pca_ta_pps", "pd_adapter"; allow_not_check_ta_status; vbat_threshold = <8200>; }; charger: charger { compatible = "mediatek,charger"; gauge = <&mtk_gauge>; charger = <&mt6375_chg>; bc12_psy = <&mt6375_chg>; bootmode = <&chosen>; algorithm_name = "Basic"; charger_configuration= <0>; alg_new_arbitration; /* common */ battery_cv = <4350000>; max_charger_voltage = <6500000>; vbus_sw_ovp_voltage = <15000000>; min_charger_voltage = <4600000>; /* sw jeita */ enable_vbat_mon = <1>; /* enable_sw_jeita; */ jeita_temp_above_t4_cv = <4240000>; jeita_temp_t3_to_t4_cv = <4240000>; jeita_temp_t2_to_t3_cv = <4340000>; jeita_temp_t1_to_t2_cv = <4240000>; jeita_temp_t0_to_t1_cv = <4040000>; jeita_temp_below_t0_cv = <4040000>; temp_t4_thres = <50>; temp_t4_thres_minus_x_degree = <47>; temp_t3_thres = <45>; temp_t3_thres_minus_x_degree = <39>; temp_t2_thres = <10>; temp_t2_thres_plus_x_degree = <16>; temp_t1_thres = <0>; temp_t1_thres_plus_x_degree = <6>; temp_t0_thres = <0>; temp_t0_thres_plus_x_degree = <0>; temp_neg_10_thres = <0>; /* battery temperature protection */ enable_min_charge_temp; min_charge_temp = <0>; min_charge_temp_plus_x_degree = <6>; max_charge_temp = <50>; max_charge_temp_minus_x_degree = <47>; /* charging current */ usb_charger_current = <500000>; ac_charger_current = <2050000>; ac_charger_input_current = <3200000>; charging_host_charger_current = <1500000>; /* dynamic mivr */ enable_dynamic_mivr; min_charger_voltage_1 = <4400000>; min_charger_voltage_2 = <4200000>; max_dmivr_charger_current = <1800000>; /* fast charging algo support indicator */ enable_fast_charging_indicator; }; logstore: logstore { enabled = <1>; pmic-register = <0xa0d>; }; seninf_top: seninf_top@1a00e000 { compatible = "mediatek,seninf-core"; reg = <0 0x1a00e000 0 0x18000>, <0 0x11c80000 0 0x20000>; reg-names = "base", "ana-rx"; interrupts = ; seninf_num = <12>; mux_num = <22>; cam_mux_num = <41>; mux-camsv-sat_range = <0 3>; mux-camsv-normal_range = <4 5>; mux-raw_range = <6 17>; mux-uisp_range = <6 17>; mux-pdp_range = <18 21>; cammux-camsv-sat_range = <0 31>; cammux-camsv-normal_range = <32 33>; cammux-raw_range = <34 36>; cammux-uisp_range = <34 36>; cammux-pdp_range = <37 40>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>, <&scpsys MT6985_POWER_DOMAIN_CSI_RX>; clocks = <&camsys_main_clk CLK_CAM_MAIN_SENINF_CON_0>, <&topckgen_clk CLK_TOP_SENINF_SEL>, <&topckgen_clk CLK_TOP_SENINF1_SEL>, <&topckgen_clk CLK_TOP_SENINF2_SEL>, <&topckgen_clk CLK_TOP_SENINF3_SEL>, <&topckgen_clk CLK_TOP_SENINF4_SEL>, <&topckgen_clk CLK_TOP_SENINF5_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>, <&topckgen_clk CLK_TOP_OSC_D4>, <&topckgen_clk CLK_TOP_MAINPLL2_D9>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_OSC_D20>, <&topckgen_clk CLK_TOP_TCK_26M_MX9>; clock-names = "clk_cam_seninf", "clk_top_seninf", "clk_top_seninf1", "clk_top_seninf2", "clk_top_seninf3", "clk_top_seninf4", "clk_top_seninf5", "clk_top_camtm", "clk_top_osc_d4", "clk_top_mainpll2_d9", "clk_top_camtg", "clk_top_osc_d20", "clk_top_tck_26m_mx9"; }; camisp: camisp@1a000000 { compatible = "mediatek,mt6985-camisp"; reg = <0 0x1a000000 0 0x1000>; reg-names = "base"; mediatek,ccd = <&remoteproc_ccd>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; interrupts = , ; operating-points-v2 = <&opp_table_cam>; mboxes = <&gce_m 24 0 CMDQ_THR_PRIO_1>; clocks = <&mmdvfs_clk CLK_MMDVFS_CAM>; clock-names = "mmdvfs_clk"; vmm-pmic-supply = <&mt6319_6_vbuck3>; }; cam_raw_a@1a030000 { compatible = "mediatek,cam-raw"; reg = <0 0x1a030000 0 0x8000>, <0 0x1a038000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,cam-id = <0>; mediatek,larbs = <&smi_larb16>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_ADLRD_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_ADLWR_CON_0>, <&camsys_rawa_clk CLK_CAM_RA_LARBX>, <&camsys_rawa_clk CLK_CAM_RA_CAM>, <&camsys_rawa_clk CLK_CAM_RA_CAMTG>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "camsys_cam_cgpdn", "camsys_camtg_cgpdn", "camsys_rawa_larbx_cgpdn", "camsys_rawa_cam_cgpdn", "camsys_rawa_camtg_cgpdn", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; iommus = <&disp_iommu M4U_PORT_L16_CQI_R1>, <&disp_iommu M4U_PORT_L16_RAWI_R2>, <&disp_iommu M4U_PORT_L16_RAWI_R3>, <&disp_iommu M4U_PORT_L16_RAWI_R5>, <&disp_iommu M4U_PORT_L16_IMGO_R1>, <&disp_iommu M4U_PORT_L16_BPCI_R1>, <&disp_iommu M4U_PORT_L16_LCSI_R1>, <&disp_iommu M4U_PORT_L16_UFEO_R1>, <&disp_iommu M4U_PORT_L16_LTMSO_R1>, <&disp_iommu M4U_PORT_L16_DRZB2NO_R1>, <&disp_iommu M4U_PORT_L16_AAO_R1>, <&disp_iommu M4U_PORT_L16_AFO_R1>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_CQI_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R3) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_RAWI_R5) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_IMGO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_BPCI_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_LCSI_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_UFEO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_LTMSO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_DRZB2NO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_AAO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L16_AFO_R1) &mmqos SLAVE_COMMON(0)>; interconnect-names = "cqi_r1", "rawi_r2", "rawi_r3", "rawi_r5", "imgo_r1", "bpci_r1", "lsci_r1", "ufeo_r1", "ltmso_r1", "drzb2no_r1", "aao_r1", "afo_r1"; }; cam_yuv_a@1a050000 { compatible = "mediatek,cam-yuv"; reg = <0 0x1a050000 0 0x8000>, <0 0x1a058000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,cam-id = <0>; mediatek,larbs = <&smi_larb17>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_yuva_clk CLK_CAM_YA_LARBX>, <&camsys_yuva_clk CLK_CAM_YA_CAM>, <&camsys_yuva_clk CLK_CAM_YA_CAMTG>; clock-names = "camsys_yuva_larbx_cgpdn", "camsys_yuva_cam_cgpdn", "camsys_yuva_camtg_cgpdn"; iommus = <&mdp_iommu M4U_PORT_L17_YUVO_R1>, <&mdp_iommu M4U_PORT_L17_YUVO_R3>, <&mdp_iommu M4U_PORT_L17_YUVO_R2>, <&mdp_iommu M4U_PORT_L17_YUVO_R5>, <&mdp_iommu M4U_PORT_L17_RGBWI_R1>, <&mdp_iommu M4U_PORT_L17_TCYSO_R1>, <&mdp_iommu M4U_PORT_L17_DRZ4NO_R3>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R3) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R2) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L17_YUVO_R5) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L17_RGBWI_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L17_TCYSO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L17_DRZ4NO_R3) &mmqos SLAVE_COMMON(1)>; interconnect-names = "yuvo_r1", "yuvo_r3", "yuvo_r2", "yuvo_r5", "rgbwi_r1", "tcyso_r1", "drz4no_r3"; }; cam_raw_b@1a070000 { compatible = "mediatek,cam-raw"; reg = <0 0x1a070000 0 0x8000>, <0 0x1a078000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,cam-id = <1>; mediatek,larbs = <&smi_larb30>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_ADLRD_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_ADLWR_CON_0>, <&camsys_rawb_clk CLK_CAM_RB_LARBX>, <&camsys_rawb_clk CLK_CAM_RB_CAM>, <&camsys_rawb_clk CLK_CAM_RB_CAMTG>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "camsys_cam_cgpdn", "camsys_camtg_cgpdn", "camsys_rawb_larbx_cgpdn", "camsys_rawb_cam_cgpdn", "camsys_rawb_camtg_cgpdn", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; iommus = <&mdp_iommu M4U_PORT_L30_CQI_R1>, <&mdp_iommu M4U_PORT_L30_RAWI_R2>, <&mdp_iommu M4U_PORT_L30_RAWI_R3>, <&mdp_iommu M4U_PORT_L30_RAWI_R5>, <&mdp_iommu M4U_PORT_L30_IMGO_R1>, <&mdp_iommu M4U_PORT_L30_BPCI_R1>, <&mdp_iommu M4U_PORT_L30_LCSI_R1>, <&mdp_iommu M4U_PORT_L30_UFEO_R1>, <&mdp_iommu M4U_PORT_L30_LTMSO_R1>, <&mdp_iommu M4U_PORT_L30_DRZB2NO_R1>, <&mdp_iommu M4U_PORT_L30_AAO_R1>, <&mdp_iommu M4U_PORT_L30_AFO_R1>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_CQI_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R2) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R3) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_RAWI_R5) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_IMGO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_BPCI_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_LCSI_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_UFEO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_LTMSO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_DRZB2NO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_AAO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L30_AFO_R1) &mmqos SLAVE_COMMON(1)>; interconnect-names = "cqi_r1", "rawi_r2", "rawi_r3", "rawi_r5", "imgo_r1", "bpci_r1", "lsci_r1", "ufeo_r1", "ltmso_r1", "drzb2no_r1", "aao_r1", "afo_r1"; }; cam_yuv_b@1a090000 { compatible = "mediatek,cam-yuv"; reg = <0 0x1a090000 0 0x8000>, <0 0x1a098000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,cam-id = <1>; mediatek,larbs = <&smi_larb34>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_yuvb_clk CLK_CAM_YB_LARBX>, <&camsys_yuvb_clk CLK_CAM_YB_CAM>, <&camsys_yuvb_clk CLK_CAM_YB_CAMTG>; clock-names = "camsys_yuvb_larbx_cgpdn", "camsys_yuvb_cam_cgpdn", "camsys_yuvb_camtg_cgpdn"; iommus = <&disp_iommu M4U_PORT_L34_YUVO_R1>, <&disp_iommu M4U_PORT_L34_YUVO_R3>, <&disp_iommu M4U_PORT_L34_YUVO_R2>, <&disp_iommu M4U_PORT_L34_YUVO_R5>, <&disp_iommu M4U_PORT_L34_RGBWI_R1>, <&disp_iommu M4U_PORT_L34_TCYSO_R1>, <&disp_iommu M4U_PORT_L34_DRZ4NO_R3>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R3) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L34_YUVO_R5) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L34_RGBWI_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L34_TCYSO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L34_DRZ4NO_R3) &mmqos SLAVE_COMMON(0)>; interconnect-names = "yuvo_r1", "yuvo_r3", "yuvo_r2", "yuvo_r5", "rgbwi_r1", "tcyso_r1", "drz4no_r3"; }; cam_raw_c@1a0b0000 { compatible = "mediatek,cam-raw"; reg = <0 0x1a0b0000 0 0x8000>, <0 0x1a0b8000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,cam-id = <2>; mediatek,larbs = <&smi_larb31>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_ADLRD_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_ADLWR_CON_0>, <&camsys_rawc_clk CLK_CAM_RC_LARBX>, <&camsys_rawc_clk CLK_CAM_RC_CAM>, <&camsys_rawc_clk CLK_CAM_RC_CAMTG>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "camsys_cam_cgpdn", "camsys_camtg_cgpdn", "camsys_rawc_larbx_cgpdn", "camsys_rawc_cam_cgpdn", "camsys_rawc_camtg_cgpdn", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; iommus = <&disp_iommu M4U_PORT_L31_CQI_R1>, <&disp_iommu M4U_PORT_L31_RAWI_R2>, <&disp_iommu M4U_PORT_L31_RAWI_R3>, <&disp_iommu M4U_PORT_L31_RAWI_R5>, <&disp_iommu M4U_PORT_L31_IMGO_R1>, <&disp_iommu M4U_PORT_L31_BPCI_R1>, <&disp_iommu M4U_PORT_L31_LCSI_R1>, <&disp_iommu M4U_PORT_L31_UFEO_R1>, <&disp_iommu M4U_PORT_L31_LTMSO_R1>, <&disp_iommu M4U_PORT_L31_DRZB2NO_R1>, <&disp_iommu M4U_PORT_L31_AAO_R1>, <&disp_iommu M4U_PORT_L31_AFO_R1>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_CQI_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_RAWI_R2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_RAWI_R3) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_RAWI_R5) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_IMGO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_BPCI_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_LCSI_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_UFEO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_LTMSO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_DRZB2NO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_AAO_R1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L31_AFO_R1) &mmqos SLAVE_COMMON(0)>; interconnect-names = "cqi_r1", "rawi_r2", "rawi_r3", "rawi_r5", "imgo_r1", "bpci_r1", "lsci_r1", "ufeo_r1", "ltmso_r1", "drzb2no_r1", "aao_r1", "afo_r1"; }; cam_yuv_c@1a0d0000 { compatible = "mediatek,cam-yuv"; reg = <0 0x1a0d0000 0 0x8000>, <0 0x1a0d8000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,cam-id = <2>; mediatek,larbs = <&smi_larb35>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_yuvc_clk CLK_CAM_YC_LARBX>, <&camsys_yuvc_clk CLK_CAM_YC_CAM>, <&camsys_yuvc_clk CLK_CAM_YC_CAMTG>; clock-names = "camsys_yuvc_larbx_cgpdn", "camsys_yuvc_cam_cgpdn", "camsys_yuvc_camtg_cgpdn"; iommus = <&mdp_iommu M4U_PORT_L35_YUVO_R1>, <&mdp_iommu M4U_PORT_L35_YUVO_R3>, <&mdp_iommu M4U_PORT_L35_YUVO_R2>, <&mdp_iommu M4U_PORT_L35_YUVO_R5>, <&mdp_iommu M4U_PORT_L35_RGBWI_R1>, <&mdp_iommu M4U_PORT_L35_TCYSO_R1>, <&mdp_iommu M4U_PORT_L35_DRZ4NO_R3>; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R3) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R2) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L35_YUVO_R5) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L35_RGBWI_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L35_TCYSO_R1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L35_DRZ4NO_R3) &mmqos SLAVE_COMMON(1)>; interconnect-names = "yuvo_r1", "yuvo_r3", "yuvo_r2", "yuvo_r5", "rgbwi_r1", "tcyso_r1", "drz4no_r3"; }; camsv1@1a100000 { compatible = "mediatek,camsv"; reg = <0 0x1a100000 0 0x1000>, <0 0x1a110000 0 0x1000>, <0 0x1a120000 0 0x1000>, <0 0x1a108000 0 0x1000>, <0 0x1a118000 0 0x1000>, <0 0x1a128000 0 0x1000>; reg-names = "base", "base_DMA", "base_SCQ", "inner_base", "inner_base_DMA", "inner_base_SCQ"; mediatek,camsv-id = <0>; mediatek,cammux-id = <0>; mediatek,larbs = <&smi_larb14>; interrupts = , , , ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L14_CQI_0>, <&mdp_iommu M4U_PORT_L14_CAMSV_0_WDMA>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB14_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_A_CON_1>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_larb14_con", "cam_main_cam_con", "cam_main_camtg_con", "cam_main_camsv_top_con", "cam_main_camsv_a_con", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L14_CQI_0) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L14_CAMSV_0_WDMA) &mmqos SLAVE_COMMON(1)>; interconnect-names = "l14_cqi_a", "l14_imgo_a"; }; camsv2@1a101000 { compatible = "mediatek,camsv"; reg = <0 0x1a101000 0 0x1000>, <0 0x1a111000 0 0x1000>, <0 0x1a121000 0 0x1000>, <0 0x1a109000 0 0x1000>, <0 0x1a119000 0 0x1000>, <0 0x1a129000 0 0x1000>; reg-names = "base", "base_DMA", "base_SCQ", "inner_base", "inner_base_DMA", "inner_base_SCQ"; mediatek,camsv-id = <1>; mediatek,cammux-id = <8>; mediatek,larbs = <&smi_larb13>; interrupts = , , , ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L13_CQI_1>, <&disp_iommu M4U_PORT_L13_CAMSV_1_WDMA>, <&disp_iommu M4U_PORT_L13_FAKE_ENG>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB13_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_B_CON_1>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_larb13_con", "cam_main_cam_con", "cam_main_camtg_con", "cam_main_camsv_top_con", "cam_main_camsv_b_con", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CQI_1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L13_CAMSV_1_WDMA) &mmqos SLAVE_COMMON(1)>; interconnect-names = "l13_cqi_b", "l13_imgo_b"; }; camsv3@1a102000 { compatible = "mediatek,camsv"; reg = <0 0x1a102000 0 0x1000>, <0 0x1a112000 0 0x1000>, <0 0x1a122000 0 0x1000>, <0 0x1a10a000 0 0x1000>, <0 0x1a11a000 0 0x1000>, <0 0x1a12a000 0 0x1000>; reg-names = "base", "base_DMA", "base_SCQ", "inner_base", "inner_base_DMA", "inner_base_SCQ"; mediatek,camsv-id = <2>; mediatek,cammux-id = <16>; mediatek,larbs = <&smi_larb29>; interrupts = , , , ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L29_CQI_2>, <&disp_iommu M4U_PORT_L29_CQI_3>, <&disp_iommu M4U_PORT_L29_CQI_4>, <&disp_iommu M4U_PORT_L29_CQI_5>, <&disp_iommu M4U_PORT_L29_CAMSV_2_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_3_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_4_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_5_WDMA>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_C_CON_1>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_larb29_con", "cam_main_cam_con", "cam_main_camtg_con", "cam_main_camsv_top_con", "cam_main_camsv_c_con", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CQI_2) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_2_WDMA) &mmqos SLAVE_COMMON(0)>; interconnect-names = "l29_cqi_c", "l29_imgo_c"; }; camsv4@1a103000 { compatible = "mediatek,camsv"; reg = <0 0x1a103000 0 0x1000>, <0 0x1a113000 0 0x1000>, <0 0x1a123000 0 0x1000>, <0 0x1a10b000 0 0x1000>, <0 0x1a11b000 0 0x1000>, <0 0x1a12b000 0 0x1000>; reg-names = "base", "base_DMA", "base_SCQ", "inner_base", "inner_base_DMA", "inner_base_SCQ"; mediatek,camsv-id = <3>; mediatek,cammux-id = <24>; mediatek,larbs = <&smi_larb29>; interrupts = , , , ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L29_CQI_2>, <&disp_iommu M4U_PORT_L29_CQI_3>, <&disp_iommu M4U_PORT_L29_CQI_4>, <&disp_iommu M4U_PORT_L29_CQI_5>, <&disp_iommu M4U_PORT_L29_CAMSV_2_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_3_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_4_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_5_WDMA>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_D_CON_1>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_larb29_con", "cam_main_cam_con", "cam_main_camtg_con", "cam_main_camsv_top_con", "cam_main_camsv_d_con", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CQI_3) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_3_WDMA) &mmqos SLAVE_COMMON(0)>; interconnect-names = "l29_cqi_d", "l29_imgo_d"; }; camsv5@1a104000 { compatible = "mediatek,camsv"; reg = <0 0x1a104000 0 0x1000>, <0 0x1a114000 0 0x1000>, <0 0x1a124000 0 0x1000>, <0 0x1a10c000 0 0x1000>, <0 0x1a11c000 0 0x1000>, <0 0x1a12c000 0 0x1000>; reg-names = "base", "base_DMA", "base_SCQ", "inner_base", "inner_base_DMA", "inner_base_SCQ"; mediatek,camsv-id = <4>; mediatek,cammux-id = <32>; mediatek,larbs = <&smi_larb29>; interrupts = , , , ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L29_CQI_2>, <&disp_iommu M4U_PORT_L29_CQI_3>, <&disp_iommu M4U_PORT_L29_CQI_4>, <&disp_iommu M4U_PORT_L29_CQI_5>, <&disp_iommu M4U_PORT_L29_CAMSV_2_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_3_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_4_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_5_WDMA>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_E_CON_1>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_larb29_con", "cam_main_cam_con", "cam_main_camtg_con", "cam_main_camsv_top_con", "cam_main_camsv_e_con", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CQI_4) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_4_WDMA) &mmqos SLAVE_COMMON(0)>; interconnect-names = "l29_cqi_e", "l29_imgo_e"; }; camsv6@1a105000 { compatible = "mediatek,camsv"; reg = <0 0x1a105000 0 0x1000>, <0 0x1a115000 0 0x1000>, <0 0x1a125000 0 0x1000>, <0 0x1a10d000 0 0x1000>, <0 0x1a11d000 0 0x1000>, <0 0x1a12d000 0 0x1000>; reg-names = "base", "base_DMA", "base_SCQ", "inner_base", "inner_base_DMA", "inner_base_SCQ"; mediatek,camsv-id = <5>; mediatek,cammux-id = <33>; mediatek,larbs = <&smi_larb29>; interrupts = , , , ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L29_CQI_2>, <&disp_iommu M4U_PORT_L29_CQI_3>, <&disp_iommu M4U_PORT_L29_CQI_4>, <&disp_iommu M4U_PORT_L29_CQI_5>, <&disp_iommu M4U_PORT_L29_CAMSV_2_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_3_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_4_WDMA>, <&disp_iommu M4U_PORT_L29_CAMSV_5_WDMA>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys_main_clk CLK_CAM_MAIN_LARB29_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAM_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMTG_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_TOP_CON_0>, <&camsys_main_clk CLK_CAM_MAIN_CAMSV_CON_1>, <&topckgen_clk CLK_TOP_CAM_SEL>, <&topckgen_clk CLK_TOP_CAMTG_SEL>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_larb29_con", "cam_main_cam_con", "cam_main_camtg_con", "cam_main_camsv_top_con", "cam_main_camsv_f_con", "topckgen_top_cam_sel", "topckgen_top_camtg_sel", "topckgen_top_camtm_sel"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CQI_5) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L29_CAMSV_5_WDMA) &mmqos SLAVE_COMMON(0)>; interconnect-names = "l29_cqi_f", "l29_imgo_f"; }; mraw1@1a130000 { compatible = "mediatek,mraw"; reg = <0 0x1a130000 0 0x8000>, <0 0x1a138000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,mraw-id = <0>; mediatek,cammux-id = <37>; mediatek,larbs = <&smi_larb25>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L25_MRAW0_CQI_M1>, <&disp_iommu M4U_PORT_L25_MRAW0_IMGBO_M1>, <&disp_iommu M4U_PORT_L25_MRAW2_CQI_M1>, <&disp_iommu M4U_PORT_L25_MRAW2_IMGBO_M1>, <&disp_iommu M4U_PORT_L25_PDAI_A_0>, <&disp_iommu M4U_PORT_L25_PDAI_A_1>, <&disp_iommu M4U_PORT_L25_PDAI_A_2>, <&disp_iommu M4U_PORT_L25_PDAI_A_3>, <&disp_iommu M4U_PORT_L25_PDAI_A_4>, <&disp_iommu M4U_PORT_L25_PDAO_A_0>, <&disp_iommu M4U_PORT_L25_MRAW0_IMGO_M1>, <&disp_iommu M4U_PORT_L25_MRAW2_IMGO_M1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_CAMTG>, <&camsys_mraw_clk CLK_CAM_MR_MRAW0>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_mraw_cg_con", "camsys_mraw_larbx", "camsys_mraw_camtg", "camsys_main_mraw0", "topckgen_top_muxcamtm"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_CQI_M1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGBO_M1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW0_IMGO_M1) &mmqos SLAVE_COMMON(0)>; interconnect-names = "l25_cqi_m1_0", "l25_imgo_m1_0", "l25_imgbo_m1_0"; }; mraw2@1a140000 { compatible = "mediatek,mraw"; reg = <0 0x1a140000 0 0x8000>, <0 0x1a148000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,mraw-id = <1>; mediatek,cammux-id = <38>; mediatek,larbs = <&smi_larb26>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&mdp_iommu M4U_PORT_L26_MRAW1_CQI_M1>, <&mdp_iommu M4U_PORT_L26_MRAW1_IMGBO_M1>, <&mdp_iommu M4U_PORT_L26_MRAW3_CQI_M1>, <&mdp_iommu M4U_PORT_L26_MRAW3_IMGBO_M1>, <&mdp_iommu M4U_PORT_L26_PDAI_B_0>, <&mdp_iommu M4U_PORT_L26_PDAI_B_1>, <&mdp_iommu M4U_PORT_L26_PDAI_B_2>, <&mdp_iommu M4U_PORT_L26_PDAI_B_3>, <&mdp_iommu M4U_PORT_L26_PDAI_B_4>, <&mdp_iommu M4U_PORT_L26_PDAO_B_0>, <&mdp_iommu M4U_PORT_L26_MRAW1_IMGO_M1>, <&mdp_iommu M4U_PORT_L26_MRAW3_IMGO_M1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_CAMTG>, <&camsys_mraw_clk CLK_CAM_MR_MRAW1>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_mraw_cg_con", "camsys_mraw_larbx", "camsys_mraw_camtg", "camsys_main_mraw1", "topckgen_top_muxcamtm"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_CQI_M1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGBO_M1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW1_IMGO_M1) &mmqos SLAVE_COMMON(1)>; interconnect-names = "l26_cqi_m1_1", "l26_imgo_m1_1", "l26_imgbo_m1_1"; }; mraw3@1a150000 { compatible = "mediatek,mraw"; reg = <0 0x1a150000 0 0x8000>, <0 0x1a158000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,mraw-id = <2>; mediatek,cammux-id = <39>; mediatek,larbs = <&smi_larb25>; interrupts = ; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L25_MRAW0_CQI_M1>, <&disp_iommu M4U_PORT_L25_MRAW0_IMGBO_M1>, <&disp_iommu M4U_PORT_L25_MRAW2_CQI_M1>, <&disp_iommu M4U_PORT_L25_MRAW2_IMGBO_M1>, <&disp_iommu M4U_PORT_L25_PDAI_A_0>, <&disp_iommu M4U_PORT_L25_PDAI_A_1>, <&disp_iommu M4U_PORT_L25_PDAI_A_2>, <&disp_iommu M4U_PORT_L25_PDAI_A_3>, <&disp_iommu M4U_PORT_L25_PDAI_A_4>, <&disp_iommu M4U_PORT_L25_PDAO_A_0>, <&disp_iommu M4U_PORT_L25_MRAW0_IMGO_M1>, <&disp_iommu M4U_PORT_L25_MRAW2_IMGO_M1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_CAMTG>, <&camsys_mraw_clk CLK_CAM_MR_MRAW2>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_mraw_cg_con", "camsys_mraw_larbx", "camsys_mraw_camtg", "camsys_main_mraw2", "topckgen_top_muxcamtm"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_CQI_M1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGBO_M1) &mmqos SLAVE_COMMON(0)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L25_MRAW2_IMGO_M1) &mmqos SLAVE_COMMON(0)>; interconnect-names = "l25_cqi_m1_2", "l25_imgo_m1_2", "l25_imgbo_m1_2"; }; mraw4@1a160000 { compatible = "mediatek,mraw"; reg = <0 0x1a160000 0 0x8000>, <0 0x1a168000 0 0x8000>; reg-names = "base", "inner_base"; mediatek,mraw-id = <3>; mediatek,cammux-id = <40>; mediatek,larbs = <&smi_larb26>; interrupts = ; iommus = <&mdp_iommu M4U_PORT_L26_MRAW1_CQI_M1>, <&mdp_iommu M4U_PORT_L26_MRAW1_IMGBO_M1>, <&mdp_iommu M4U_PORT_L26_MRAW3_CQI_M1>, <&mdp_iommu M4U_PORT_L26_MRAW3_IMGBO_M1>, <&mdp_iommu M4U_PORT_L26_PDAI_B_0>, <&mdp_iommu M4U_PORT_L26_PDAI_B_1>, <&mdp_iommu M4U_PORT_L26_PDAI_B_2>, <&mdp_iommu M4U_PORT_L26_PDAI_B_3>, <&mdp_iommu M4U_PORT_L26_PDAI_B_4>, <&mdp_iommu M4U_PORT_L26_PDAO_B_0>, <&mdp_iommu M4U_PORT_L26_MRAW1_IMGO_M1>, <&mdp_iommu M4U_PORT_L26_MRAW3_IMGO_M1>; power-domains = <&scpsys MT6985_POWER_DOMAIN_CAM_MRAW>; clocks = <&camsys_main_clk CLK_CAM_MAIN_CAM_MRAW_CON_0>, <&camsys_mraw_clk CLK_CAM_MR_LARBX>, <&camsys_mraw_clk CLK_CAM_MR_CAMTG>, <&camsys_mraw_clk CLK_CAM_MR_MRAW3>, <&topckgen_clk CLK_TOP_CAMTM_SEL>; clock-names = "cam_main_mraw_cg_con", "camsys_mraw_larbx", "camsys_mraw_camtg", "camsys_main_mraw3", "topckgen_top_muxcamtm"; interconnects = <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_CQI_M1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGBO_M1) &mmqos SLAVE_COMMON(1)>, <&mmqos MASTER_LARB_PORT(M4U_PORT_L26_MRAW3_IMGO_M1) &mmqos SLAVE_COMMON(1)>; interconnect-names = "l26_cqi_m1_3", "l26_imgo_m1_3", "l26_imgbo_m1_3"; }; remoteproc_ccd: remoteproc_ccd@1a030000 { compatible = "mediatek,ccd"; reg = <0 0x1a030000 0 0x10000>; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; iommus = <&disp_iommu M4U_PORT_L16_CQI_R1>, <&disp_iommu M4U_PORT_L16_RAWI_R2>, <&disp_iommu M4U_PORT_L16_RAWI_R3>, <&disp_iommu M4U_PORT_L16_RAWI_R5>, <&disp_iommu M4U_PORT_L16_IMGO_R1>, <&disp_iommu M4U_PORT_L16_BPCI_R1>, <&disp_iommu M4U_PORT_L16_LCSI_R1>, <&disp_iommu M4U_PORT_L16_UFEO_R1>, <&disp_iommu M4U_PORT_L16_LTMSO_R1>, <&disp_iommu M4U_PORT_L16_DRZB2NO_R1>, <&disp_iommu M4U_PORT_L16_AAO_R1>, <&disp_iommu M4U_PORT_L16_AFO_R1>; msg_dev { mtk,rpmsg-name = "mtk_ccd_msgdev"; }; }; met { met_emi: met-emi { compatible = "mediatek,met_emi"; emi-num = <2>; dram-num = <2>; dramc-ver = <2>; /*0: dram ebg, 1:emi_freq, 2: DRAMC_DCM_CTRL 3:chn_emi_low_effi */ met-emi-support-list = <0x13>; cen-emi-reg-base = <0x10219000 0x1021d000>; cen-emi-reg-size = <0x1000>; chn-emi-reg-base = <0x10235000 0x10245000 0x10255000 0x10265000>; chn-emi-reg-size = <0xa90>; dramc-nao-reg-base = <0x10234000 0x10244000 0x10254000 0x10264000>; dramc-nao-reg-size = <0x76c>; dramc-ao-reg-base = <0x10230000 0x10240000 0x10250000 0x10260000>; dramc-ao-reg-size = <0x2000>; ddrphy-ao-reg-base = <0x10238000 0x10248000 0x10258000 0x10268000>; ddrphy-ao-reg-size = <0x1650>; ddrphy-ao-misc-cg-ctrl0 = <0x70c>; ddrphy-ao-misc-cg-ctrl2 = <0x714>; dram-freq-default = <6400>; ddr-ratio-default = <8>; dram-type-default = <8>; apmixedsys-reg-base = <0x1000c000>; apmixedsys-reg-size = <0x410>; slc-pmu-reg-base = <0x10342000 0x10343000>; slc-pmu-reg-size = <0x1000>; }; met-res-ram { compatible = "mediatek,met_res_ram"; met-res-ram-sspm { size = <0x400000>; /* 4M: only reserve on userdebug/eng load */ start = <0x0>; /* start addr of reserved ram*/ }; met-res-ram-mcupm { size = <0x400000>; /* 4M: only reserve on userdebug/eng load */ start = <0x0>; /* start addr of reserved ram*/ }; met-res-ram-gpueb { size = <0x400000>; /* 4M: only reserve on userdebug/eng load */ start = <0x0>; /* start addr of reserved ram*/ }; }; mcupm_rts_header:mcupm-rts-header { node-0 = "MCUPM_MET_UNIT_TEST", "test"; node-1 = "__MCUPM_MET_L3CTL__", "op_policy,ct_portion,nct_portion,\ cpuqos_mode,dnth0,dnth1,upth0,upth1,\ hit0,hit1,hit2,hit3,mis0,mis1,mis2,mis3,\ l3_hit,l3_mis,pmu_cyc_cnt"; node-2 = "__MCUPM_MET_TEST__", "taskId,isrId,dvfs"; }; sspm_rts_header:sspm-rts-header { node-0 = "SSPM_PTPOD", "_id,voltage"; node-1 = "SSPM_MET_UNIT_TEST", "test"; node-2 = "SSPM_QOS_BOUND_STATE", "ver,apu_num,idx,state,num,event,emibw_mon_total,", "emibw_mon_cpu,emibw_mon_gpu,emibw_mon_mm,", "emibw_mon_md,smibw_mon_gpu,smibw_mon_apu,", "apubw_mon_vpu0,apubw_mon_vpu1,apubw_mon_mdla0,", "apubw_mon_mdla1,apubw_mon_mdla2,apubw_mon_mdla3,", "apubw_mon_edma0,apubw_mon_edma1,", "apulat_mon_vpu0,apulat_mon_vpu1,apulat_mon_mdla0,", "apulat_mon_mdla1,apulat_mon_mdla2,apulat_mon_mdla3,", "apulat_mon_edma0,apulat_mon_edma1"; node-3 = "SSPM_CM_MGR_NON_WFX", "non_wfx_0,non_wfx_1,non_wfx_2,non_wfx_3,", "non_wfx_4,non_wfx_5,non_wfx_6,non_wfx_7"; node-4 = "SSPM_CM_MGR_LOADING", "ratio,cps"; node-5 = "SSPM_CM_MGR_POWER", "c_up_array_0,c_up_array_1,c_up_array_2,c_down_array_0,c_down_array_1,", "c_down_array_2,c_up_0,c_up_1,c_up_2,c_down_0,c_down_1,c_down_2,c_up,", "c_down,v_up,v_down,v2f_0,v2f_1,v2f_2"; node-6 = "SSPM_CM_MGR_OPP", "v_dram_opp,v_dram_opp_cur,c_opp_cur_0,c_opp_cur_1,c_opp_cur_2,d_times_up,", "d_times_down"; node-7 = "SSPM_CM_MGR_RATIO", "ratio_0,ratio_1,ratio_2,ratio_3,ratio_4,", "ratio_5,ratio_6,ratio_7"; node-8 = "SSPM_CM_MGR_BW", "total_bw"; node-9 = "SSPM_CM_MGR_CP_RATIO", "up0,up1,up2,up3,up4,up5,down0,down1,down2,down3,down4,down5"; node-10 = "SSPM_CM_MGR_VP_RATIO", "up0,up1,up2,up3,up4,up5,down0,down1,down2,down3,down4,down5"; node-11 = "SSPM_CM_MGR_DE_TIMES", "up0,up1,up2,up3,up4,up5,down0,down1,down2,down3,down4,down5,reset"; node-12 = "SSPM_CM_MGR_DSU_DVFS_PWR", "up_L,up_B,up_BB,up_DSU,cur_L,cur_B,cur_BB,cur_DSU,down_L,down_B,", "down_BB,down_DSU,total_up,total_cur,total_down"; node-13 = "SSPM_CM_MGR_DSU_DVFS_ACT_STALL_PWR", "up_L_a,up_B_a,up_BB_a,cur_L_a,cur_B_a,", "cur_BB_a,down_L_a,down_B_a,down_BB_a,", "up_L_s,up_B_s,up_BB_s,cur_L_s,cur_B_s,", "cur_BB_s,down_L_s,down_B_s,down_BB_s"; node-14 = "SSPM_CM_MGR_DSU_DVFS_STALL", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,l3_bw_val"; node-15 = "SSPM_CM_MGR_DSU_DVFS_ACTIVE", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-16 = "SSPM_CM_MGR_DSU_DVFS_OPP", "map_opp_50,map_opp_70,final,", "orig,L3_vote_opp,debounce_up,debounce_down"; node-17 = "SSPM_CM_MGR_DSU_DVFS_THRESHOLD_FLAG", "up_L,up_B,up_BB,down_L,down_B,down_BB,", "up_L_flag,up_B_flag,up_BB_flag,", "down_L_flag,down_B_flag,down_BB_flag"; node-18 = "SSPM_SWPM_CPU__CORE_ACTIVE_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-19 = "SSPM_SWPM_CPU__CORE_IDLE_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-20 = "SSPM_SWPM_CPU__CORE_OFF_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-21 = "SSPM_SWPM_CPU__CORE_STALL_RATIO", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-22 = "SSPM_SWPM_CPU__CORE_PMU_L3DC", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-23 = "SSPM_SWPM_CPU__CORE_PMU_INST_SPEC", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-24 = "SSPM_SWPM_CPU__CORE_PMU_CYCLES", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-25 = "SSPM_SWPM_CPU__CORE_NON_WFX_CTR", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-26 = "SSPM_SWPM_CPU__DSU_STATE_RATIO", "active,idle,dormant,off"; node-27 = "SSPM_SWPM_CPU__DSU_L3_BW", "L3_BW"; node-28 = "SSPM_SWPM_CPU__MCUSYS_STATE_RATIO", "active,idle,off"; node-29 = "SSPM_SWPM_CPU__MCUSYS_EMI_BW", "cpu_emi_bw"; node-30 = "SSPM_SWPM_CPU__DVFS", "vproc3,vproc2,vproc1,cpuL_freq,cpuBL_freq,cpuB_freq,cpu_L_opp,", "cpu_BL_opp,cpu_B_opp,cci_volt,cci_freq,cci_opp"; node-31 = "SSPM_SWPM_CPU__LKG_POWER", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,dsu"; node-32 = "SSPM_SWPM_CPU__POWER", "cpu_L,cpu_B,cpu_BB,dsu,mcusys"; node-33 = "SSPM_SWPM_GPU__GPU_STATE_RATIO", "active,idle,off"; node-34 = "SSPM_SWPM_GPU__LOADING", "top_loading,stack_loading,iterator_loading"; node-35 = "SSPM_SWPM_GPU__DVFS", "top_freq,stack_freq,vgpu,vcore,mtcmos,top_ratio,stack_ratio"; node-36 = "SSPM_SWPM_GPU__URATE", "alu_fma,alu_cvt,alu_sfu,tex,lsc,l2c,vary,tiler,rast"; node-37 = "SSPM_SWPM_GPU__THERMAL", "thermal,top_lkg,stack_lkg"; node-38 = "SSPM_SWPM_GPU__COUNTER", "GPU_ACTIVE,EXEC_CORE_ACTIVE,EXEC_INSTR_FMA,EXEC_INSTR_CVT,EXEC_INSTR_SFU,", "TEX,VARY_SLOT,L20,L21,ITER_TILER_ACTIVE,ITER_COMPUTE_ACTIVE,", "ITER_FRAG_ACTIVE,VARY16_SLOT,ITERATOR_ACTIVE"; node-39 = "SSPM_SWPM_GPU__POWER", "gpu"; node-40 = "SSPM_SWPM_CORE__CAM_STATE_RATIO", "RAW_A_active,RAW_B_active,RAW_C_active,idle,off"; node-41 = "SSPM_SWPM_CORE__IMG_STATE_RATIO", "P2_active,P2_idle,MFB_active,WPE_active,off"; node-42 = "SSPM_SWPM_CORE__IPE_STATE_RATIO", "FDVT_active,DVP_active,DVS_active,DV_idle,off"; node-43 = "SSPM_SWPM_CORE__MDP_STATE_RATIO", "active,off"; node-44 = "SSPM_SWPM_CORE__DISP_STATE_RATIO", "active,off"; node-45 = "SSPM_SWPM_CORE__ADSP_STATE_RATIO", "active,off"; node-46 = "SSPM_SWPM_CORE__VENC_STATE_RATIO", "active,idle,off"; node-47 = "SSPM_SWPM_CORE__VDEC_STATE_RATIO", "active,idle,off"; node-48 = "SSPM_SWPM_CORE__INFRA_STATE_RATIO", "dact,cact,idle,dcm"; node-49 = "SSPM_SWPM_CORE__VDO_CODING_TYPE", "venc,vdec"; node-50 = "SSPM_SWPM_CORE__DVFS", "vcore,ddr_freq,vcore_opp,ddr_opp"; node-51 = "SSPM_SWPM_CORE__POWER", "dramc,infra_top,aphy_vcore"; node-52 = "SSPM_SWPM_CORE__LKG_POWER", "infra_top,dramc,thermal"; node-53 = "SSPM_SWPM_DRAM__MEM_IDX", "read_bw_0,read_bw_1,write_bw_0,write_bw_1,", "srr_pct,ssr_pct,pdir_pct_0,pdir_pct_1,", "phr_pct_0,phr_pct_1,util_0,util_1,", "trans_0,trans_1,mr4,ddr_freq,ddr_opp"; node-54 = "SSPM_SWPM_DRAM__DVFS", "ddr_freq"; node-55 = "SSPM_SWPM_DRAM__POWER", "aphy_vddq_0p6v,aphy_vm_0p75v,aphy_vio_1p2v,dram_vddq_0p6v,", "dram_vdd2l_0p9v,dram_vdd2h_1p05v,dram_vdd1_1p8v"; node-56 = "SSPM_SWPM_ME__POWER", "disp,mdp,venc,vdec"; node-57 = "SSPM_SWPM_ME__IDX", "vdec_fps,venc_fps,disp_fps,disp_resolution"; node-58 = "SSPM_SWPM_VPU__VPU0_STATE_RATIO", "active,idle,off"; node-59 = "SSPM_SWPM_VPU__VPU1_STATE_RATIO", "active,idle,off"; node-60 = "__SSPM_GPU_APU_SSC_CNT__", "N_APU_0_R,N_APU_0_W,N_GPU_0_R,N_GPU_0_W,", "N_APU_1_R,N_APU_1_W,N_GPU_1_R,", "N_GPU_1_W,S_APU_0_R,S_APU_0_W,S_GPU_0_R,", "S_GPU_0_W,S_APU_1_R,S_APU_1_W,", "S_GPU_1_R,S_GPU_1_W"; node-61 = "SSPM_SLBC_SLOT", "enable,force,done,buffer_used,f_buffer,cached_used,force_size"; node-62 = "SSPM_SLBC_REF", "venc,sh_p2,sh_apu,mml,ainr,disp,aov_dc,aov_apu,aisr_apu,", "aisr_mml,sh_p1,smt,apu,aod,bif"; node-63 = "SSPM_SLBC_BW", "mm,apu,mm_est"; node-64 = "SSPM_SLBC_PMU", "hit,miss,apu_r,apu_w,mm_r,mm_w"; node-65 = "SSPM_SLBC_WAY", "venc,sh_p2,sh_apu,mml,ainr,disp,aov_dc,aov_apu,aisr_apu,", "aisr_mml,sh_p1,smt,apu,aod,bif,slb,cpu,gpu,slc,left"; node-66 = "SSPM_SWPM_CPU__DSU_PMU", "dsu_cycles"; node-67 = "SSPM_SWPM_CPU__CORE_TEMP", "cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; node-68 = "SSPM_SWPM_SOC__SMAP", "i2max,imax"; node-69 = "SSPM_SWPM_CPU__PMU_TIMES", "idx_cnt,lock,idx_rechk,lock_rechk,valid,off_hint,diff_us"; node-70 = "SSPM_SWPM_CORE__MEM_RAW_IDX", "diff_us,data_rate,ddr_ratio,emi_freq,s1_ratio,", "wact_0,wact_1,bcnt_0,bcnt_1,", "dcm_ctrl_0,dcm_ctrl_1,", "stb_0_0,stb_0_1,stb_1_0,stb_1_1,", "stb_2_0,stb_2_1,stb_3_0,stb_3_1,", "pd_0_0,pd_0_1,pd_1_0,pd_1_1,", "pd_2_0,pd_2_1,pd_3_0,pd_3_1"; node-71 = "SSPM_SPM_RES__DDREN_REQ", "mcu,mcupm,disp0,disp1,adsp,ufs,gce,infra,peri,md,scp,sspm,emi"; node-72 = "SSPM_SPM_RES__APSRC_REQ", "mcu,mcupm,md,scp,sspm"; node-73 = "SSPM_SPM_DBG__PWR_OFF", "dsu,mcu,gpu,venc,vdec,mdp,disp,cam,img,mminfra"; node-74 = "SSPM_SPM_DBG__PWR_ACT", "scp,adsp,mmup"; node-75 = "SSPM_SPM_DBG__SYS_STA", "s0,s1"; node-76 = "SSPM_SWPM_DRAM__MEM_RAW_IDX", "diff_us,data_rate,ddr_ratio,emi_freq,s1_ratio,", "wact_0,wact_1,bact_0,bact_1,bcnt_0,bcnt_1,tact_0,tact_1,", "pgh_0,pgh_1,pgh_2,pgh_3,", "pgm_0,pgm_1,pgm_2,pgm_3,", "intb_0,intb_1,intb_2,intb_3,", "stb_0_0,stb_0_1,stb_1_0,stb_1_1,", "stb_2_0,stb_2_1,stb_3_0,stb_3_1,", "mr4_idx_0_0,mr4_idx_0_1,mr4_idx_1_0,mr4_idx_1_1,", "mr4_idx_2_0,mr4_idx_2_1,mr4_idx_3_0,mr4_idx_3_1"; node-77 = "SSPM_SWPM_CORE__SLC_IDX", "pmu_17,pmu_18,pmu_19,pmu_20,pmu_21,pmu_22,pmu_23,pmu_24,", "pmu_25,pmu_26,pmu_27,pmu_28,pmu_29"; }; gpueb_rts_header:gpueb-rts-header { node-0 = "GPUEB_MET_UNIT_TEST", "test"; node-1 = "GPUEB_PTP3_CC_FC_PING", "cc0_ping,cc1_ping,cc2_ping,cc4_ping,cc5_ping,cc6_ping,\ fc0_ping,fc1_ping,fc2_ping,fc4_ping,fc5_ping,fc6_ping"; node-2 = "GPUEB_PTP3_CC_FC_SW", "CC,FC"; node-3 = "GPUEB_PTP3_FSM", "FLL0,FLL1,FLL2,FLL4,FLL5,FLL6"; node-4 = "GPUEB_PTP3_FLL_ENABLE", "FLL0,FLL1,FLL2,FLL4,FLL5,FLL6"; node-5 = "GPUEB_PTP3_FREQ", "sign_freq,work_freq,cur_freq"; node-6 = "GPUEB_PTP3_VOLT", "sign_volt,work_volt,cur_volt"; node-7 = "GPUEB_PTP3_INVALID_FMETER", "val"; node-8 = "GPUEB_PTP3_FREQ_MONITOR", "FLL0_in,FLL1_in,FLL2_in,FLL4_in,FLL5_in,FLL6_in,\ FLL0_out,FLL1_out,FLL2_out,FLL4_out,FLL5_out,FLL6_out"; node-9 = "GPUEB_PTP3_VOLT_MONITOR", "inVolt,outVolt"; }; }; mkp { compatible = "mediatek,mkp-drv"; memory-region = <&mkp_mem>; }; }; &scp_i2c1{ clock-frequency = <1000000>; mt6338_pmic: mt6338_pmic@6b { status = "okay"; compatible = "mediatek,mt6338_pmic"; reg = <0x6b>; mt6338_sound: mt6338_sound { compatible = "mediatek,mt6338-sound"; mediatek,dmic-mode = <0>; mediatek,mic-type = <3 3 3 3>; mediatek,micbias-val = <2 2 2 2>; mediatek,micbias-mux = <0 1 2 3 3 0 0>; io-channels = <&mt6338_auxadc AUXADC_HPOFS_CAL>; io-channel-names = "pmic_hpofs_cal"; nvmem = <&mt6338_efuse>; nvmem-names = "pmic-hp-efuse"; }; mt6338_efuse: mt6338_efuse { compatible = "mediatek,mt6338-efuse"; #address-cells = <1>; #size-cells = <1>; }; mt6338_auxadc: mt6338-auxadc { compatible = "mediatek,mt6338-auxadc"; #io-channel-cells = <1>; chip_temp { channel = ; }; accdet { channel = ; }; hpofs_cal { channel = ; avg-num = <256>; }; }; mt6338_accdet: mt6338_accdet { compatible = "mediatek,mt6338-accdet"; accdet-name = "mt6338-accdet"; accdet-mic-vol = <8>; accdet-plugout-debounce = <1>; accdet-mic-mode = <2>; eint_use_ext_res = <0>; headset-mode-setting = <0x500 0x500 1 0x1f0 0x800 0x800 0x20 0x44 0x4 0x1 0x5 0x3 0x3 0x5 0xe>; headset-use-ap-eint = <0>; headset-eint-num = <0>; headset-eint-trig-mode = <1>; headset-key-mode = <0>; headset-three-key-threshold = <0 80 220 400>; headset-three-key-threshold-CDD = <0 121 192 600>; headset-four-key-threshold = <0 58 121 192 400>; io-channels = <&mt6338_auxadc AUXADC_ACCDET>; io-channel-names = "pmic_accdet"; nvmem = <&mt6338_efuse>; nvmem-names = "mt63xx-accdet-efuse"; status = "okay"; }; }; }; &spmi { pmic: pmic@4 { mt6363_dynamic_loading_throttling: mtk-dynamic-loading-throttling { compatible = "mediatek,mt6363-dynamic_loading_throttling"; /* charger: mtk_charger_thread */ mediatek,charger = <&lk_charger>; /* 2000~2900mV, one gear per 100mV */ uvlo-level = <2600>; vbb-uvlo-level = <2600>; io-channels = <&mt6375_auxadc MT6375_AUXADC_IMP>, <&mt6375_auxadc MT6375_AUXADC_IMIX_R>, <&mt6375_auxadc MT6375_AUXADC_BATSNS>; io-channel-names = "pmic_ptim", "pmic_imix_r", "pmic_batadc"; bootmode = <&chosen>; }; }; mt6319_6: mt6319@6 { compatible = "mediatek,mt6319"; reg = <0x6 SPMI_USID>; extbuck-debug { compatible = "mediatek,spmi-pmic-debug"; }; mt6319_6_regulator: mt6319-6-regulator { compatible = "mediatek,mt6315_6-regulator"; buck-size = <2>; buck1-modeset-mask = <0x3>; mt6319_6_vbuck1: 6-vbuck1 { regulator-compatible = "vbuck1"; regulator-name = "6_vbuck1"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; regulator-always-on; }; mt6319_6_vbuck3: 6-vbuck3 { regulator-compatible = "vbuck3"; regulator-name = "6_vbuck3"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; regulator-always-on; }; }; }; mt6319_7: mt6319@7 { compatible = "mediatek,mt6319"; reg = <0x7 SPMI_USID>; extbuck-debug { compatible = "mediatek,spmi-pmic-debug"; }; mt6319_7_regulator: mt6319-7-regulator { compatible = "mediatek,mt6315_7-regulator"; buck-size = <2>; buck1-modeset-mask = <0xB>; mt6319_7_vbuck1: 7-vbuck1 { regulator-compatible = "vbuck1"; regulator-name = "7_vbuck1"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; regulator-always-on; }; mt6319_7_vbuck3: 7-vbuck3 { regulator-compatible = "vbuck3"; regulator-name = "7_vbuck3"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-always-on; }; }; }; mt6319_15: mt6319@f { compatible = "mediatek,mt6319"; reg = <0xf SPMI_USID>; extbuck-debug { compatible = "mediatek,spmi-pmic-debug"; }; mt6319_15_regulator: mt6319-15-regulator { compatible = "mediatek,mt6315_15-regulator"; buck-size = <2>; buck1-modeset-mask = <0xB>; mt6319_15_vbuck3: 15-vbuck3 { regulator-compatible = "vbuck3"; regulator-name = "15_vbuck3"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; regulator-enable-ramp-delay = <256>; regulator-always-on; }; }; }; clock_buffer_ctrl: clock_buffer_ctrl { compatible = "mediatek,clock_buffer_ctrl"; mediatek,xo-buf-hwbblpm-mask = <1 0 0 0 0>, <0 0 0>, <0 0 0>, <0 0>; mediatek,xo-buf-hwbblpm-bypass = <0 0 0 0 0>, <0 0 0>, <0 0 0>, <0 0>; mediatek,xo-bbck4 = <0>; mediatek,enable; pmif = <&spmi 0>; pmif_version = <2>; srclken_rc = <&srclken_rc>; // consys = <&consys>; // pcie = <&pcie_ckm_xtal_ck>; }; }; #include "mediatek/mt6685.dtsi" &mt6685_mfd { mt6685_clock_buffer: mt6685_clock_buffer { mediatek,xo-buf-support = <1 1 1 1 0> /* BBCK */, <1 1 0> /* RFCK1 */, <1 1 0> /* RFCK2 */, <0 0> /* CONCK */; mediatek,bblpm-support; mediatek,xo-voter-support; mediatek,dcxo-spmi-rw; mediatek,pmrc-en-support; clkbuf_ctl = <&clock_buffer_ctrl>; mediatek,enable; }; }; &mt6685_rtc { status = "okay"; }; #include "mediatek/cust_mt6985_msdc.dtsi" #include "mediatek/rt5133.dtsi" #include "mediatek/mt6363.dtsi" #include "mediatek/mt6373.dtsi" #include "mediatek/cust_mt6985_connfem.dtsi" &rt5133 { interrupts-extended = <&pio 187 0x0>; enable-gpio = <&pio 188 0x0>; }; &mt6363_vbuck2 { regulator-always-on; }; &mt6363_vbuck4 { regulator-always-on; }; &mt6363_vbuck5 { regulator-always-on; }; &mt6363_vbuck6 { regulator-always-on; }; &mt6363_vsram_digrf { regulator-always-on; }; &mt6363_vsram_modem { regulator-always-on; }; &mt6363_vsram_cpub { regulator-always-on; }; &mt6363_vsram_cpum { regulator-always-on; }; &mt6363_vsram_cpul { regulator-always-on; }; &mt6363_vsram_apu { regulator-always-on; }; &mt6363_vcn15 { regulator-always-on; }; &mt6363_vufs18 { regulator-always-on; }; &mt6363_vm18 { regulator-always-on; }; &mt6363_vufs12 { regulator-always-on; }; &mt6363_vrf12 { regulator-always-on; }; &mt6373_vbuck2 { regulator-always-on; }; &mt6373_vbuck4 { regulator-always-on; }; &mt6373_vsram_digrf_aif { regulator-always-on; }; &mt6373_vbuck5 { regulator-always-on; }; &mt6373_vbuck6 { regulator-always-on; }; &mt6373_vbuck7 { regulator-always-on; }; &mt6373_vbuck4_ufs { regulator-min-microvolt = <0>; }; /delete-node/ &mt6363_vbuck4_sshub; /delete-node/ &mt6373_vmch; /delete-node/ &mt6373_vmch_eint_low; &main_pmic { pmic-lvsys-notify { compatible = "mediatek,mt6363-lvsys-notify"; thd-volts-l = <3400>; thd-volts-h = <3500>; lv-deb-sel = <0>; hv-deb-sel = <2>; vio18-switch-reg = <0x53 0x58>; status = "okay"; }; }; &mddriver { /* for md pmic voltage setting*/ md-vmodem-supply = <&mt6363_vbuck2>; md-vmodem = <800000 800000>; md-vsram-supply = <&mt6363_vsram_modem>; md-vsram = <800000 800000>; md-vdigrf-supply = <&mt6363_vbuck5>; md-vdigrf = <725000 725000>; }; &md_auxadc { io-channels = <&pmic_adc (ADC_PURES_OPEN_MASK | AUXADC_VIN1)>; }; &i2c5 { clock-frequency = <1000000>; mt6375: mt6375@34 { compatible = "mediatek,mt6375"; reg = <0x34>; status = "okay"; interrupt-parent = <&pio>; interrupts = <66 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; wakeup-source; mt6375_adc: adc { compatible = "mediatek,mt6375-adc"; #io-channel-cells = <1>; interrupts = ; interrupt-names = "adc_donei"; }; mt6375_chg: chg { compatible = "mediatek,mt6375-chg"; interrupts = , , , , , , , , , ; interrupt-names = "fl_pwr_rdy", "fl_detach", "fl_vbus_ov", "fl_chg_tout", "fl_wdt", "fl_bc12_dn", "fl_aicc_done", "fl_pe_done", "fl_batpro_done", "adc_vbat_mon_ov"; io-channels = <&mt6375_adc MT6375_ADC_CHGVIN>, <&mt6375_adc MT6375_ADC_VSYS>, <&mt6375_adc MT6375_ADC_VBAT>, <&mt6375_adc MT6375_ADC_IBUS>, <&mt6375_adc MT6375_ADC_IBAT>, <&mt6375_adc MT6375_ADC_TEMPJC>, <&mt6375_adc MT6375_ADC_USBDP>, <&mt6375_adc MT6375_ADC_USBDM>; chg_name = "primary_chg"; aicr = <500>; mivr = <4400>; cv = <4200>; ichg = <2000>; ieoc = <150>; wdt = <40000>; /* wdt_en; */ te_en; vbus_ov = <14500>; vrec = <100>; otg_lbp = <2800>; ircmp_r = <16700>; ircmp_v = <32>; chg_tmr = <10>; chg_tmr_en; dcdt_sel = <600>; bc12_sel = <&mtk_ctd>; boot_mode = <&chosen>; phys = <&u2port0 PHY_TYPE_USB2>; phy-names = "usb2-phy"; usb = <&ssusb>; pmic-uvlo = <&mt6363_dynamic_loading_throttling>; //usb_killer_detect; mt6375_otg_vbus: otg { regulator-compatible = "mt6375,otg-vbus"; regulator-name = "usb-otg-vbus"; regulator-min-microvolt = <4850000>; regulator-max-microvolt = <5500000>; regulator-min-microamp = <500000>; regulator-max-microamp = <2400000>; }; }; mt6375_typec: tcpc { compatible = "mediatek,mt6375-tcpc"; interrupts = ; interrupt-names = "pd_evt"; /* tcpc_device's name */ tcpc,name = "type_c_port0"; /* 0: Unknown, 1: SNK, 2: SRC, 3: DRP, 4: Try.SRC, 5: Try.SNK */ tcpc,role_def = <5>; /* 0: Default, 1: 1.5, 2: 3.0 */ tcpc,rp_level = <1>; /* 0: Never, 1: Always, 2: EMarkOnly, 3: StartOnly */ tcpc,vconn_supply = <1>; io-channels = <&mt6375_adc MT6375_ADC_SBU1>, <&mt6375_adc MT6375_ADC_SBU2>; charger = <&mt6375_chg>; tcpc,en_wd; tcpc,en_wd_sbu_polling; tcpc,en_wd_polling_only; tcpc,en_ctd; tcpc,en_fod; tcpc,en_typec_otp; //tcpc,en_floatgnd; wd,sbu_calib_init = <1200>; /* mV */ wd,sbu_pl_bound = <200>; /* mV */ wd,sbu_pl_lbound_c2c = <1100>; /* mV */ wd,sbu_pl_ubound_c2c = <2600>; /* mV */ wd,sbu_ph_auddev = <100>; /* mV */ wd,sbu_ph_lbound = <888>; /* mV */ wd,sbu_ph_lbound1_c2c = <2850>; /* mV */ wd,sbu_ph_ubound1_c2c = <3150>; /* mV */ wd,sbu_ph_ubound2_c2c = <3800>; /* mV */ wd,sbu_aud_ubound = <1600>; /* mV */ /* 0:16x, 1:128x, 2:512x, 3:1024x */ wd,wd0_tsleep = <1>; /* 0:400us, 1:1ms, 2:2ms, 3:4ms, 4:10ms, 5:40ms, 6:100ms, 7:400ms */ wd,wd0_tdet = <3>; /* example wd0_tsleep = 512x, wd0_tdet = 4ms, wd0 polling time = 512*4ms */ pd-data { pd,vid = <0x29cf>; pd,pid = <0x6375>; pd,source-cap-ext = /bits/ 8 <0xcf 0x29 0x75 0x63 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x07 0x00>; pd,mfrs = "RichtekTCPC"; /* * VSAFE5V = 0, MAX_POWER = 1, CUSTOM = 2, * MAX_POWER_LV = 0x21, MAX_POWER_LVIC = 0x31 * MAX_POWER_HV = 0x41, MAX_POWER_HVIC = 0x51 */ pd,charging_policy = <0x31>; pd,source-pdo-size = <1>; pd,source-pdo-data = <0x00019096>; /* 5V, 1500 mA */ pd,sink-pdo-size = <1>; pd,sink-pdo-data = <0x000190c8>; /* * No DP, host + device * pd,id-vdo-size = <6>; * pd,id-vdo-data = <0xd14029cf 0x0 0x63750000 0x61000000 0x0 0x41000000>; * With DP * pd,id-vdo-size = <6>; * pd,id-vdo-data = <0xd54029cf 0x0 0x63750000 0x61000000 0x0 0x41000000>; */ pd,id-vdo-size = <6>; pd,id-vdo-data = <0xd54029cf 0x0 0x63750000 0x61000000 0x0 0x41000000>; bat,nr = <1>; bat-info0 { bat,vid = <0x29cf>; bat,pid = <0x6375>; bat,mfrs = "bat1"; bat,design_cap = <3000>; }; }; dpm_caps { local_dr_power; local_dr_data; // local_ext_power; local_usb_comm; // local_usb_suspend; // local_high_cap; // local_give_back; local_no_suspend; local_vconn_supply; // attempt_discover_cable_dfp; attempt_enter_dp_mode; attempt_discover_cable; attempt_discover_id; /* 0: disable, 1: prefer_snk, 2: prefer_src */ pr_check = <0>; // pr_reject_as_source; // pr_reject_as_sink; // pr_check_gp_source; // pr_check_gp_sink; /* 0: disable, 1: prefer_ufp, 2: prefer_dfp */ dr_check = <0>; // dr_reject_as_dfp; // dr_reject_as_ufp; }; displayport { /* connection type = "both", "ufp_d", "dfp_d" */ 1st_connection = "dfp_d"; 2nd_connection = "dfp_d"; signal,dp_v13; //signal,dp_gen2; //usbr20_not_used; typec,receptacle; ufp_d { //pin_assignment,mode_a; //pin_assignment,mode_b; //pin_assignment,mode_c; //pin_assignment,mode_d; //pin_assignment,mode_e; }; dfp_d { //pin_assignment,mode_a; //pin_assignment,mode_b; pin_assignment,mode_c; pin_assignment,mode_d; pin_assignment,mode_e; //pin_assignment,mode_f; }; }; }; mt6375_auxadc: auxadc { compatible = "mediatek,pmic-auxadc", "mediatek,mt6375-auxadc"; interrupts = ; interrupt-controller; #interrupt-cells = <1>; #io-channel-cells = <1>; io-channels = <&mt6375_adc MT6375_ADC_VBAT>, <&mt6375_auxadc MT6375_AUXADC_BATSNS_DBG>; io-channel-names = "chg_vbat", "auxadc_vbat"; charger = <&mt6375_chg>; isink_load-supply = <&mt6363_isink_load>; imix_r { val = <90>; }; }; mtk_gauge: mtk_gauge { compatible = "mediatek,mt6375-gauge"; interrupt-controller; #interrupt-cells = <1>; bootmode = <&chosen>; charger = <&mt6375_chg>; io-channels = <&mt6375_auxadc MT6375_AUXADC_BATSNS>, <&mt6375_auxadc MT6375_AUXADC_BATON>, <&mt6375_auxadc MT6375_AUXADC_IMP>, <&mt6375_auxadc MT6375_AUXADC_IMIX_R>, <&mt6375_auxadc MT6375_AUXADC_VREF>; io-channel-names = "bat_volt", "bat_temp", "ptim_bat_volt", "ptim_r", "vref"; interrupts-extended = <&mt6375 MT6375_GM30_EVT>, <&mtk_gauge RG_INT_STATUS_FG_BAT_H>, <&mtk_gauge RG_INT_STATUS_FG_BAT_L>, <&mt6375_auxadc RG_INT_STATUS_BAT2_H>, <&mt6375_auxadc RG_INT_STATUS_BAT2_L>, <&mt6375_auxadc RG_INT_STATUS_NAG_C_DLTV>, <&mtk_gauge RG_INT_STATUS_BATON_BAT_OUT>, <&mtk_gauge RG_INT_STATUS_FG_ZCV>, <&mtk_gauge RG_INT_STATUS_FG_N_CHARGE_L>, <&mtk_gauge RG_INT_STATUS_FG_IAVG_H>, <&mtk_gauge RG_INT_STATUS_FG_IAVG_L>, <&mt6375_auxadc RG_INT_STATUS_BAT_TEMP_H>, <&mt6375_auxadc RG_INT_STATUS_BAT_TEMP_L>; interrupt-names = "GM30_EVT", "COULOMB_H", "COULOMB_L", "VBAT2_H", "VBAT2_L", "NAFG", "BAT_OUT", "ZCV", "FG_N_CHARGE_L", "FG_IAVG_H", "FG_IAVG_L", "BAT_TMP_H", "BAT_TMP_L"; nvmem-cells = <&fg_init>, <&fg_soc>; nvmem-cell-names = "initialization", "state-of-charge"; }; lbat_service { compatible = "mediatek,mt6375-lbat-service"; interrupts-extended = <&mt6375_auxadc RG_INT_STATUS_BAT_H>, <&mt6375_auxadc RG_INT_STATUS_BAT_L>; interrupt-names = "bat_h", "bat_l"; resistance-ratio = <4 1>; }; dbg { compatible = "mediatek,mt6375-dbg"; }; mt6375_batoc_throttle: mtk_battery_oc_throttling { compatible = "mediatek,mt6375-battery_oc_throttling"; interrupts-extended = <&mtk_gauge MT6375_IRQ_FG_CUR_H>, <&mtk_gauge MT6375_IRQ_FG_CUR_L>; interrupt-names = "fg_cur_h", "fg_cur_l"; oc-thd-h = <6800>; oc-thd-l = <8000>; }; }; }; &i2c6 { ps5170: ps5170@28 { compatible = "parade,ps5170"; reg = <0x28>; mediatek,vs-voter = <&pmic 0x189a 0x20 1>; status = "okay"; }; gate_ic: gate_ic@11 { #address-cells = <1>; #size-cells = <0>; compatible = "mediatek,gate-ic-i2c"; gate-power-gpios = <&pio 68 0>; reg = <0x11>; id = <6>; status = "okay"; }; }; /* BT combo GPIO start */ &pio { bt_combo_gpio_init: bt_combo_gpio_init { /* BT_UTXD, GPIO224*/ pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; /* BT_URXD, GPIO225*/ pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; bt_combo_gpio_pre_on: bt_combo_gpio_pre_on { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-up; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-up; }; }; bt_combo_uart_tx_aux: bt_combo_uart_tx_aux { pins_cmd1_dat { pinmux = ; }; }; bt_combo_uart_rx_aux: bt_combo_uart_rx_aux { pins_cmd1_dat { pinmux = ; }; }; bt_rst_on: bt_rst_on { pins_cmd1_dat { pinmux = ; output-high; }; }; bt_rst_off: bt_rst_off { pins_cmd1_dat { pinmux = ; output-low; }; }; bt_find_my_phone_high: bt-find-my-phone-high { pins-cmd1-dat { pinmux = ; output-high; }; }; bt_find_my_phone_low: bt-find-my-phone-low { pins-cmd1-dat { pinmux = ; output-low; }; }; }; /* BT combo GPIO end */ /* WF GPIO start */ &pio { wf_rst_off: wf_rst_off { pins_cmd1_dat { pinmux = ; output-low; }; }; wf_rst_on: wf_rst_on { pins_cmd1_dat { pinmux = ; output-high; }; }; wf_rst_pta_uart_init: wf_rst_pta_uart_init { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; wf_rst_pta_uart_on: wf_rst_pta_uart_on { pins_cmd1_dat { pinmux = ; output-low; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; wf_rst_pta_uart_off: wf_rst_pta_uart_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; }; /* WF GPIO end */ #include "mediatek/bat_setting/mt6985_battery_prop.dtsi" /* AUDIO GPIO standardization start */ &pio { aud_clk_mosi_off: aud_clk_mosi_off { pins_cmd0_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_clk_mosi_on: aud_clk_mosi_on { pins_cmd0_dat { pinmux = ; input-enable; bias-disable; }; pins_cmd1_dat { pinmux = ; input-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_mosi_off: aud_dat_mosi_off { pins_cmd1_dat { pinmux = ; input-enable; bias-disable; }; }; aud_dat_mosi_on: aud_dat_mosi_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_mosi_ch34_off: aud_dat_mosi_ch34_off { pins_cmd1_dat { pinmux = ; input-enable; bias-disable; }; }; aud_dat_mosi_ch34_on: aud_dat_mosi_ch34_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_miso0_off: aud_dat_miso0_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_miso0_on: aud_dat_miso0_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_miso2_off: aud_dat_miso2_off { pins_cmd1_dat { pinmux = ; input-enable; bias-disable; }; }; aud_dat_miso2_on: aud_dat_miso2_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; vow_dat_miso_off: vow_dat_miso_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; vow_dat_miso_on: vow_dat_miso_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; vow_clk_miso_off: vow_clk_miso_off { pins_cmd3_dat { pinmux = ; input-enable; bias-disable; }; }; vow_clk_miso_on: vow_clk_miso_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s0_off: aud_gpio_i2s0_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s0_on: aud_gpio_i2s0_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s3_off: aud_gpio_i2s3_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd3_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s3_on: aud_gpio_i2s3_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd3_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; connsys_pin_pmic_en_default: connsys-pin-pmic-en-default { pins-cmd-dat { pinmux = ; output-low; }; }; connsys_pin_pmic_en_set: connsys-pin-pmic-en-set { pins-cmd-dat { pinmux = ; output-high; }; }; connsys_pin_pmic_en_clr: connsys-pin-pmic-en-clr { pins-cmd-dat { pinmux = ; output-low; }; }; connsys_pin_pmic_faultb_default: connsys-pin-pmic-faultb-default { pins-cmd-dat { pinmux = ; input-enable; bias-pull-down; }; }; connsys_pin_pmic_faultb_enable: connsys-pin-pmic-faultb-enable { pins-cmd-dat { pinmux = ; input-enable; bias-pull-up; }; }; connsys_combo_gpio_init: connsys-combo-gpio-init { /* 228 SCP_WB_UTXD */ pins-cmd1-dat { pinmux = ; slew-rate = <0>; bias-pull-down; }; /* 229 SCP_WB_URXD */ pins-cmd2-dat { pinmux = ; slew-rate = <0>; bias-pull-down; }; }; connsys_combo_gpio_pre_on: connsys-combo-gpio-pre-on { /* 228 SCP_WB_UTXD */ pins-cmd1-dat { pinmux = ; slew-rate = <0>; bias-pull-up; }; /* 229 SCP_WB_URXD */ pins-cmd2-dat { pinmux = ; slew-rate = <0>; bias-pull-up; }; }; connsys_combo_gpio_on: connsys-combo-gpio-on { /* 228 SCP_WB_UTXD */ pins-cmd1-dat { pinmux = ; }; /* 229 SCP_WB_URXD */ pins-cmd2-dat { pinmux = ; }; }; connsys_pin_ext32k_en_default: connsys-pin-ext32k-en-default { pins-cmd-data { pinmux = ; output-low; }; }; connsys_pin_ext32k_en_set: connsys-pin-ext32k-en-set { pins-cmd-data { pinmux = ; output-high; }; }; connsys_pin_ext32k_en_clr: connsys-pin-ext32k-en-clr { pins-cmd-data { pinmux = ; output-low; }; }; aud_gpio_i2s8_off: aud_gpio_i2s8_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s8_on: aud_gpio_i2s8_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s9_off: aud_gpio_i2s9_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd3_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s9_on: aud_gpio_i2s9_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd3_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_etdmin_off: aud-gpio-etdmin-off { pins-cmd1-dat { pinmux = ; input-enable; bias-pull-down; }; pins-cmd2-dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_etdmin_on: aud-gpio-etdmin-on { pins-cmd1-dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins-cmd2-dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_etdmout_off: aud-gpio-etdmout-off { pins-cmd1-dat { pinmux = ; input-enable; bias-pull-down; }; pins-cmd2-dat { pinmux = ; input-enable; bias-pull-down; }; pins-cmd3-dat { pinmux = ; input-enable; bias-pull-down; }; pins-cmd4-dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_etdmout_on: aud-gpio-etdmout-on { pins-cmd1-dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins-cmd2-dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins-cmd3-dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins-cmd4-dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; }; /* AUDIO GPIO standardization end */ #include "mediatek/mt6985-clkitg.dtsi" #include "mediatek/mt6985-disable-unused.dtsi" #include "mediatek/trusty.dtsi" &trusty { trusty-sapu { compatible = "android,trusty-sapu"; iommus = <&apu_iommu0 M4U_PORT_L40_APU_CODE>; status = "okay"; }; };