// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2022 MediaTek Inc.
 * Author: Chuan-Wen Chen <chuan-wen.chen@mediatek.com>
 */

&disable_unused {
	status = "okay";
	disable-unused-clk-mdpsys {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&mdpsys_config_clk CLK_MDP_MUTEX0>,
			<&mdpsys_config_clk CLK_MDP_APB_BUS>,
			<&mdpsys_config_clk CLK_MDP_SMI0>,
			<&mdpsys_config_clk CLK_MDP_RDMA0>,
			<&mdpsys_config_clk CLK_MDP_FG0>,
			<&mdpsys_config_clk CLK_MDP_HDR0>,
			<&mdpsys_config_clk CLK_MDP_AAL0>,
			<&mdpsys_config_clk CLK_MDP_RSZ0>,
			<&mdpsys_config_clk CLK_MDP_TDSHP0>,
			<&mdpsys_config_clk CLK_MDP_COLOR0>,
			<&mdpsys_config_clk CLK_MDP_WROT0>,
			<&mdpsys_config_clk CLK_MDP_FAKE_ENG0>,
			<&mdpsys_config_clk CLK_MDP_DLI_ASYNC0>,
			<&mdpsys_config_clk CLK_MDP_DLI_ASYNC1>,
			<&mdpsys_config_clk CLK_MDP_RSZ2>,
			<&mdpsys_config_clk CLK_MDP_WROT2>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>;
	};

	disable-unused-clk-mminfra_config {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&mminfra_config_clk CLK_MMINFRA_GCE_D>,
			<&mminfra_config_clk CLK_MMINFRA_GCE_M>,
			<&mminfra_config_clk CLK_MMINFRA_GCE_26M>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>;
	};

	disable-unused-clk-sramrc_apb {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&sramrc_apb_clk CLK_SRAMRC_APB_SRAMRC_EN>;
	};

	disable-unused-clk-ipesys {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&ipesys_clk CLK_IPE_LARB19>,
			<&ipesys_clk CLK_IPE_LARB20>,
			<&ipesys_clk CLK_IPE_SMI_SUBCOM>,
			<&ipesys_clk CLK_IPE_FD>,
			<&ipesys_clk CLK_IPE_FE>,
			<&ipesys_clk CLK_IPE_RSC>,
			<&ipesys_clk CLK_IPE_GALS>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_IPE>;
	};

	disable-unused-clk-camsys_rawb {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&camsys_rawb_clk CLK_CAM_RB_LARBX>,
			<&camsys_rawb_clk CLK_CAM_RB_CAM>,
			<&camsys_rawb_clk CLK_CAM_RB_CAMTG>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBB>;
	};

	disable-unused-clk-camsys_rawa {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&camsys_rawa_clk CLK_CAM_RA_LARBX>,
			<&camsys_rawa_clk CLK_CAM_RA_CAM>,
			<&camsys_rawa_clk CLK_CAM_RA_CAMTG>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBA>;
	};

	disable-unused-clk-camsys_main {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&camsys_main_clk CLK_CAM_M_LARB13>,
			<&camsys_main_clk CLK_CAM_M_LARB14>,
			<&camsys_main_clk CLK_CAM_M_CAM>,
			<&camsys_main_clk CLK_CAM_M_CAMTG>,
			<&camsys_main_clk CLK_CAM_M_SENINF>,
			<&camsys_main_clk CLK_CAM_M_CAMSV1>,
			<&camsys_main_clk CLK_CAM_M_CAMSV2>,
			<&camsys_main_clk CLK_CAM_M_CAMSV3>,
			<&camsys_main_clk CLK_CAM_M_FAKE_ENG>,
			<&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>;
	};

	disable-unused-clk-scp_iic {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&scp_iic_clk CLK_SCP_IIC_AP_CLOCK_I2C0>,
			<&scp_iic_clk CLK_SCP_IIC_AP_CLOCK_I2C1>,
			<&scp_iic_clk CLK_SCP_IIC_AP_CLOCK_I2C2>,
			<&scp_iic_clk CLK_SCP_IIC_AP_CLOCK_I2C3>,
			<&scp_iic_clk CLK_SCP_IIC_AP_CLOCK_I2C4>,
			<&scp_iic_clk CLK_SCP_IIC_AP_CLOCK_I2C5>,
			<&scp_iic_clk CLK_SCP_IIC_AP_CLOCK_I2C6>;
	};

	disable-unused-clk-vencsys {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&venc_gcon_clk CLK_VEN1_CKE0_LARB>,
			<&venc_gcon_clk CLK_VEN1_CKE1_VENC>,
			<&venc_gcon_clk CLK_VEN1_CKE2_JPGENC>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_VEN0>;
	};

	disable-unused-clk-vdec_gcon_base {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>,
			<&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN>,
			<&vdec_gcon_base_clk CLK_VDE2_VDEC_ACTIVE>,
			<&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN_ENG>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_VDE0>;
	};

	disable-unused-clk-imgsys1 {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&imgsys1_clk CLK_IMGSYS1_LARB9>,
			<&imgsys1_clk CLK_IMGSYS1_DIP>,
			<&imgsys1_clk CLK_IMGSYS1_GALS>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_DIP1>;
	};

	disable-unused-clk-dispsys_config {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&dispsys_config_clk CLK_MM_DISP_MUTEX0>,
			<&dispsys_config_clk CLK_MM_DISP_OVL0>,
			<&dispsys_config_clk CLK_MM_DISP_FAKE_ENG0>,
			<&dispsys_config_clk CLK_MM_INLINEROT0>,
			<&dispsys_config_clk CLK_MM_DISP_WDMA0>,
			<&dispsys_config_clk CLK_MM_DISP_FAKE_ENG1>,
			<&dispsys_config_clk CLK_MM_DISP_DBI0>,
			<&dispsys_config_clk CLK_MM_DISP_OVL0_2L_NW>,
			<&dispsys_config_clk CLK_MM_DISP_RDMA0>,
			<&dispsys_config_clk CLK_MM_DISP_RDMA1>,
			<&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC0>,
			<&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC1>,
			<&dispsys_config_clk CLK_MM_DISP_DLI_ASYNC2>,
			<&dispsys_config_clk CLK_MM_DISP_DLO_ASYNC0>,
			<&dispsys_config_clk CLK_MM_DISP_DLO_ASYNC1>,
			<&dispsys_config_clk CLK_MM_DISP_DLO_ASYNC2>,
			<&dispsys_config_clk CLK_MM_DISP_RSZ0>,
			<&dispsys_config_clk CLK_MM_DISP_COLOR0>,
			<&dispsys_config_clk CLK_MM_DISP_CCORR0>,
			<&dispsys_config_clk CLK_MM_DISP_AAL0>,
			<&dispsys_config_clk CLK_MM_DISP_GAMMA0>,
			<&dispsys_config_clk CLK_MM_DISP_POSTMASK0>,
			<&dispsys_config_clk CLK_MM_DISP_DITHER0>,
			<&dispsys_config_clk CLK_MM_DISP_DSC_WRAP0>,
			<&dispsys_config_clk CLK_MM_DISP_DUMMY_MOD_B0>,
			<&dispsys_config_clk CLK_MM_DISP_DSI0>,
			<&dispsys_config_clk CLK_MM_DISP_DP_INTF0>,
			<&dispsys_config_clk CLK_MM_APB_BUS>,
			<&dispsys_config_clk CLK_MM_DISP_TDSHP0>,
			<&dispsys_config_clk CLK_MM_DISP_C3D0>,
			<&dispsys_config_clk CLK_MM_DISP_Y2R0>,
			<&dispsys_config_clk CLK_MM_MDP_AAL0>,
			<&dispsys_config_clk CLK_MM_DISP_CHIST0>,
			<&dispsys_config_clk CLK_MM_DISP_CHIST1>,
			<&dispsys_config_clk CLK_MM_DISP_OVL0_2L>,
			<&dispsys_config_clk CLK_MM_DLI_ASYNC3>,
			<&dispsys_config_clk CLK_MM_DLO_ASYNC3>,
			<&dispsys_config_clk CLK_MM_DUMMY_MOD_B1>,
			<&dispsys_config_clk CLK_MM_DISP_OVL1_2L>,
			<&dispsys_config_clk CLK_MM_DUMMY_MOD_B2>,
			<&dispsys_config_clk CLK_MM_DUMMY_MOD_B3>,
			<&dispsys_config_clk CLK_MM_DUMMY_MOD_B4>,
			<&dispsys_config_clk CLK_MM_DISP_OVL1_2L_NW>,
			<&dispsys_config_clk CLK_MM_DUMMY_MOD_B5>,
			<&dispsys_config_clk CLK_MM_DUMMY_MOD_B6>,
			<&dispsys_config_clk CLK_MM_DUMMY_MOD_B7>,
			<&dispsys_config_clk CLK_MM_SMI_IOMMU>,
			<&dispsys_config_clk CLK_MM_DISP_DSI>,
			<&dispsys_config_clk CLK_MM_DISP_DBPI>,
			<&dispsys_config_clk CLK_MM_DISP_HRT_URGENT>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>;
	};

	disable-unused-clk-imp_iic_wrap_en {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C0>,
			<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C2>,
			<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C4>,
			<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C9>;
	};

	disable-unused-clk-imp_iic_wrap_s {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C1>,
			<&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C6>,
			<&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C7>,
			<&imp_iic_wrap_s_clk CLK_IMPS_AP_CLOCK_I2C8>;
	};

	disable-unused-clk-imp_iic_wrap_ws {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&imp_iic_wrap_ws_clk CLK_IMPWS_AP_CLOCK_I2C3>,
			<&imp_iic_wrap_ws_clk CLK_IMPWS_AP_CLOCK_I2C5>;
	};

	disable-unused-clk-imp_iic_wrap_c {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&imp_iic_wrap_c_clk CLK_IMPC_AP_CLOCK_I2C10>,
			<&imp_iic_wrap_c_clk CLK_IMPC_AP_CLOCK_I2C11>;
	};

	disable-unused-clk-afe {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&afe_clk CLK_AFE_AFE>,
			<&afe_clk CLK_AFE_22M>,
			<&afe_clk CLK_AFE_24M>,
			<&afe_clk CLK_AFE_APLL2_TUNER>,
			<&afe_clk CLK_AFE_APLL_TUNER>,
			<&afe_clk CLK_AFE_ADC>,
			<&afe_clk CLK_AFE_DAC>,
			<&afe_clk CLK_AFE_DAC_PREDIS>,
			<&afe_clk CLK_AFE_TML>,
			<&afe_clk CLK_AFE_NLE>,
			<&afe_clk CLK_AFE_GENERAL3_ASRC>,
			<&afe_clk CLK_AFE_CONNSYS_I2S_ASRC>,
			<&afe_clk CLK_AFE_GENERAL1_ASRC>,
			<&afe_clk CLK_AFE_GENERAL2_ASRC>,
			<&afe_clk CLK_AFE_DAC_HIRES>,
			<&afe_clk CLK_AFE_ADC_HIRES>,
			<&afe_clk CLK_AFE_ADC_HIRES_TML>,
			<&afe_clk CLK_AFE_I2S5_BCLK>,
			<&afe_clk CLK_AFE_I2S1_BCLK>,
			<&afe_clk CLK_AFE_I2S2_BCLK>,
			<&afe_clk CLK_AFE_I2S3_BCLK>,
			<&afe_clk CLK_AFE_I2S4_BCLK>;
			power-domains = <&scpsys MT6835_POWER_DOMAIN_AUDIO>;
	};

	disable-unused-clk-pericfg_ao {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&pericfg_ao_clk CLK_PERAOP_UART0>,
			<&pericfg_ao_clk CLK_PERAOP_UART1>,
			<&pericfg_ao_clk CLK_PERAOP_PWM_HCLK>,
			<&pericfg_ao_clk CLK_PERAOP_PWM_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK1>,
			<&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK2>,
			<&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK3>,
			<&pericfg_ao_clk CLK_PERAOP_PWM_FBCLK4>,
			<&pericfg_ao_clk CLK_PERAOP_BTIF_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_DISP_PWM0>,
			<&pericfg_ao_clk CLK_PERAOP_SPI0_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_SPI1_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_SPI2_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_SPI3_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_SPI4_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_SPI5_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_SPI6_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_SPI7_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_APDMA>,
			<&pericfg_ao_clk CLK_PERAOP_USB_FRMCNT>,
			<&pericfg_ao_clk CLK_PERAOP_USB_SYS>,
			<&pericfg_ao_clk CLK_PERAOP_USB_XHCI>,
			<&pericfg_ao_clk CLK_PERAOP_MSDC1_SRC>,
			<&pericfg_ao_clk CLK_PERAOP_MSDC1_HCLK>,
			<&pericfg_ao_clk CLK_PERAOP_MSDC0_SRC>,
			<&pericfg_ao_clk CLK_PERAOP_MSDC0_HCLK>,
			<&pericfg_ao_clk CLK_PERAOP_MSDC0_AES>,
			<&pericfg_ao_clk CLK_PERAOP_MSDC0_XCLK>,
			<&pericfg_ao_clk CLK_PERAOP_MSDC0_HCLK_WRAP>,
			<&pericfg_ao_clk CLK_PERAOP_NFIECC_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_NFI_BCLK>,
			<&pericfg_ao_clk CLK_PERAOP_NFI_HCLK>,
			<&pericfg_ao_clk CLK_AUXADC_BCLK_AP>,
			<&pericfg_ao_clk CLK_AUXADC_BCLK_MD>,
			<&pericfg_ao_clk CLK_PERAO_AUDIO_SLV_CKP>,
			<&pericfg_ao_clk CLK_PERAO_AUDIO_MST_CKP>,
			<&pericfg_ao_clk CLK_PERAO_INTBUS_CKP>;
	};

	disable-unused-clk-nemi_reg {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&nemi_reg_clk CLK_NEMI_REG_BUS_MON_MODE>;
	};

	disable-unused-clk-infracfg_ao {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&infracfg_ao_clk CLK_IFRAO_THERM>,
			<&infracfg_ao_clk CLK_IFRAO_CPUM>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF1_AP>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF1_MD>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF_AP>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF_MD>,
			<&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>,
			<&infracfg_ao_clk CLK_IFRAO_CQ_DMA>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF5_MD>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF2_AP>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF2_MD>,
			<&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF4_AP>,
			<&infracfg_ao_clk CLK_IFRAO_CCIF4_MD>,
			<&infracfg_ao_clk CLK_IFRAO_RG_MMW_DPMAIF26M_CK>,
			<&infracfg_ao_clk CLK_IFRAO_RG_MEM_SUB_CK>,
			<&infracfg_ao_clk CLK_IFRAO_AES_TOP0>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_0>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_1>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_2>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_3>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_4>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_5>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_6>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_7>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_8>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_9>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_10>,
			<&infracfg_ao_clk CLK_IFRAO_I2C_DUMMY_11>,
			<&infracfg_ao_clk CLK_IFRAOP_DCM_RG_FORCE>;
	};

	disable-unused-clk-vlp_cksys {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&vlp_cksys_clk CLK_VLP_CK_SCP_SEL>,
			<&vlp_cksys_clk CLK_VLP_CK_PWM_VLP_SEL>,
			<&vlp_cksys_clk CLK_VLP_CK_AXI_VLP_SEL>,
			<&vlp_cksys_clk CLK_VLP_CK_DBGAO_26M_SEL>,
			<&vlp_cksys_clk CLK_VLP_CK_SRCK_SEL>,
			<&vlp_cksys_clk CLK_VLP_CK_SRAMRC_SEL>;
	};

	disable-unused-clk-topckgen {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV0>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV1>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV2>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV3>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV4>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIVB>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV5>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV6>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV7>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV8>,
			<&topckgen_clk CLK_TOP_APLL12_CK_DIV9>,
			<&topckgen_clk CLK_TOP_AXI_SEL>,
			<&topckgen_clk CLK_TOP_AXIP_SEL>,
			<&topckgen_clk CLK_TOP_DISP0_SEL>,
			<&topckgen_clk CLK_TOP_MDP0_SEL>,
			<&topckgen_clk CLK_TOP_MMINFRA_SEL>,
			<&topckgen_clk CLK_TOP_MMUP_SEL>,
			<&topckgen_clk CLK_TOP_CAMTG_SEL>,
			<&topckgen_clk CLK_TOP_CAMTG2_SEL>,
			<&topckgen_clk CLK_TOP_CAMTG3_SEL>,
			<&topckgen_clk CLK_TOP_CAMTG4_SEL>,
			<&topckgen_clk CLK_TOP_UART_SEL>,
			<&topckgen_clk CLK_TOP_MSDC_0P_MACRO_SEL>,
			<&topckgen_clk CLK_TOP_MSDC50_0_HCLK_SEL>,
			<&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
			<&topckgen_clk CLK_TOP_AES_MSDCFDE_SEL>,
			<&topckgen_clk CLK_TOP_MSDC_MACRO_SEL>,
			<&topckgen_clk CLK_TOP_MSDC30_1_SEL>,
			<&topckgen_clk CLK_TOP_AUDIO_SEL>,
			<&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,
			<&topckgen_clk CLK_TOP_DISP_PWM_SEL>,
			<&topckgen_clk CLK_TOP_USB_TOP_SEL>,
			<&topckgen_clk CLK_TOP_USB_XHCI_SEL>,
			<&topckgen_clk CLK_TOP_SENINF_SEL>,
			<&topckgen_clk CLK_TOP_SENINF1_SEL>,
			<&topckgen_clk CLK_TOP_SENINF2_SEL>,
			<&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>,
			<&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>,
			<&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>,
			<&topckgen_clk CLK_TOP_U_SEL>,
			<&topckgen_clk CLK_TOP_AUD_1_SEL>,
			<&topckgen_clk CLK_TOP_AUD_2_SEL>,
			<&topckgen_clk CLK_TOP_DPMAIF_MAIN_SEL>,
			<&topckgen_clk CLK_TOP_VENC_SEL>,
			<&topckgen_clk CLK_TOP_VDEC_SEL>,
			<&topckgen_clk CLK_TOP_PWM_SEL>,
			<&topckgen_clk CLK_TOP_AUDIO_H_SEL>,
			<&topckgen_clk CLK_TOP_MCUPM_SEL>,
			<&topckgen_clk CLK_TOP_IMG1_SEL>,
			<&topckgen_clk CLK_TOP_IPE_SEL>,
			<&topckgen_clk CLK_TOP_CAM_SEL>,
			<&topckgen_clk CLK_TOP_CAMTM_SEL>,
			<&topckgen_clk CLK_TOP_MSDC_1P_RX_SEL>,
			<&topckgen_clk CLK_TOP_NFI1X_SEL>,
			<&topckgen_clk CLK_TOP_DBI_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S3_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S6_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S7_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S8_MCK_SEL>,
			<&topckgen_clk CLK_TOP_APLL_I2S9_MCK_SEL>;
	};

	disable-unused-clk-apmixedsys {
		compatible = "mediatek,clk-disable-unused";
		clocks =
			<&apmixedsys_clk CLK_APMIXED_ARMPLL_LL>,
			<&apmixedsys_clk CLK_APMIXED_ARMPLL_BL>,
			<&apmixedsys_clk CLK_APMIXED_CCIPLL>,
			<&apmixedsys_clk CLK_APMIXED_MAINPLL>,
			<&apmixedsys_clk CLK_APMIXED_UNIVPLL>,
			<&apmixedsys_clk CLK_APMIXED_MSDCPLL>,
			<&apmixedsys_clk CLK_APMIXED_MMPLL>,
			<&apmixedsys_clk CLK_APMIXED_TVDPLL>,
			<&apmixedsys_clk CLK_APMIXED_APLL1>,
			<&apmixedsys_clk CLK_APMIXED_APLL2>,
			<&apmixedsys_clk CLK_APMIXED_MPLL>,
			<&apmixedsys_clk CLK_APMIXED_IMGPLL>;
	};

	disable-unused-pd-ufs0_dormant {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_UFS0_DORMANT>;
	};

	disable-unused-pd-audio {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_AUDIO>;
	};

	disable-unused-pd-isp_dip1 {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_DIP1>;
	};

	disable-unused-pd-isp_ipe {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_ISP_IPE>;
	};

	disable-unused-pd-vde0 {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_VDE0>;
	};

	disable-unused-pd-ven0 {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_VEN0>;
	};

	disable-unused-pd-cam_main {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_MAIN>;
	};

	disable-unused-pd-cam_suba {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBA>;
	};

	disable-unused-pd-cam_subb {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_CAM_SUBB>;
	};

	disable-unused-pd-disp {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_DISP>;
	};

	disable-unused-pd-mm_infra {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_INFRA>;
	};

	disable-unused-pd-mm_proc_dormant {
		compatible = "mediatek,scpsys-disable-unused";
		power-domains = <&scpsys MT6835_POWER_DOMAIN_MM_PROC_DORMANT>;
	};
};